KR20010001447A - A forming method for field oxide of semiconductor device - Google Patents
A forming method for field oxide of semiconductor device Download PDFInfo
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- KR20010001447A KR20010001447A KR1019990020669A KR19990020669A KR20010001447A KR 20010001447 A KR20010001447 A KR 20010001447A KR 1019990020669 A KR1019990020669 A KR 1019990020669A KR 19990020669 A KR19990020669 A KR 19990020669A KR 20010001447 A KR20010001447 A KR 20010001447A
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000002955 isolation Methods 0.000 claims abstract description 50
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract 2
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 특히 트렌치를 사용하는 소자분리공정에서 트렌치의 측벽에 질화막 스페이서를 형성한 다음, 상기 트렌치를 매립하는 소자분리막을 형성한 후 상기 질화막 스페이서를 제거하여 트렌치와 반도체기판 간에 틈을 형성함으로써 후속 산화공정시 소자분리막과 반도체기판의 계면간에 스트레스가 발생하는 것을 방지하는 반도체소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and in particular, in the device isolation process using a trench, a nitride spacer is formed on sidewalls of the trench, and then the nitride spacer is formed after the device isolation film is formed to fill the trench. By forming a gap between the trench and the semiconductor substrate to prevent the occurrence of stress between the interface between the device isolation layer and the semiconductor substrate during the subsequent oxidation process.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.
일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.
그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method has a limitation in that it is applied to a giga DRAM device due to a problem of thinning an isolation layer and a buzz big phenomenon.
또한, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워 질 것이다.In addition, the trench isolation process is difficult to bury the trench region as the design rule is reduced as well as the complexity of the process, it will be difficult to apply the trench isolation process when the design rule approaches 0.1 ㎛.
이하, 첨부된 도면을 참고로 하여 종래기술을 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in the prior art.
도 1 은 종래기술에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도이다.1 is a cross-sectional view illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.
먼저, 반도체기판(11) 상부에 패드산화막(도시안됨)과 질화막(도시안됨)의 적층구조를 형성하고, 상기 질화막 상부에 소자분리 영역으로 예정된 부분을 노출시키는 감광막 패턴(도시안됨)을 형성한다.First, a stacked structure of a pad oxide film (not shown) and a nitride film (not shown) is formed on the semiconductor substrate 11, and a photoresist pattern (not shown) is formed on the nitride film to expose a predetermined portion as an isolation region. .
다음, 상기 감광막 패턴을 식각마스크로 사용하여 상기 적층구조 및 소정 두께의 반도체기판(11)을 식각하여 트렌치를 형성한다.Next, the trench is formed by etching the stacked structure and the semiconductor substrate 11 having a predetermined thickness using the photoresist pattern as an etching mask.
그 다음, 상기 감광막 패턴을 제거한다.Then, the photoresist pattern is removed.
다음, 상기 트렌치의 표면을 열산화시켜 희생산화막(도시안됨)을 성장시킨 후 습식식각을 실시하여 제거함으로써 상기 트렌치 형성공정시 발생된 상기 트렌치 표면의 결함을 제거한다.Next, the surface of the trench is thermally oxidized to grow a sacrificial oxide film (not shown), followed by wet etching to remove defects on the trench surface generated during the trench formation process.
그 후, 다시 열산화공정을 실시하여 상기 트렌치의 표면에 산화막(도시안됨)을 형성한다.Thereafter, a thermal oxidation process is performed again to form an oxide film (not shown) on the surface of the trench.
다음, 전체표면 상부에 상기 트렌치를 매립하는 산화막을 형성한다.Next, an oxide film filling the trench is formed on the entire surface.
그 다음, 상기 산화막을 상기 질화막을 식각방지막으로 사용하여 화학적기계적연마(chemical mechanical polishing, 이하 CMP 라함)공정을 실시하여 제거하여 소자분리막(17)을 형성한다.Then, the oxide film is removed by performing a chemical mechanical polishing (CMP) process using the nitride film as an etch stop layer to form an isolation layer 17.
다음, 상기 질화막을 제거한 다음, 소자분리막과 반도체기판(11)과의 단차를 줄이기 위하여 상기 소자분리막을 습식식각방법으로 소정 두께 제거한 후, 후속공정을 실시한다.Next, after the nitride film is removed, the thickness of the device isolation film is removed by a wet etching method to reduce the step difference between the device isolation film and the semiconductor substrate 11, and then a subsequent process is performed.
상기와 같이 종래기술에 따른 반도체소자의 소자분리막 형성방법은, 트렌치 매립후 각종 산화공정시 소자분리막과 인접해있는 반도체기판이 산화되는데, 이때 상기 트렌치와 반도체기판 간에 산화막의 성장틈이 없기 때문에 과도한 스트레스가 유발되고, 도 1에 도시된 바와 같이 스트레스에 의한 기판결함(15)으로 인하여 접합누설전류(junction leakage current)가 증가하여 소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, in the method of forming a device isolation film of a semiconductor device according to the prior art, a semiconductor substrate adjacent to a device isolation film is oxidized during various oxidation processes after trench filling, since there is no growth gap between the trench and the semiconductor substrate. As a result of stress, as shown in FIG. 1, the junction defect current increases due to the substrate defect 15 due to stress, thereby deteriorating the characteristics and reliability of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 트렌치를 사용하는 소자분리공정에서 소자분리막과 반도체기판 간에 틈을 형성하여 후속 산화공정시 상기 소자분리막과 반도체기판 간에 스트레스가 발생하는 것을 방지하는 반도체소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, to form a gap between the device isolation film and the semiconductor substrate in the device isolation process using a trench to prevent the stress between the device isolation film and the semiconductor substrate during the subsequent oxidation process It is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device.
도 1 은 종래기술에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.1 is a cross-sectional view showing a device isolation film forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.
〈 도면의 주요부분에 대한 부호의 설명 〉<Description of reference numerals for the main parts of the drawings>
11, 21 : 반도체기판 13, 23 : 패드산화막11, 21: semiconductor substrate 13, 23: pad oxide film
15 : 스트레스에 의한 기판결함 17, 31 : 소자분리막15: substrate defect due to stress 17, 31: device isolation film
25 : 제1질화막 패턴 27 : 트렌치25 first nitride film pattern 27 trench
29 : 제2질화막 스페이서 32 : 틈29: second nitride film spacer 32: gap
33 : 산화막33: oxide film
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리막 형성방법은,Device isolation film forming method of a semiconductor device according to the present invention for achieving the above object,
반도체기판에 소자분리막으로 예정되는 부분을 노출시키는 제1절연막 패턴을 형성하고, 상기 제1절연막 패턴을 식각마스크로 상기 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming a trench on the semiconductor substrate by exposing a first insulating layer pattern to expose a predetermined portion of the device isolation layer, and etching the semiconductor substrate using the first insulating layer pattern as an etching mask;
상기 트렌치 및 제1절연막 패턴의 측벽에 제2절연막 스페이서를 형성하는 공정과,Forming a second insulating film spacer on sidewalls of the trench and the first insulating film pattern;
상기 구조 전체표면에 고밀도 플라즈마 화학기상증착방법으로 제3절연막을 형성하는 공정과,Forming a third insulating film on the entire surface of the structure by a high density plasma chemical vapor deposition method;
상기 제3절연막을 화학적 기계적 연마방법으로 제거하여 상기 트렌치를 매립하는 소자분리막을 형성하는 공정과,Removing the third insulating layer by a chemical mechanical polishing method to form an isolation layer filling the trench;
상기 제1질화막 패턴을 제거하는 동시에 상기제2질화막 스페이서를 제거하여 상기 소자분리막과 반도체기판 간에 틈을 형성하는 공정과,Removing a gap between the device isolation layer and the semiconductor substrate by removing the first nitride layer pattern and simultaneously removing the second nitride layer spacer;
상기 구조를 열처리하는 공정과,Heat-treating the structure;
후속 산화공정에서 상기 틈이 매립되는 공정을 포함하는 것을 특징으로 한다.And a step of filling the gap in a subsequent oxidation step.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.
먼저, 반도체기판(21) 상부에 패드산화막과 제1질화막의 적층구조를 형성하고, 상기 제1질화막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막 패턴(도시안됨)을 형성한다. 이때, 상기 패드산화막은 50 ∼ 300Å 두께로 형성하고, 상기 제1질화막은 1000 ∼ 3000Å 두께로 형성한다.First, a stack structure of a pad oxide film and a first nitride film is formed on the semiconductor substrate 21, and a photoresist pattern (not shown) is formed on the first nitride film to expose a portion intended to be an isolation region. In this case, the pad oxide film is formed to a thickness of 50 to 300 kPa, and the first nitride film is formed to a thickness of 1000 to 3000 kPa.
다음, 상기 감광막 패턴을 식각마스크로 사용하여 상기 적층구조를 식각하여 소자분리영역으로 예정되는 반도체기판(21)을 노출시키는 제1질화막 패턴(25)과 패드산화막 패턴(23)을 형성한 후, 상기 감광막 패턴을 제거한다.Next, after forming the first nitride layer pattern 25 and the pad oxide layer pattern 23 exposing the semiconductor substrate 21 to be an element isolation region by etching the stack structure using the photoresist pattern as an etching mask, The photosensitive film pattern is removed.
그 다음, 상기 제1질화막 패턴(25)을 식각마스크로 상기 반도체기판(21)을 식각하여 1000 ∼ 3000Å 깊이의 트렌치(27)를 형성한다.Next, the semiconductor substrate 21 is etched using the first nitride film pattern 25 as an etch mask to form a trench 27 having a depth of 1000 to 3000 Å.
그 후, 상기 트렌치(27)의 표면을 열산화시켜 희생산화막(도시안됨)을 성장시킨 후 습식식각을 실시하여 제거하는 희생산화공정을 실시함으로써 상기 트렌치(27) 형성공정시 발생된 상기 트렌치(27) 표면의 결함을 제거한다.Thereafter, the surface of the trench 27 is thermally oxidized to grow a sacrificial oxide film (not shown), and then a sacrificial oxidation process is performed by performing wet etching to remove the trench. 27) Remove surface defects.
다음, 전체표면 상부에 10 ∼ 100Å 두께의 제2질화막을 형성하고, 상기 제2질화막을 전면식각하여 상기 트렌치(27) 및 적층구조의 측벽에 제2질화막 스페이서(29)를 형성한다.Next, a second nitride film having a thickness of 10 to 100 Å is formed on the entire surface, and a second nitride film spacer 29 is formed on the sidewalls of the trench 27 and the laminated structure by etching the entire surface of the second nitride film.
이때, 상기 제2질화막은 전면식각하지 않고 그대로 사용할 수도 있다. (도 2a참조)In this case, the second nitride film may be used as it is without etching the entire surface. (See Figure 2A)
그 다음, 전체표면 상부에 고밀도 플라즈마 화학기상증착(high density plasma chemical vapor deposition, HDP-CVD)방법으로 3000 ∼ 10000Å 두께의 산화막을 형성하고, 상기 제1질화막 패턴(25)을 식각장벽으로 사용하여 화학적 기계적 연마(chemical mechanical polishing, CMP)방법으로 상기 산화막을 제거함으로써 상기 트렌치(27)를 매립하는 소자분리막(31)을 형성한다. (도 2b참조)Then, an oxide film having a thickness of 3000 to 10000 kPa is formed on the entire surface by high density plasma chemical vapor deposition (HDP-CVD), and the first nitride film pattern 25 is used as an etch barrier. By removing the oxide film by a chemical mechanical polishing (CMP) method, an isolation layer 31 filling the trench 27 is formed. (See Figure 2b)
다음, 상기 제1질화막 패턴(25)을 인산용액을 이용한 습식식각방법으로 제거한다. 이때, 상기 제2질화막 스페이서(29)도 동시에 제거되어 상기 소자분리막(31)과 반도체기판(21)의 계면에 소정 두께의 틈(32)을 형성한다.Next, the first nitride film pattern 25 is removed by a wet etching method using a phosphoric acid solution. In this case, the second nitride film spacer 29 is also simultaneously removed to form a gap 32 having a predetermined thickness at an interface between the device isolation layer 31 and the semiconductor substrate 21.
한편, 상기 제2질화막 스페이서(29)를 형성하지 않고 제2질화막을 그대로 사용한 경우에는 상기 트렌치(27)의 하부에 제2질화막이 그대로 남아있게 된다. (도 2c참조)On the other hand, when the second nitride film is used as it is without forming the second nitride film spacer 29, the second nitride film remains in the lower portion of the trench 27. (See FIG. 2C)
다음, 상기 구조를 1000 ∼ 1200℃에서 30 ∼ 60분간 열처리한다.Next, the structure is heat-treated at 1000 to 1200 ° C. for 30 to 60 minutes.
그 다음, 희생산화공정, 게이트 산화막형성공정 등의 후속공정을 실시하게 되면, 상기 소자분리막(31)과 인접하고 있는 반도체기판(21)이 산화되어 상기 틈(32)을 메우는 산화막(33)이 형성된다. (도 2d참조)Subsequently, a subsequent process such as a sacrificial oxidation process or a gate oxide film forming process is performed, whereby the semiconductor substrate 21 adjacent to the device isolation layer 31 is oxidized to fill the gap 32. Is formed. (See FIG. 2D)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 트렌치를 이용한 소자분리공정에서 반도체기판 상부에 소자분리영역을 노출시키는 절연막 패턴을 형성하고, 상기 절연막 패턴을 식각마스크로 사용하여 트렌치를 형성한 다음, 상기 트렌치의 측벽에 절연막 스페이서를 형성한 후, 상기 트렌치를 매립하는 소자분리막을 형성한 다음, 상기 절연막 패턴을 제거하는 동시에 상기 절연막 스페이서를 제거하여 상기 소자분리막과 반도체기판 간에 틈을 형성함으로써 후속공정시 상기 소자분리막과 인접하고 있는 반도체기판이 산화되어 스트레스를 발생시키는 것을 완화하여 접합누설전류를 감소시켜 소자의 특성 및 신뢰성을 향상시키고, 그에 따른 반도체소자의 고집적화를 유리하게 하는 이점이 있다.As described above, in the method of forming a device isolation film of a semiconductor device according to the present invention, an insulating film pattern for exposing a device isolation region is formed on an upper portion of a semiconductor substrate in a device isolation process using a trench, and the insulating film pattern is used as an etching mask. After the trench is formed, an insulating film spacer is formed on the sidewalls of the trench, and then an isolation layer for filling the trench is formed. Then, the insulation layer pattern is removed and the insulation spacer is removed to form a gap between the isolation layer and the semiconductor substrate. By forming a gap, the semiconductor substrate adjacent to the device isolation film is oxidized in a subsequent process to reduce stress, thereby reducing the junction leakage current, thereby improving device characteristics and reliability, and conducive to high integration of the semiconductor device. This has the advantage.
Claims (9)
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