KR20010001373A - A method for forming gate electrode of semiconductor device - Google Patents
A method for forming gate electrode of semiconductor device Download PDFInfo
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- KR20010001373A KR20010001373A KR1019990020530A KR19990020530A KR20010001373A KR 20010001373 A KR20010001373 A KR 20010001373A KR 1019990020530 A KR1019990020530 A KR 1019990020530A KR 19990020530 A KR19990020530 A KR 19990020530A KR 20010001373 A KR20010001373 A KR 20010001373A
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Abstract
Description
본 발명은 반도체소자의 게이트전극 형성방법에 관한 것으로, 특히 게이트전극 측벽에 스페이서를 형성할때 반도체기판이 손상되는 현상을 최소화시킬 수 있는 기술에 관한 것이다.The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly, to a technique capable of minimizing a phenomenon in which a semiconductor substrate is damaged when a spacer is formed on a sidewall of a gate electrode.
일반적으로 트랜지스터는 다결정실리콘으로 게이트전극을 형성하고 불순물 이온주입공정에 의한 소오스/드레인 접합영역으로 이루어졌다.In general, a transistor is formed of a source / drain junction region by a gate electrode formed of polycrystalline silicon and an impurity ion implantation process.
그러나, 반도체소자가 고집적화됨에 따라 이웃한 게이트전극 및 도전배선 들과의 절연 특성이 저하되는 단점이 유발되었다.However, as semiconductor devices have been highly integrated, insulation characteristics with neighboring gate electrodes and conductive wirings are degraded.
이들을 해결하기 위하여 상기 게이트전극 측벽에 절연막 스페이서를 형성하였다.In order to solve these problems, insulating film spacers are formed on the sidewalls of the gate electrodes.
이때, 상기 절연막 스페이서의 식각공정시에 혹은 후에 게이트절연막을 함께 건식식각 제거하는 경우에는 상기 반도체기판 표면이 과도식각되어 손상되는 현상이 유발되는 문제점이 있다. 반면에, 절연막 스페이서의 식각공정시에 게이트 절연막을 식각하지 않고, 별도의 후속공정에서 습식식각에 의해 제거하는 경우에는 게이트 전극 하부의 게이트 산화막 측면까지 과도 식각되어 게이트전극의 특성을 열화시키는 문제점이 발생된다. 여기서, 상기 이방성식각공정시 수반되는 과도식각공정은 상기 반도체기판이 상부로 부터 100 Å 두께 이하로 형성되도록 실시한다.In this case, when the gate insulating layer is dry-etched together during or after the etching process of the insulating layer spacer, the surface of the semiconductor substrate may be excessively etched and damaged. On the other hand, when the gate insulating film is not etched during the etching process of the insulating film spacer and is removed by wet etching in a subsequent process, the gate electrode is excessively etched to the side of the gate oxide film under the gate electrode, thereby deteriorating the characteristics of the gate electrode. Is generated. Here, the transient etching process involved in the anisotropic etching process is performed so that the semiconductor substrate is formed to a thickness of less than 100 Å from the top.
도 1 은 종래기술에 따른 반도체소자의 게이트전극 형성방법을 도시한 단면도로서, 기판 표면의 상기 게이트산화막을 습식방법으로 제거하는 경우 단점이 유발되는 현상을 도시한 것이다.1 is a cross-sectional view illustrating a method of forming a gate electrode of a semiconductor device according to the related art, and illustrates a phenomenon in which a disadvantage is caused when the gate oxide film on a surface of a substrate is removed by a wet method.
먼저, 반도체기판(31) 상부에 게이트산화막(33), 다결정실리콘(35) 및 마스크절연막(37)을 적층하고 이를 게이트전극 마스크를 이용한 식각공정으로 식각하여 게이트전극을 형성한다.First, a gate oxide layer 33, a polysilicon 35, and a mask insulating layer 37 are stacked on the semiconductor substrate 31 and etched by an etching process using a gate electrode mask to form a gate electrode.
그리고, 전체표면상부에 질화막(39)을 일정두께 증착하고 이를 이방성식각하여 상기 게이트전극 측벽에 질화막(39) 스페이서를 형성한다.In addition, a nitride film 39 is deposited on the entire surface and anisotropically etched to form a nitride film 39 spacer on the sidewall of the gate electrode.
그리고, 상기 게이트전극 하부를 제외한 반도체기판 표면의 게이트산화막(33)을 습식방법으로 제거한다.Then, the gate oxide film 33 on the surface of the semiconductor substrate except for the lower portion of the gate electrode is removed by a wet method.
이때, 상기 게이트전극 하부에 형성된 게이트산화막(33)이 측면식각되어 게이트전극의 특성을 열화시키는 단점이 유발된다. (도 1)At this time, the gate oxide layer 33 formed on the lower portion of the gate electrode is side-etched to deteriorate the characteristics of the gate electrode. (Figure 1)
상기한 바와같이 종래기술에 따른 반도체소자의 게이트전극 형성방법은, 게이트전극 측벽에 절연막 스페이서를 형성할때 상기 반도체기판의 손상을 100 Å 이하로 되도록 실시하기 어렵고 게이트절연막이 유실되는 현상으로 인하여 게이트전극의 특성이 열화되는 문제점이 있다.As described above, the gate electrode forming method of the semiconductor device according to the related art is difficult to perform the damage of the semiconductor substrate to 100 Å or less when the insulating film spacer is formed on the sidewall of the gate electrode, and the gate insulating film is lost due to the phenomenon that the gate insulating film is lost. There is a problem that the characteristics of the electrode is deteriorated.
본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 질화막 증착공정, 제1건식식각공정, 산화막 증착공정, 제2건식식각공정 및 습식식각공정을 이용하여 기판의 손상없이 게이트전극 측벽에 절연막 스페이서를 형성함으로써 게이트전극의 특성 열화없이 반도체소자의 고집적화를 가능하게 하는 반도체소자의 게이트전극 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the insulating film spacer on the sidewall of the gate electrode without damaging the substrate by using the nitride film deposition process, the first dry etching process, the oxide film deposition process, the second dry etching process and the wet etching process It is an object of the present invention to provide a method for forming a gate electrode of a semiconductor device that enables high integration of the semiconductor device without deteriorating the characteristics of the gate electrode.
도 1 는 종래기술에 따른 반도체소자의 게이트전극 형성방법을 도시한 단면도.1 is a cross-sectional view showing a gate electrode forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 게이트전극 형성방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
〈 도면의 주요부분에 대한 부호의 설명 〉<Description of reference numerals for the main parts of the drawings>
11,31 : 반도체기판 13,33 : 게이트산화막11,31: semiconductor substrate 13,33: gate oxide film
15,35 : 다결정실리콘막 17,37 : 마스크산화막15,35 polysilicon film 17,37 mask oxide film
19,39 : 질화막 스페이서 21 : 산화막19,39: nitride film spacer 21: oxide film
ⓐ : 게이트산화막 손실 부분Ⓐ: gate oxide loss
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 게이트전극 형성방법은,In order to achieve the above object, the gate electrode forming method of a semiconductor device according to the present invention,
반도체기판 상부에 게이트절연막, 다결정실리콘 및 마스크절연막 적층구조의 게이트전극을 형성하는 공정과,Forming a gate electrode having a gate insulating film, a polysilicon and a mask insulating film stacked structure on the semiconductor substrate;
상기 게이트전극 측벽에 질화막 스페이서를 형성하는 공정과,Forming a nitride film spacer on the sidewalls of the gate electrode;
전체표면상부에 산화막을 일정두께 형성하는 공정과,Forming a certain thickness of an oxide film on the entire surface;
상기 산화막을 이방성식각하여 상기 질화막 스페이서 측벽에 산화막 스페이서를 형성하는 공정과,Anisotropically etching the oxide film to form an oxide film spacer on sidewalls of the nitride film spacer;
상기 산화막 스페이서와 상기 반도체기판 표면에 남아있는 산화막 및 게이트절연막을 습식방법으로 제거하여 측벽에 질화막 스페이서가 형성된 게이트전극을 형성하는 공정을 포함하는 것을 특징으로한다.And removing the oxide film and the gate insulating film remaining on the surface of the semiconductor substrate by a wet method to form a gate electrode having the nitride film spacer formed on the sidewalls.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 게이트전극 형성방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 게이트산화막(13), 다결정실리콘막(15) 및 마스크산화막(17)을 적층한다.First, the gate oxide film 13, the polycrystalline silicon film 15, and the mask oxide film 17 are stacked on the semiconductor substrate 11.
그리고, 상기 적층구조 상부에 게이트전극 마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(도시안됨)을 형성한다.A photoresist pattern (not shown) is formed on the stack structure by an exposure and development process using a gate electrode mask (not shown).
그리고, 이를 마스크로하여 상기 반도체기판(11)을 노출시키도록 상기 적층구조를 식각하고 상기 감광막패턴을 제거함으로써 게이트전극을 형성한다.The gate electrode is formed by etching the stacked structure and removing the photoresist pattern so that the semiconductor substrate 11 is exposed as a mask.
그 다음, 상기 게이트전극을 포함한 전체표면상부에 질화막(19)을 일정두께 형성한다.Next, a nitride film 19 is formed on the entire surface including the gate electrode.
그리고, 상기 질화막(19)을 제1건식식각하되, 이방성식각하여 질화막(19) 스페이서를 형성한다.The nitride film 19 is first dry etched, but is anisotropically etched to form the nitride film 19 spacer.
이때, 상기 이방성식각공정은 상기 질화막(19)과 게이트산화막(13)의 식각선택비 차이를 10 이상으로 하는 조건에서 실시하여 상기 질화막(19)만이 식각될 수 있도록 한다. (도 2a)In this case, the anisotropic etching process is performed under the condition that the difference in etching selectivity between the nitride film 19 and the gate oxide film 13 is 10 or more so that only the nitride film 19 can be etched. (FIG. 2A)
그 다음, 전체표면상부에 산화막(21)을 일정두께 형성한다. 이때, 상기 산화막(21)은 게이트산화막(13)보다 두껍게 형성한다. (도 2b)Then, an oxide film 21 is formed on the entire surface at a constant thickness. In this case, the oxide film 21 is formed thicker than the gate oxide film 13. (FIG. 2B)
그리고, 상기 산화막(21)을 제2건식식각하되, 이방성식각하여 상기 게이트전극 측벽에 질화막(19) 스페이서 측벽에 산화막(21) 스페이서를 형성한다. (도 2c)A second dry etching of the oxide layer 21 is performed, and anisotropic etching is performed to form an oxide layer 21 spacer on the sidewall of the nitride layer 19 on the sidewall of the gate electrode. (FIG. 2C)
그리고, 상기 반도체기판(11) 상부의 산화막(21) 스페이서를 습식방법으로 제거하여 측벽에 질화막(19) 스페이서가 구비된 게이트전극을 형성한다.In addition, the oxide layer 21 spacer on the semiconductor substrate 11 is removed by a wet method to form a gate electrode having the nitride layer 19 spacer on the sidewall.
이때, 상기 산화막(21)은 상기 반도체기판(11) 상부에서 이방성식각공정시 기판의 손상을 방지하고, 상기 질화막(19) 스페이서 측벽에 형성되어 게이트전극 하부로 게이트산화막(13)이 측면식각되는 현상을 방지하는 역할을 한다. (도 2d)In this case, the oxide film 21 prevents damage to the substrate during the anisotropic etching process on the semiconductor substrate 11 and is formed on the spacer sidewall of the nitride film 19 so that the gate oxide film 13 is etched laterally under the gate electrode. It prevents the phenomenon. (FIG. 2D)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 게이트전극 형성방법은, 게이트전극 측벽에 질화막 스페이서를 형성하고 전체표면상부에 산화막을 형성한 다음, 이를 이방성식각하고 산화막을 습식방법으로 제거함으로써 상기 게이트전극 및 반도체기판의 특성 열화없이 게이트전극을 형성할 수 있어 반도체소자의 고집적화를 가능하게 하는 효과를 갖는다.As described above, in the method of forming a gate electrode of a semiconductor device according to the present invention, a nitride spacer is formed on a sidewall of a gate electrode, an oxide film is formed on an entire surface, and then anisotropically etched and the oxide film is removed by a wet method. Since the gate electrode can be formed without deteriorating the characteristics of the electrode and the semiconductor substrate, the semiconductor device has an effect of enabling high integration of the semiconductor device.
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