KR20000075048A - Method of manufacturing chip stacked package in wafer level - Google Patents
Method of manufacturing chip stacked package in wafer level Download PDFInfo
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- KR20000075048A KR20000075048A KR1019990019383A KR19990019383A KR20000075048A KR 20000075048 A KR20000075048 A KR 20000075048A KR 1019990019383 A KR1019990019383 A KR 1019990019383A KR 19990019383 A KR19990019383 A KR 19990019383A KR 20000075048 A KR20000075048 A KR 20000075048A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
본 발명은 서로 다른 반도체 칩들을 적층하여 단일 패키지로 제조하는 적층 칩 패키지 제조방법에 관한 것이며, 더욱 구체적으로는 일차적으로 제조된 각 반도체 칩들을 웨이퍼 레벨에서 배선을 재배열한 후 플립 본딩 기술을 이용하여 적층시키는 것을 특징으로 하는 웨이퍼 레벨에서의 적층 칩 패키지 제조방법에 관한 것이다.The present invention relates to a stacked chip package manufacturing method of stacking different semiconductor chips into a single package, and more specifically, by using flip bonding technology after rearranging wires at a wafer level for each of the semiconductor chips manufactured first. The present invention relates to a method for manufacturing a laminated chip package at a wafer level, characterized in that the lamination is performed.
반도체 칩들을 적층하여 단일 패키지로 제조하는 적층 칩 패키지 기술은 이미 일차적으로 제조된 반도체 칩들을 이용하여 반도체 패키지 용량을 확장시키거나 반도체 패키지의 용량을 기준으로 실장영역을 최소화할 수 있는 등의 이점을 갖기 때문에 여러 가지 형태로 개발되어 왔다.The stacked chip package technology, in which semiconductor chips are stacked and manufactured in a single package, has advantages such as extending semiconductor package capacity or minimizing a mounting area based on semiconductor package capacity by using semiconductor chips that are already manufactured first. It has been developed in many forms.
도 1a 내지 도 1c는 기존의 적층 칩 패키지들의 구조를 간략하게 도시한 단면도들이며, 이들 도면을 설명하면 다음과 같다.1A to 1C are cross-sectional views briefly illustrating structures of existing stacked chip packages, and these drawings will be described below.
도 1a는 일반적인 반도체 패키지들(10)을 차례로 적층시킨 모습이며, 도 1b는 성형수지로 성형되기 전의 리드 프레임 상태에서 반도체 칩들(22, 24)이 적층된 후 단일 패키지(20)로 성형된 모습이고, 도 1c는 리드 프레임 등을 중심으로 두 개 이상의 반도체 칩들(32, 34)이 활성면을 마주 보며 적층된 패키지(30)의 모습을 도시한다.FIG. 1A is a view of stacking general semiconductor packages 10 in sequence, and FIG. 1B is formed of a single package 20 after stacking the semiconductor chips 22 and 24 in a lead frame state before molding the molding resin. 1C illustrates a package 30 in which two or more semiconductor chips 32 and 34 are stacked facing the active surface with respect to a lead frame or the like.
이러한 기존의 적층 칩 패키지들은 일차적으로 완성된 후 웨이퍼에서 분리된 개개의 반도체 칩들을 리드 프레임 등과 같은 보조수단을 통해 적층시키고 외부 기판에 실장하는 형태로 이루어져 있다. 따라서, 이들 적층 칩 패키지들의 제조방법은 개개의 반도체 칩들을 제조하는 웨이퍼 제조공정(Wafer Fabrication)과 웨이퍼에서 개개의 반도체 칩들을 분리한 후 최종 제품인 반도체 패키지로 조립하는 패키지 조립공정(Assembly)을 모두 포함한다.These conventional stacked chip packages are primarily formed by stacking individual semiconductor chips separated from a wafer through auxiliary means such as lead frames and mounting them on an external substrate. Therefore, the method of manufacturing these stacked chip packages includes both a wafer fabrication process of manufacturing individual semiconductor chips and a package assembly process of separating individual semiconductor chips from a wafer and then assembling the final product into a semiconductor package. Include.
이와 같이 기존의 적층 칩 패키지 제조방법이 웨이퍼 제조공정과 패키지 조립공정을 모두 포함함에 따라, 최종 제품을 완성하기까지의 작업시간(Throughput)의 증가와 공정의 복잡화로 인한 신뢰성의 저하 및 공정비용의 증가 등을 가져오게 되며, 결국 고가의 제품을 생산하게 됨으로써 가격 경쟁력이 약화되는 등의 단점을 가져올 수 있다.As a conventional method of manufacturing a stacked chip package includes both a wafer manufacturing process and a package assembling process, reliability and degradation of process cost due to an increase in the throughput and complexity of the process are required. It may lead to an increase, and eventually to produce an expensive product may lead to a disadvantage, such as a weak price competitiveness.
본 발명의 목적은 제조공정과 제조시간을 단축하고 제조비용의 절감할 수 있는 칩 스케일 패키지(CSP) 형태의 웨이퍼 레벨에서의 적층 칩 패키지를 제조하는 제조방법을 제공하는 것이다.An object of the present invention is to provide a manufacturing method for manufacturing a laminated chip package at the wafer level in the form of a chip scale package (CSP) which can shorten the manufacturing process and manufacturing time and reduce the manufacturing cost.
본 발명의 또 다른 목적은 웨이퍼 레벨에서 배선을 재배열시킨 후 플립 본딩 기술을 이용하여 적층시키는 것을 특징으로 하는 웨이퍼 레벨에서의 적층 칩 패키지 제조방법을 제공하는 것이다.It is still another object of the present invention to provide a method for manufacturing a stacked chip package at a wafer level, wherein the wiring is rearranged at the wafer level and then laminated using flip bonding technology.
도 1a 내지 도 1c는 기존의 적층 칩 패키지들을 도시한 단면도,1A to 1C are cross-sectional views illustrating conventional stacked chip packages;
도 2는 본 발명의 일 실시예에 따른 적층 칩 패키지 제조방법을 순차적으로 도시한 순서도,2 is a flowchart sequentially showing a method of manufacturing a stacked chip package according to an embodiment of the present invention;
도 3a 내지 도 3e는 도 2의 순서에 따른 제조공정을 각 단계별로 도시한 공정도,3a to 3e is a process diagram showing each step of the manufacturing process according to the sequence of FIG.
도 4a 내지 도 4d는 웨이퍼 레벨에서 배선을 재배열하는 공정을 순차적으로 도시한 공정 단면도이다.4A through 4D are cross-sectional views sequentially illustrating a process of rearranging wires at a wafer level.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 반도체 패키지 20, 30 : 적층 칩 패키지10: semiconductor package 20, 30: laminated chip package
22, 24, 32, 34 : 반도체 칩 110/130 : 제1/제2 웨이퍼22, 24, 32, 34: semiconductor chip 110/130: first / second wafer
120/140 : 제1/제2 반도체 칩 124 : 범프120/140: first / second semiconductor chip 124: bump
150 : 칩 실장부 152, 162, 242 : 패드150: chip mounting portion 152, 162, 242: pad
160 : 접속부 170 : 솔더 볼160 connection part 170 solder ball
180 : 봉지부 190 : 기판(Substrate)180: encapsulation unit 190: substrate (Substrate)
200 : 웨이퍼 레벨 적층 칩 패키지(WL-Chip Stacked Package)200: WL-Chip Stacked Package
210 : 반도체 칩 212 : 본딩패드210: semiconductor chip 212: bonding pad
220 : 금속기저층(UBM ; Under Barrier Metal)220: Under Barrier Metal (UBM)
230, 250 : 절연막 240 : 금속 배선230, 250: insulating film 240: metal wiring
이러한 목적을 달성하기 위하여 본 발명은 웨이퍼 레벨에서 서로 다른 크기의 제1/제2 반도체 칩들을 적층하여 적층 칩 패키지를 제조하는 방법에 있어서, (a) 제1/제2 반도체 칩들이 각각 형성된 제1/제2 웨이퍼들을 준비하는 단계와; (b) 제1 반도체 칩들 위로 배선을 재배열함으로써 소정의 범프들을 형성하는 단계와; (c) 제2 반도체 칩들 위로 배선을 재배열함으로써 소정의 범프들에 대응하는 범프 패드들이 구비된 칩 실장부와 칩 실장부의 주변으로 볼 패드들이 구비된 접속부를 형성하는 단계와; (d) 제1 반도체 칩들을 개개로 분리한 후 제 2반도체 칩의 칩 실장부 위로 플립 본딩하는 단계와; (e) 제2 반도체 칩의 볼 패드들 위로 솔더 볼들을 형성하는 단계; 및 (f) 제2 반도체 칩들을 개개로 분리하는 단계;를 포함하며, 칩 실장부는 제1 반도체 칩의 크기에 대응하여 형성되고, 솔더 볼들은 제1 반도체 칩이 플립 본딩된 높이보다 큰 직경으로 형성되는 것을 특징으로 하는 웨이퍼 레벨에서의 적층 칩 패키지 제조방법을 제공한다.In order to achieve the above object, the present invention provides a method of manufacturing a stacked chip package by stacking first and second semiconductor chips having different sizes at a wafer level, comprising: (a) forming a first and second semiconductor chips, respectively; Preparing first / second wafers; (b) forming predetermined bumps by rearranging the wiring over the first semiconductor chips; (c) rearranging the wiring over the second semiconductor chips to form a chip mounting portion having bump pads corresponding to predetermined bumps and a connection portion having ball pads around the chip mounting portion; (d) separately separating the first semiconductor chips and flip bonding them onto the chip mounting portion of the second semiconductor chip; (e) forming solder balls over the ball pads of the second semiconductor chip; And (f) separately separating the second semiconductor chips, wherein the chip mounting portion is formed corresponding to the size of the first semiconductor chip, and the solder balls are formed to have a diameter larger than the height at which the first semiconductor chip is flip-bonded. It provides a method for manufacturing a laminated chip package at the wafer level characterized in that it is formed.
이하, 도면을 참조하여 본 발명의 바람직한 실시예들을 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
도 2는 본 발명의 일 실시예에 따른 웨이퍼 레벨에서의 적층 칩 패키지 제조방법을 순차적으로 도시한 순서도이며, 도 3a 내지 도 3e는 도 2의 각 단계를 상세히 도시한 공정도들이다. 도 2 내지 도 3e를 참고로 하여 본 발명에 따른 적층 칩 패키지 제조방법을 설명하면 다음과 같다.2 is a flowchart sequentially illustrating a method of manufacturing a stacked chip package at a wafer level according to an embodiment of the present invention, and FIGS. 3A to 3E are process diagrams illustrating each step of FIG. 2 in detail. Referring to Figures 2 to 3E will be described a method of manufacturing a stacked chip package according to the present invention.
본 발명에 따른 적층 칩 패키지 제조방법은 크게 구분하여 크기가 서로 다른 제1/제2 반도체 칩들이 각각 형성되어 있는 웨이퍼들을 준비하는 단계(40)와, 제1 반도체 칩 위로 소정의 범프를 형성하는 단계(50)와, 제2 반도체 칩 위로 칩 실장부와 접속부를 형성하는 단계(60)와, 제1 반도체 칩들을 개개로 분리하여 제2 반도체 칩들의 각 칩 실장부 위로 플립 본딩하는 단계(70)와, 볼 패드 위로 솔더 볼을 형성하는 단계(80) 및 개개의 적층 칩 패키지로 분리하는 단계(90)를 포함한다.The method for manufacturing a stacked chip package according to the present invention comprises the steps of preparing 40 wafers each having first and second semiconductor chips having different sizes, and forming a predetermined bump on the first semiconductor chip. Step 50, forming a chip mounting portion and a connecting portion over the second semiconductor chip (60), and separating the first semiconductor chips individually and flip bonding over each chip mounting portion of the second semiconductor chips (70) ), Forming a solder ball over the ball pad (80) and separating it into individual stacked chip packages (90).
이를 좀 더 상세히 설명하면 도 3a에 도시된 것처럼 제1 웨이퍼(110)의 제1 반도체 칩들(120)은 플립 본딩할 수 있도록 소정의 범프들(124)이 활성면(122) 위로 형성된 것을 특징으로 하며, 제2 웨이퍼(130)의 제2 반도체 칩들(140)은 도 3b에 도시된 것처럼 제1 반도체 칩(120)의 범프들(124)이 본딩될 수 있도록 범프 패드들(152)이 형성된 칩 실장부(150)와 칩 실장부(150)를 중심으로 주변에 볼 패드들(162)이 형성된 접속부(160)가 형성된 것을 특징으로 한다.In more detail, as shown in FIG. 3A, predetermined bumps 124 are formed on the active surface 122 to flip-bond the first semiconductor chips 120 of the first wafer 110. In addition, the second semiconductor chips 140 of the second wafer 130 are chips in which bump pads 152 are formed to bond the bumps 124 of the first semiconductor chip 120 as illustrated in FIG. 3B. A connection part 160 having ball pads 162 formed around the mounting unit 150 and the chip mounting unit 150 may be formed.
이와 같은 제1/제2 반도체 칩들을 적층하기 위하여, 크기가 작은 제1 반도체 칩들(120)을 제1 웨이퍼(110)로부터 개개로 분리한 후 제2 반도체 칩(140)의 칩 실장부(150) 위로 플립 본딩한다. 제1 반도체 칩들(120)이 플립 본딩된 모습이 도 3c에 평면도로 도시되어 있으며, 제1 반도체 칩(120)이 플립 본딩된 주위로 볼 패드들(162)이 노출된 모습을 알 수 있다.In order to stack the first and second semiconductor chips, the small semiconductor chips 120 may be separated from the first wafer 110, and then the chip mounting unit 150 of the second semiconductor chip 140 may be separated. ) Flip bond over. 3C is a plan view of the flip-bonding of the first semiconductor chips 120, and the ball pads 162 are exposed around the flip-bonding of the first semiconductor chip 120.
도 3d는 도 3c에서 제1/제2 반도체 칩들(120/140)이 적층된 모습을 나타낸 단면도이며, 이에 더하여 제2 반도체 칩(140)의 볼 패드들 위로 솔더 볼들(170)이 형성된 모습을 도시한다. 도 3d에 도시된 것처럼, 제1/제2 반도체 칩들을 플립 본딩할 때 사용되는 범프(124)의 크기는 볼 패드 위로 실장되는 솔더 볼(170)의 크기에 비하여 상대적으로 작은 것을 알 수 있다.FIG. 3D is a cross-sectional view illustrating the stacking of the first and second semiconductor chips 120 and 140 in FIG. 3C. In addition, the solder balls 170 are formed on the ball pads of the second semiconductor chip 140. Illustrated. As shown in FIG. 3D, it can be seen that the size of the bump 124 used when flip bonding the first and second semiconductor chips is relatively small compared to the size of the solder ball 170 mounted on the ball pad.
이때, 일반적으로 사용되는 범프는 100 내지 150㎛의 크기로, 솔더 볼은 350 내지 500㎛의 직경을 갖는 것이 바람직하며, 또한 제1/제2 반도체 칩들이 플립 본딩된 영역에는 언더필(Underfill) 공정을 통해 봉지부(180)가 형성되는 것이 바람직하다.In this case, it is preferable that the bumps generally used have a size of 100 to 150 μm, the solder balls have a diameter of 350 to 500 μm, and an underfill process is performed on the areas where the first and second semiconductor chips are flip-bonded. It is preferable that the encapsulation unit 180 is formed through the sealing unit 180.
좀 더 상세하게 설명한다면, 제1 반도체 칩(120)의 두께(t2)와 범프(124)의 직경(t1)을 더한 값보다 솔더 볼(170)의 직경(t3) - 예를 들어, 350 내지 500㎛ - 이 더 크게 형성되어 있으며, 이를 이용하여 도 3e에 도시된 바와 같이 본 발명에 따른 적층 칩 패키지(200)가 외부 기판(190 ; Substrate) 위로 실장될 때 솔더 볼들(170)이 기판(190)과의 접속 단자 역할을 할 수 있도록 한다.In more detail, the diameter t3 of the solder ball 170 is greater than the thickness t2 of the first semiconductor chip 120 and the diameter t1 of the bump 124-for example, 350 to 500 μm − is formed to be larger, and as shown in FIG. 3E, when the stacked chip package 200 according to the present invention is mounted on an external substrate 190, the solder balls 170 are formed on the substrate ( It can serve as a connection terminal with 190).
위에서 제1/제2 반도체 칩의 활성면 위로 형성되는 범프 또는 패드 등은 웨이퍼 레벨에서 배선을 재배열하는 공정을 통하여 진행되는 것이 바람직하며, 위와 같이 배선을 재배열하는 공정을 도 4a 내지 도 4d를 통해 간략히 설명하면 다음과 같다.Bumps or pads formed on the active surface of the first and second semiconductor chips from above are preferably performed through a process of rearranging the wirings at the wafer level, and the process of rearranging the wirings as described above is illustrated in FIGS. 4A to 4D. If briefly described as follows.
즉, 위에서 기술된 배선을 재배열하는 공정은 본딩패드들(212)이 형성된 반도체 칩(210) 위로 절연막(230)을 형성하는 단계(도 4a)와, 절연막(230)을 일부 제거한 뒤 본딩패드들(212) 위로 금속기저층(220 ; UBM ; Under Barrier Metal)을 형성하는 단계와(도 4b), 절연막(230) 위로 금속기저층(220)과 연결되는 일정한 형태의 금속 배선(240)을 재배열하는 단계(도 4c) 및 금속 배선(240)의 일부가 노출되어 패드(242)를 형성하도록, 금속 배선(240)이 재배열된 반도체 칩(210) 위로 절연막(250)을 다시 형성하는 단계(도 4d)를 포함하는 것을 특징으로 한다.In other words, the process of rearranging the wiring described above may include forming an insulating film 230 over the semiconductor chip 210 on which the bonding pads 212 are formed (FIG. 4A), and removing the insulating film 230, and then removing the bonding pads. Forming a metal base layer 220 (UBM; Under Barrier Metal) over the fields 212 (FIG. 4B), and rearranging a metal wire 240 having a predetermined shape connected to the metal base layer 220 over the insulating film 230. Forming an insulating film 250 over the semiconductor chip 210 in which the metal wires 240 are rearranged so that a part of the metal wires 240 are exposed to form a pad 242 (FIG. 4C). 4d).
배선을 재배열하는 공정을 좀 더 상세히 설명하면 다음과 같다.The process of rearranging the wiring in more detail is as follows.
각 반도체 칩에 있어서, SiN, SiON 등과 같은 패시베이션 층(Passivation layer) 위로 두께 5∼20 ㎛의 폴리이미드(PI ; Polyimide) 또는 벤조 사이클로 부텐(BCB ; Benzo Cyclo Butene ; 이하 'BCB'라 한다)과 같은 비도전성 물질이 형성되어 절연막으로 사용될 수 있으며, 이러한 절연막이 구리(Cu), 알루미늄(Al), 아연(Zn) 등의 금속 배선과 패시베이션 층 사이에서 열팽창계수(CTE ; Coefficient Thermal Expansion)의 차이 또는 기계적 손상 등으로부터 반도체 칩의 회로를 보호할 수 있다.In each semiconductor chip, a polyimide (PI) or benzo cyclobutene (BCB) of 5 to 20 µm in thickness over a passivation layer such as SiN, SiON, etc. The same non-conductive material can be formed and used as an insulating film, and the insulating film has a difference in coefficient of thermal expansion (CTE) between a metal wiring and a passivation layer such as copper (Cu), aluminum (Al), and zinc (Zn). Alternatively, the circuit of the semiconductor chip can be protected from mechanical damage or the like.
또한, 본딩패드와 금속배선 사이에는 금속기저층이 형성되어 본딩패드를 보호하고, 금속배선과 본딩패드의 접착력을 향상시킬 수 있다. 금속기저층은 일반적으로 티타늄/구리(Ti/Cu) 또는 크롬/구리/금(Cr/Cu/Au) 등의 구성으로 형성될 수 있다.In addition, a metal base layer may be formed between the bonding pads and the metal wires to protect the bonding pads and to improve adhesion between the metal wires and the bonding pads. The metal base layer may generally be formed of titanium / copper (Ti / Cu) or chromium / copper / gold (Cr / Cu / Au).
이상에서 설명한 바와 같이, 본 발명에 따른 적층 칩 패키지 제조방법은 웨이퍼 레벨에서 배선을 재배열하는 공정을 통하여 형성된 제1/제2 반도체 칩들을 플립 본딩한 후 솔더 볼을 외부 접속 단자로 이용하는 칩 스케일 패키지 형태의 적층 칩 패키지 제조방법이다.As described above, in the method of manufacturing a stacked chip package according to the present invention, a chip scale using flip-bonding first and second semiconductor chips formed through a rearrangement of wiring at a wafer level and using solder balls as external connection terminals A method of manufacturing a stacked chip package in a package form.
이러한 방법을 통하여 제조된 적층 칩 패키지는 종래의 적층 칩 패키지들에 비하여 그 크기가 작으면서도 적층된 반도체 칩들 사이의 전기적 연결이 범프와 같이 길이가 짧은 수단을 통해 이루어지므로 신호전달이 빠른 특징을 갖는다.The stacked chip package manufactured by the above method has a small signal compared to the conventional stacked chip packages, but the signal transmission is fast because the electrical connection between the stacked semiconductor chips is made through short length means such as bumps. .
본 발명에 따른 적층 칩 패키지 제조방법은 서로 크기가 다른 제1/제2 반도체 칩들이 각각 형성된 웨이퍼들을 준비한 후 웨이퍼 레벨에서 배선을 재배열하는 기술과 플립 본딩 기술을 이용하여 제1 반도체 칩을 제2 반도체 칩의 칩 실장부 위로 적층한 후 제2 반도체 칩의 볼 패드들 위로 적층된 제1 반도체 칩의 높이보다 큰 직경을 갖는 솔더 볼들을 형성하는 것을 특징으로 하며, 이러한 특징에 따라 크기가 작으면서도 적층된 반도체 칩들 사이의 신호전달이 빠른 특징을 갖는 적층 칩 패키지를 구현할 수 있으며, 또한 본 발명에 따른 모든 제조공정이 웨이퍼 레벨에서 수행될 수 있기 때문에 제조공정과 제조시간이 단축될 수 있고 나아가 제조비용을 절감할 수 있다.In the method of manufacturing a multilayer chip package according to the present invention, after preparing wafers on which first and second semiconductor chips having different sizes are prepared, the first semiconductor chip may be prepared using a technique of rearranging wiring at a wafer level and flip bonding technology. 2, the solder balls having a diameter larger than the height of the first semiconductor chip stacked on the ball pads of the second semiconductor chip are stacked on the chip mounts of the second semiconductor chip. In addition, it is possible to implement a stacked chip package having a fast signal transfer between stacked semiconductor chips, and also all manufacturing processes according to the present invention can be performed at the wafer level, thereby reducing the manufacturing process and manufacturing time. The manufacturing cost can be reduced.
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| KR100836769B1 (en) * | 2007-06-18 | 2008-06-10 | 삼성전자주식회사 | Method of fabricating semiconductor chip package and semiconductor package including the same |
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| KR100836769B1 (en) * | 2007-06-18 | 2008-06-10 | 삼성전자주식회사 | Method of fabricating semiconductor chip package and semiconductor package including the same |
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