KR20000074508A - Setup skew reduction circuit - Google Patents

Setup skew reduction circuit Download PDF

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KR20000074508A
KR20000074508A KR1019990018507A KR19990018507A KR20000074508A KR 20000074508 A KR20000074508 A KR 20000074508A KR 1019990018507 A KR1019990018507 A KR 1019990018507A KR 19990018507 A KR19990018507 A KR 19990018507A KR 20000074508 A KR20000074508 A KR 20000074508A
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clock signal
clock
driving means
driver
setup
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KR1019990018507A
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Korean (ko)
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배대기
권익수
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윤종용
삼성전자 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Abstract

PURPOSE: A setup skew reducing circuit is provided which inputs a clock signal output from a clock driver to a multiple driving means by compensating time delay generated by a line resistance and a line capacity of an inner signal line to reduce setup skew. CONSTITUTION: A setup skew reducing circuit includes a clock driver(100) for receiving a clock signal and outputting it, a plurality of delayers(211,212,...21N), serially connected to the clock driver, for sequentially delaying the clock signal output from the clock driver, and a plurality of driving means(220,221,...22N) for performing a predetermined operation according to the clock signal output from the delayers. The setup skew reducing circuit is constructed in such a manner that the clock signals output from the first to last delayer are sequentially applied to the last to first driving means.

Description

셋업 스큐 감소회로 {Setup skew reduction circuit}Setup skew reduction circuit

본 발명은 복수의 구동부에 하나의 클럭신호를 공급할 경우에 발생되는 셋업 스큐(setup skew)를 감소시킬 수 있도록 하는 셋업 스큐 감소회로에 관한 것으로 특히 반도체 메모리 장치에 적용되는 셋업 스큐 감소회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a setup skew reduction circuit for reducing setup skew generated when one clock signal is supplied to a plurality of driving units, and more particularly, to a setup skew reduction circuit applied to a semiconductor memory device. .

일반적으로 반도체 메모리 장치는 칩이 대용량화 및 고속화 됨에 따라 셋업 시간 및 홀드 시간에 대한 중요성이 점차 증대되고 있는 실정이다.In general, semiconductor memory devices are increasingly important in terms of setup time and hold time as chips have increased in capacity and speed.

도 1은 동기(Synchronous) SRAM(Static Random Access Memory)에서 외부의 클럭신호를 입력 받아 내부의 회로의 각 부위에 공급하는 클럭신호 공급회로도이다.1 is a clock signal supply circuit diagram for receiving an external clock signal from a synchronous SRAM (Static Random Access Memory) and supplying it to each part of an internal circuit.

여기서, 부호 100은 외부의 클럭신호를 입력 받아 출력하는 클럭 드라이버이고, 부호 110, 111, ㆍㆍㆍ, 11N은 상기 클럭 드라이버(100)가 출력하는 클럭신호에 따라 소정의 동작을 수행하는 어드레스 버퍼 및 데이터 입력 버퍼 등의 구동 수단이다.Here, reference numeral 100 denotes a clock driver for receiving and outputting an external clock signal, and reference numerals 110, 111, ..., 11N denote an address buffer for performing a predetermined operation according to the clock signal output from the clock driver 100. And drive means such as a data input buffer.

상기 클럭 드라이버(100)의 출력단자와 상기 구동 수단(110, 111, ㆍㆍㆍ, 11N)의 클럭신호가 입력되는 클럭단자의 사이에는 내부 신호 라인(120)이 구비되는 것으로 클럭 드라이버(100)가 출력하는 클럭신호가 내부 신호 라인(120)을 통해 상기 구동 수단(110, 111, ㆍㆍㆍ, 11N)의 클럭단자에 공급되어 구동 수단(110, 111, ㆍㆍㆍ, 11N)이 클럭신호에 동기로 소정의 동작을 수행한다.An internal signal line 120 is provided between the output terminal of the clock driver 100 and the clock terminal to which the clock signal of the driving means 110, 111,..., 11N is input. Is supplied to the clock terminal of the driving means (110, 111, ..., 11N) via the internal signal line 120, and the driving means (110, 111, ..., 11N) is clock signal. A predetermined operation is performed in synchronization with.

이러한 종래의 클럭신호 공급회로에 따르면, 구동 수단(110, 111, ㆍㆍㆍ, 11N)의 클럭단자가 내부 신호 라인(120)을 통해 공통으로 연결되어 있는 것으로서 각각의 구동 수단(110, 111, ㆍㆍㆍ, 11N)의 사이에는 소정 폭 및 소정 길이를 가지는 내부 신호 라인(120) 자체의 라인 저항(R) 및 라인 커패시턴스(C)를 가지게 되고, 이 라인 저항(R) 및 라인 커패시턴스(C)에 의해 클럭신호가 지연되어 구동 수단(110, 111, ㆍㆍㆍ, 11N)에 동시에 입력되지 못하게 된다.According to the conventional clock signal supply circuit, the clock terminals of the driving means 110, 111, ..., 11N are commonly connected through the internal signal line 120, and the respective driving means 110, 111, 11N) has a line resistance R and a line capacitance C of the internal signal line 120 itself having a predetermined width and a predetermined length, and the line resistance R and the line capacitance C ), The clock signal is delayed and cannot be simultaneously input to the driving means 110, 111, ..., 11N.

즉, 첫 번째 구동 수단(110)으로 입력되는 클럭신호에 비하여 구동수단(111, 112, ㆍㆍㆍ, 11N)으로 입력되는 클럭신호는 순차적으로 TRC만큼 지연되어 입력되는 것으로서 마지막 구동 수단(11N)에는 첫 번째 구동 수단(110)으로 입력되는 클럭신호가 NㆍTRC만큼 지연되어 입력되고, 이로 인하여 구동수단(111, 112, ㆍㆍㆍ, 11N)이 공급되는 클럭신호에 따라 동시에 동작하지 못하게 되는 문제점이 있었다.That is, the clock signal inputted to the driving means 111, 112, ..., 11N is sequentially delayed by TRC as compared to the clock signal inputted to the first driving means 110, and the last driving means 11N is input. The clock signal input to the first driving means 110 is delayed by N. TRC, and thus, the driving means 111, 112,..., 11N cannot be operated simultaneously according to the clock signal supplied. There was a problem.

그리고 동기 SRAM에서는 클럭신호가 변환(transition)될 경우에 어드레스 신호 또는 데이터 라인을 샘플링하게 되는데, 상기와 같은 종래의 클럭신호 공급회로에서는 셋업 시간의 스큐가 클럭 드라이버(100)에서 가장 가까운 구동 수단(110)과 가장 먼 구동 수단(11N)의 사이에서 NㆍTRC만큼 발생하여 동기 SRAM의 운영 측면 및 인터페이스 측면에 많은 지장을 주는 문제점이 있었다.In the synchronous SRAM, when a clock signal is converted, an address signal or a data line is sampled. In the conventional clock signal supply circuit as described above, the skew of the setup time is the driving means closest to the clock driver 100 ( There was a problem that the N and TRC were generated between the driving means 11N and the farthest driving means 11N, causing a lot of problems on the operation side and the interface side of the synchronous SRAM.

따라서 본 발명의 목적은 클럭 드라이버에서 출력되는 클럭신호가 동일한 시간만큼 지연된 후 구동 수단으로 입력되게 하여 셋업 스큐를 감소시키는 셋업 스큐 감소회로를 제공하는 데 있다.Accordingly, an object of the present invention is to provide a setup skew reduction circuit which reduces the setup skew by causing the clock signal output from the clock driver to be delayed by the same time and then input to the driving means.

이러한 목적을 달성하기 위한 본 발명의 셋업 스큐 감소회로에 따르면, 클럭 드라이버에서 출력되는 클럭신호를 복수의 지연기로 순차적으로 지연시키고, 첫 번째 지연기부터 마지막 지연기의 출력신호가 마지막 구동 수단부터 첫 번째 구동 수단에 클럭신호로 공급되게 연결한다.According to the setup skew reduction circuit of the present invention for achieving this object, the clock signal output from the clock driver is sequentially delayed to a plurality of delayers, and the output signal of the first delayed to the last delayed first from the last driving means. The second drive means to be supplied as a clock signal.

상기 복수의 지연기들의 지연 시간은 상기 복수의 구동 수단으로 입력되는 클럭신호가 내부 신호 라인을 통해 흐르는 시간만큼 지연시키게 한다.The delay time of the plurality of delayers causes the clock signal inputted to the plurality of driving means to be delayed by the time flowing through the internal signal line.

그러므로 본 발명에 따르면, 클럭 드라이버에서 출력되는 클럭신호가 복수의 구동 수단으로 직접 입력시킬 경우에 발생되는 시간을 복수의 지연기가 지연 및 보상하여 복수의 구동 수단으로 입력시킴으로써 복수의 구동 수단은 클럭신호에 동기로 모두 동시에 동작하게 되고, 셋업 스큐가 발생하지 않게 된다.Therefore, according to the present invention, a plurality of driving means generates a clock signal by delaying and compensating for a time generated when a clock signal output from a clock driver is directly input to a plurality of driving means, and inputting the plurality of driving means to the plurality of driving means. At the same time, they all run in sync, and no setup skew occurs.

도 1은 종래의 클럭신호 공급회로이고,1 is a conventional clock signal supply circuit,

도 2는 본 발명의 셋업 스큐 감소회로가 적용된 클럭신호 공급회로도이다.2 is a clock signal supply circuit to which the setup skew reduction circuit of the present invention is applied.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

200 : 클럭 드라이버200: clock driver

211, 212, ㆍㆍㆍ, 21N : 지연기211, 212, ..., 21N: Delay

220, 221, ㆍㆍㆍ, 22N : 구동 수단220, 221, ..., 22N: drive means

INV : 인버터INV: Inverter

이하 첨부된 도 2의 도면을 참조하여 본 발명의 셋업 스큐 감소회로를 상세히 설명한다.Hereinafter, the setup skew reduction circuit of the present invention will be described in detail with reference to the accompanying drawings of FIG. 2.

도 2는 본 발명의 셋업 스큐 감소회로가 적용된 클럭신호 공급회로도이다.2 is a clock signal supply circuit to which the setup skew reduction circuit of the present invention is applied.

여기서, 부호 200은 외부의 클럭신호를 입력 받아 출력하는 클럭 드라이버이고, 부호 211, 212, ㆍㆍㆍ, 21N은 상기 클럭 드라이버(200)의 출력단자에 직렬 연결되어 클럭 드라이버(200)가 출력하는 클럭신호를 순차적으로 지연시키는 복수의 지연기이다.Here, reference numeral 200 denotes a clock driver for receiving and outputting an external clock signal, and reference numerals 211, 212, ..., 21N are connected in series with an output terminal of the clock driver 200 and output by the clock driver 200. A plurality of delayers for sequentially delaying clock signals.

부호 220, 221, ㆍㆍㆍ, 22N은 상기 복수의 지연기(21N, 21N－1, ㆍㆍㆍ, 211) 및 상기 클럭 드라이버(200)가 출력하는 클럭신호에 따라 소정의 동작을 수행하는 어드레스 버퍼 및 데이터 입력 버퍼 등의 구동 수단이다.Reference numerals 220, 221, ..., 22N denote addresses for performing a predetermined operation according to the clock signals outputted by the plurality of delay units 21N, 21N-1, ..., 211 and the clock driver 200. Driving means such as a buffer and a data input buffer.

상기 복수의 지연기(211, 212, ㆍㆍㆍ, 21N)는 각기 2개의 인버터(INV)를 직렬 연결하여 입력되는 클럭신호를 지연 출력하는 것으로 이들 지연기(211, 212, ㆍㆍㆍ, 21N)는 상기 클럭 드라이버(200)에서 출력되는 클럭신호를 복수의 구동 수단(220, 221, ㆍㆍㆍ, 22N)에 직접 공급할 경우에 발생되는 지연 시간만큼 클럭신호를 각기 지연시켜 출력하게 한다.The plurality of delay units 211, 212, ..., 21N respectively delay the output of the clock signal input by connecting two inverters INV in series. These delay units 211, 212, ..., 21N ) Delays and outputs the clock signal by a delay time generated when the clock signal output from the clock driver 200 is directly supplied to the plurality of driving means 220, 221, ..., 22N.

이와 같이 구성된 본 발명의 셋업 스큐 감소회로는 클럭 드라이버(200)가 외부로부터 클럭신호를 입력 받아 출력하게 된다.In the setup skew reduction circuit of the present invention configured as described above, the clock driver 200 receives and outputs a clock signal from an external source.

상기 클럭 드라이버(200)가 출력하는 클럭신호는 직렬 연결된 복수의 지연기(211, 212, ㆍㆍㆍ, 21N)로 입력되어 순차적으로 지연 출력된다.The clock signal output by the clock driver 200 is input to a plurality of delayers 211, 212, ..., 21N connected in series and sequentially delayed.

상기 복수의 지연기(211, 212, ㆍㆍㆍ, 21N)가 순차적으로 지연시켜 출력하는 클럭신호 및 상기 클럭 드라이버(200)가 출력하는 클럭신호들은 복수의 구동수단(22N, 22N－1, ㆍㆍㆍ, 220)에 클럭신호로 입력되는 것으로서 복수의 구동수단(22N, 22N－1, ㆍㆍㆍ, 220)은 복수의 지연기(211, 212, ㆍㆍㆍ, 21N) 및 클럭 드라이버(200)가 각기 출력하는 클럭신호에 따라 각기 소정의 동작을 수행하게 된다.Clock signals outputted by sequentially delaying the plurality of delay units 211, 212, ..., 21N, and clock signals outputted by the clock driver 200 are provided by a plurality of driving means 22N, 22N-1, ... The plurality of driving means 22N, 22N-1,..., 220 are input as clock signals to the plurality of delay units 211, 212,... 21N and the clock driver 200. Each of the) performs a predetermined operation according to the clock signal output.

여기서, 본 발명은 상기 복수의 지연기(211, 212, ㆍㆍㆍ, 21N)가, 상기 클럭 드라이버(200)에서 출력되는 클럭신호를 복수의 구동 수단(220, 221, ㆍㆍㆍ, 22N)에 직접 공급할 경우에 발생되는 지연 시간만큼 클럭신호를 각기 지연시켜 보상한 후 복수의 구동 수단(220, 221, ㆍㆍㆍ, 22N)에 공급하게 된다.In the present invention, the plurality of delay units (211, 212, ..., 21N), the clock signal output from the clock driver 200 is a plurality of driving means (220, 221, ..., 22N) The clock signal is delayed and compensated for each delay time generated when directly supplied to the plurality of drive means, and then supplied to the plurality of driving means 220, 221, ..., 22N.

그러므로 복수의 구동 수단(220, 221, ㆍㆍㆍ, 22N)에 공급되는 클럭신호는 상호간에 시간의 지연이 발생됨이 없이 동시에 공급된다.Therefore, the clock signals supplied to the plurality of driving means 220, 221, ..., 22N are simultaneously supplied without any time delay between them.

이상에서와 같이 본 발명에 따르면, 클럭 드라이버에서 출력되는 클럭신호를 복수의 구동 수단에 공급할 경우에 내부 신호 라인의 라인 저항 및 라인 커패시턴스에 의해 발생되는 시간 지연을 보상하여 복수의 구동 수단에 공급함으로써 복수의 구동 수단에 공급되는 클럭신호들은 상호간에 시간의 지연 없이 동시에 공급되어 셋업 스큐의 발생을 줄일 수 있다.As described above, according to the present invention, when the clock signal output from the clock driver is supplied to the plurality of driving means, the time delay caused by the line resistance and the line capacitance of the internal signal line is compensated and supplied to the plurality of driving means. The clock signals supplied to the plurality of driving means can be supplied simultaneously without delay of time to each other to reduce the occurrence of setup skew.

Claims (4)

클럭신호를 입력받아 출력하는 클럭 드라이버;A clock driver for receiving and outputting a clock signal; 클럭 드라이버에 직렬 연결되어 클럭 드라이버가 출력하는 클럭신호를 순차적으로 지연시키는 복수의 지연기; 및A plurality of delayers serially connected to the clock driver and sequentially delaying a clock signal output by the clock driver; And 상기 복수의 지연기가 출력하는 클럭신호에 따라 소정의 동작을 수행하는 복수의 구동 수단을 구비하고,A plurality of driving means for performing a predetermined operation according to a clock signal outputted by the plurality of delayers, 상기 복수의 지연기들 중에서 첫 번째부터 마지막 지연기가 출력하는 클럭신호가 마지막 구동수단부터 첫 번째 구동수단에 클럭신호가 각기 공급되게 내부 신호 라인으로 연결하는 것을 특징으로 하는 셋업 스큐 감소회로.And a clock signal output from a first to last delay unit of the plurality of delayers is connected to an internal signal line such that clock signals are supplied from the last driving unit to the first driving unit, respectively. 제 1 항에 있어서, 상기 복수의 지연기들은;2. The apparatus of claim 1, wherein the plurality of retarders; 상기 클럭 드라이버에서 출력되는 클럭신호를 복수의 구동 수단에 직접 공급할 경우에 발생되는 지연 시간만큼 클럭신호를 각기 지연시키는 것을 특징으로 하는 셋업 스큐 감소회로.And delaying each clock signal by a delay time generated when the clock signal output from the clock driver is directly supplied to a plurality of driving means. 제 1 항 또는 제 2 항에 있어서, 상기 복수의 지연기들은;3. The apparatus of claim 1 or 2, wherein the plurality of retarders; 2개의 직렬 연결된 인버터인 것을 특징으로 하는 셋업 스큐 감소회로.Setup skew reduction circuit, characterized in that the two series connected inverter. 제 1 항 또는 제 2 항에 있어서, 상기 복수의 지연기들은;3. The apparatus of claim 1 or 2, wherein the plurality of retarders; 패시브 소자로 클럭신호를 지연시키는 것을 특징으로 하는 셋업 스큐 감소회로.A set-up skew reduction circuit which delays a clock signal with a passive element.
KR1019990018507A 1999-05-21 1999-05-21 Setup skew reduction circuit KR20000074508A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7321207B2 (en) 2002-09-12 2008-01-22 Samsung Electronics Co., Ltd. Inverter apparatus and liquid crystal display including inverter apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7321207B2 (en) 2002-09-12 2008-01-22 Samsung Electronics Co., Ltd. Inverter apparatus and liquid crystal display including inverter apparatus

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