KR20000073030A - Device for overlapping and adding window in AC-3 decoder - Google Patents

Abstract

PURPOSE: An apparatus for overlapping/adding window in an AC-3 decoder is to eliminate an aliasing phenomenon generated by an overlapping between adjacent windows, thereby exactly restoring an audio signal. CONSTITUTION: An apparatus for overlapping/adding window in an AC-3 decoder comprises an address generating/controlling portion(10) for generating an address to access a memory and a buffer and controlling an overlapping and adding operation of a window with respect to a time-base signal, a window memory for storing a data table to overlap the window, a down mix buffer(30) for storing a signal converted from frequency domain into time domain, a delaying buffer(40) for storing a former block data delayed to overlap the window, a sample calculating portion(50) for overlapping and adding a windowing value of the former block data and a windowing value of a present block data according to a control of the address generating/controlling portion to eliminate an aliasing phenomenon, and a PCM calculating portion(60) for rounding a level of a data output from the sample calculating portion to generate a pulse code modulation data.

Description

Device for overlapping and adding window in AC-3 decoder

The present invention relates to an AC-3 (Dolby proposed) audio decoder, which is an audio standard adopted by High Definition TeleVision (HDTV), and particularly when analyzing an audio signal in an AC-3 decoder. When converting from a frequency domain to a time domain, hardware implementation of a window overlapping / adding device that removes aliasing caused by overlapping between adjacent time-base windows is performed in hardware. A window superimposition / addition apparatus of an AC-3 decoder that allows for restoration.

In general, an AC-3 decoder is an apparatus for decoding an audio signal coded according to the AC-3 standard, which is an audio compression standard in HDTV. The AC-3 decoder must be provided with a window overlap / add device to remove aliasing generated when converting a signal in the frequency domain into the time domain. If aliasing occurs, there is that much signal distortion, which cannot be recovered in any way. This makes it difficult to accurately restore the audio signal.

That is, as shown in FIG. 1, when performing a forward / inverse transform on the received signal INPUT SIGNAL, a sequence in which aliasing is generated on the time axis is generated. Synthesis windowing is then performed by multiplying the signals without aliasing for each signal. In addition, the overlapped / adding operation of the previous signal and the current signal on which synthesis windowing is performed is performed to remove the aliased portion. This window overlapping / adding device should be provided in the AC-3 decoder.

Therefore, the present invention has been proposed by the implementation request of the window overlapping / adding device as described above, and an object of the present invention is

When analyzing an audio signal in an AC-3 decoder, a window that removes aliasing caused by overlapping between adjacent time-base windows when converting the signal from the frequency domain to the time domain. The present invention provides a window overlapping / adding device of an AC-3 decoder capable of accurately recovering an audio signal by implementing the overlapping / adding device as a hardware device.

In order to achieve the above object, the window overlapping / adding device of the AC-3 decoder according to the present invention,

An address generation / control unit for generating an address for accessing each memory and a buffer, and for controlling window overlapping and addition operations on time axis signals;

A window memory for storing a data table for window overlapping;

A down mix buffer for storing signals converted from frequency domain to time domain;

A delay buffer for storing previous block data delayed for data overlap;

A sample calculator for removing aliasing by overlapping and adding a windowing value of previous block data and a windowing value of current block data according to the control of the address generator / control unit;

The PCM calculation unit generates pulse code modulation (PCM) data by rounding the level of data output from the sample calculation unit to a value within a minimum value and a maximum value that can be processed by an AC-3 decoder. It is characterized by the technical configuration.

The sample calculator comprises: a first flip flop (FF) for latching previous block data stored in the delay buffer according to a clock; A second flip-flop for latching window table data stored in the window memory according to the clock; A third FF for latching a time base signal stored in the downmix buffer according to the clock; A fourth FF for latching window table data stored in the window memory according to the clock; A negative converter for converting the signal output from the first FF into a negative number; A first multiplexer for selecting and outputting one of an output signal of the first FF and an output signal of the negative converter according to a selection control signal (select) output from the address generator / control unit; A first multiplier configured to multiply the output signal of the first multiplexer by the output signal of the second FF to perform windowing; A second multiplier configured to multiply the output signal of the third FF by the output signal of the fourth FF to perform windowing; An adder configured to perform an addition operation on the output signal of the first multiplier and the output signal of the second multiplier; A subtractor for performing a subtraction operation on the output signal of the first multiplier and the output signal of the second multiplier; A second multiplexer for selecting and outputting one of an output signal of the adder and an output signal of the subtractor according to the address selection control signal (select); A shifter which performs a function of an input value * 2 by shifting the output signal of the second multiplexer 1 bit to the left; A rounding unit for rounding an output signal of the shifter; It characterized in that it comprises a limit value substitution unit for replacing the output signal of the rounding unit to a value within the range that can be processed by the PCM calculation unit.

The PCM calculator may include: an adder configured to perform an addition operation with a specific value (Ox20) on the signal output from the limit value replacement unit of the sample calculator; A limit value substitution unit for replacing an output signal of the adder with a value within a range that can be processed by a digital-to-analog converter (DAC) of an AC-3 decoder; A longval / fractval calculator for calculating fractval and longval using the output signal of the limit value substitution unit; A comparison unit comparing the fractval and longval calculated by the longval / fractval calculation unit; An inspecting unit which checks the value compared by the comparing unit and outputs it to the shifter; And a shifter for shifting the output signal of the test unit by 6 bits.

1 is a signal waveform diagram showing a window overlap / add operation method in an AC-3 decoder;

2 is a block diagram of a window overlapping / adding device of an AC-3 decoder according to the present invention;

3 is a block diagram of a sample calculation unit of FIG. 2;

4 is a block diagram of a PCM calculator in FIG.

<Explanation of symbols for the main parts of the drawings>

10: address generation / control unit 20: window memory

30: Down mix buffer 40: Delay buffer

50: sample calculation unit 60: PCM calculation unit

70: output buffer

Hereinafter, the window overlapping / adding device of the present invention AC-3 decoder will be described in detail with reference to the accompanying drawings.

Samples of the time base generated during the processing of the AC-3 decoder must be windowed, and the previous and current signals overlap and add to form the final Pulse Code Modulation (PCM) audio signal. (adding) operation must be performed.

Here is a pseudo code representation that shows the general way of windowing samples on the time base:

for (n = 0; n <N / 8; n ++) {

x [2 * n] = -yi [N / 8 + n] * w [2 * n];

x [2 * n + 1] = yr [N / 8 n -1] * w [2 * n + 1];

x [N / 4 + 2 * n] = − yr [n] * w [N / 4 + 2 * n];

x [N / 4 + 2 * n + 1] = yi [N / 4−n−1] * w [N / 4 + 2 * n + 1];

x [N / 2 + 2 * n] = -yr [N / 8 + n] * w [N / 2-2 * n-1];

x [N / 2 + 2 * n +1] = yi [N / 8-n-1] * w [N / 2-2 * n-2];

x [3 * N / 4 + 2 * n] = yi [n] * w [N / 4-2 * n-1];

x [3 * N / 4 + 2 * n + 1] = -yr [N / 4-n-1] * w [N / 4-2 * n-2];

}

In the above, yi represents signal data output from the front end of the window overlapping / adding device in the AC-3 decoder, and yr represents current signal data. w denotes a table value used for windowing.

Next, window overlap and add operation must be performed to configure the synthesized windowing signal as the final PCM audio signal. The following is a pseudo code expression showing a general overlap / add operation.

for (n = 0; n <N / 2; n ++) {

pcm [n] = 2 * (x [n] + delay [n]);

delay [n] = x [N / 2 + n);

}

pcm represents the final value of overlapping & adding the windowed value, which is transmitted as a pulse code to the Digital to Analog Converter (DAC) in serial data format. The delay is stored in a temporary buffer for subsequent signal aliasing cancellations.

The window overlapping / adding device block configuration of the AC-3 decoder implementing the above window overlapping / adding algorithm in hardware according to the present invention is shown in FIG.

As shown, the window overlapping / adding device of the AC-3 decoder according to the present invention includes an address generation / control unit 10, a window memory 20, a down mix buffer 30, a delay buffer 40, and a sample calculation unit. 50, a PCM calculation unit 60, and an output buffer 70.

The address generation / control unit 10 generates an address for accessing each memory and a buffer, and controls window overlapping and addition operations for the time axis signal. It receives the clock (woa_clk), the number of channels (outnchans [2: 0]), the start signal (woa_start), and the outmode for setting the output mode from the outside, the window memory 20, the downmix buffer 30, and the delay. An address for accessing the buffer 40 is generated.

In general, one frame is composed of 6 blocks, and each block has 6 channels. So window nesting / adding operations are done in blocks.

The window memory 20 is a ROM of 256 words size for storing a data table for overlapping windows. Down mix buffer 30 is a 256 * 6 word size SRAM for storing signals converted from the frequency domain to the time domain. Thus, the downmix buffer 30 has a total width of 1536 with 22 bits of data width and 256 words per channel and 6 channels.

Delay buffer 40 is an SRAM for storing previous block data delayed for data overlap. The delay buffer 40 has a total width of 768 depths with data width 22 bits, 128 words per channel, and 6 channels.

The sample calculator 50 is an apparatus for removing aliasing by overlapping and adding a windowing value of a previous block data and a windowing value of a current block data according to the control of the address generator / control unit 10. This is shown in FIG.

The sample calculator 50 may include first to fourth flip flops (FF) 51a to 51d, a negative number converter 52, a first multiplexer 53, a first multiplier 54a, and a first to fourth flip flop (FF) 51a to 51d. 2 multiplier 54b, adder 55a, subtractor 55b, second multiplexer 56, shifter 57, rounding unit 58, and limit value replacement unit 59.

The first flip-flop (FF) 51a latches previous block data stored in the delay buffer 40 according to a clock, and the second flip-flop 51b stores a window table stored in the window memory 20. The data is latched according to the clock, the third FF 51c latches the time base signal stored in the downmix buffer 30 according to the clock, and the fourth FF 51d is stored in the window memory 20. The window table data is latched in accordance with the clock.

The negative converter 52 converts the signal output from the first FF 51a into a negative number. The conversion method is a 2's complement method that adds one after taking a complement to an input signal. The first multiplexer 53 is one of an output signal of the first FF 51a and an output signal of the negative converter 52 according to a selection control signal (select) output from the address generator / control unit 10. Select to print. The first multiplexer 53 selects an output signal of the negative converter 52 when the selection control signal is "1" and outputs the output signal to the first multiplier 53, and when the selection control signal is "0", the first multiplexer 53. An output signal of the FF 51a is selected and output to the first multiplier 53.

The first multiplier 54a multiplies 22 bits of the output signal of the first multiplexer 53 and 22 bits of the output signal of the second FF 51b to perform windowing, and the second multiplier 54b 22 bits of the output signal of the third FF 51c and 22 bits of the output signal of the fourth FF 51d are multiplied to perform windowing.

The adder 55a performs an addition operation on the output signal of the first multiplier 54a and the output signal of the second multiplier 54b. The subtractor 55b performs a subtraction operation on the output signal of the first multiplier 54a and the output signal of the second multiplier 54b. The adder 55a and the subtractor 55b can perform two's complement operations, respectively, and the output is 44 bits in consideration of an internal carry occurrence.

The second multiplexer 56 selects and outputs one of an output signal of the adder 55a and an output signal of the subtractor 55b according to the address selection control signal select. The second multiplexer 56 selects an output signal of the adder 55a when the selection control signal is "1" and outputs the output signal to the shifter 57, and when the selection control signal is "0", The output signal of the subtractor 55b is selected and output to the shifter 57.

The shifter 57 performs a 1-bit shift on the output signal of the second multiplexer 56 to the left to perform a function of an input value * 2. The rounding unit 58 rounds the output signal of the shifter 57.

The limit value replacing unit 59 replaces the output signal of the rounding unit 58 with a value within a range that can be processed by the PCM calculating unit 60. Thus, if the result value of the window overlap / add operation exceeds the maximum value that can be processed by the PCM calculator 60, the result value is replaced with the maximum value. If the window overlap / add operation value is less than or equal to the minimum value that can be processed by the PCM calculator 60, the operation value is replaced with the minimum value. After allocating bits of arithmetic bits + 2, the upper 3 bits are examined to produce a result. That is, if the upper bits of the result value of the window overlap / add operation are 001,010,011, the maximum value is replaced, and if the upper bits are 100,101,111, the minimum value is replaced.

The PCM calculator 60 generates the PCM data by rounding the level of data output from the sample calculator 50 to a value within a minimum value and a maximum value that can be processed by the AC-3 decoder. Its block configuration is shown in FIG.

The PCM calculator 60 includes an adder 61, a limit value substitute 62, a longval / fractval calculator 63, a comparator 64, an inspector 65, a shifter 66, and a flip-flop FF. (67).

The adder 61 performs an addition operation on the signal output from the limit value replacement unit 59 of the sample calculator 50 with a specific value Ox20. The limit value replacing unit 62 replaces the output signal of the adder 61 with a value within a range that can be processed by the digital-to-analog converter (DAC) of the AC-3 decoder. Thus, if the output signal of the adder 61 exceeds the maximum value that can be processed in the DAC, the output signal is replaced with the maximum value, and the output signal of the adder 61 can be processed in the DAC. If smaller, the output signal of the adder 61 is replaced with the minimum value. That is, after the operation bit + 1 bit is allocated, the upper 2 bits of the output signal of the adder 61 are examined, and when the upper 2 bits are 01, the maximum value is substituted, and when the upper 2 bits are 10, the minimum value is substituted. do.

The longval / fractval calculation unit 63 calculates fractval and longval using the output signal of the limit value substitution unit 62. That is, fractval is calculated by shifting 15 bits to the left (input value << 15), and longval is calculated by performing {input value, 15'b000000000000000} & 37'h1fffe00000 operations.

The comparison unit 64 compares the fractval and longval calculated by the longval / fractval calculation unit 63. In addition, the inspection unit 65 examines the value compared by the comparison unit 64 and outputs it to the shifter 66. The shifter 66 shifts the output signal of the inspection unit 65 by 6 bits. That is, the shifter 66 multiplies the output signal of the inspection unit 65 by Ox 20, and then multiplies the result value by 2 to perform a 6-bit shifting operation.

In this way, when the PCM signal is finally output from the PCM calculator 60, the PCM signal is temporarily buffered in the output buffer 70. Thus, the PCM signal is temporarily buffered in the output buffer 70 before being output to the DAC, which is the rear end of the window overlapping / adding device, thereby preventing data loss due to a collision between the window overlapping / adding device and the DAC. .

As described above, the window overlapping / adding device of the AC-3 decoder according to the present invention may convert a signal from a frequency domain to a time domain when analyzing an audio signal in the AC-3 decoder. In this case, by implementing a window overlap / add device as a hardware device that eliminates aliasing caused by overlap between adjacent time base windows, the audio signal can be accurately restored.

Claims (4)

When analyzing an audio signal in an AC-3 decoder, a window that removes aliasing caused by overlapping between adjacent time-base windows when converting the signal from the frequency domain to the time domain. In the nesting / adding device, An address generation / control unit for generating an address for accessing each memory and a buffer, and for controlling window overlapping and addition operations on time axis signals; A window memory for storing a data table for window overlapping; A down mix buffer for storing signals converted from frequency domain to time domain; A delay buffer for storing previous block data delayed for data overlap; A sample calculator for removing aliasing by overlapping and adding a windowing value of previous block data and a windowing value of current block data according to the control of the address generator / control unit; PCM calculator that generates pulse code modulation (PCM) data by rounding the level of data output from the sample calculator to a value within the minimum and maximum values that can be processed by the AC-3 decoder. Window overlapping / adding device of an AC-3 decoder. The method of claim 1, And an output buffer for temporarily buffering the PCM output signal output from the PCM calculator. The method of claim 1, wherein the sample calculation unit, A first flip flop (FF) for latching previous block data stored in the delay buffer according to a clock; A second flip-flop for latching window table data stored in the window memory according to the clock; A third FF for latching a time base signal stored in the downmix buffer according to the clock; A fourth FF for latching window table data stored in the window memory according to the clock; A negative converter for converting the signal output from the first FF into a negative number; A first multiplexer for selecting and outputting one of an output signal of the first FF and an output signal of the negative converter according to a selection control signal (select) output from the address generator / control unit; A first multiplier configured to multiply the output signal of the first multiplexer by the output signal of the second FF to perform windowing; A second multiplier configured to multiply the output signal of the third FF by the output signal of the fourth FF to perform windowing; An adder configured to perform an addition operation on the output signal of the first multiplier and the output signal of the second multiplier; A subtractor for performing a subtraction operation on the output signal of the first multiplier and the output signal of the second multiplier; A second multiplexer for selecting and outputting one of an output signal of the adder and an output signal of the subtractor according to the address selection control signal (select); A shifter which performs a function of an input value * 2 by shifting the output signal of the second multiplexer 1 bit to the left; A rounding unit for rounding an output signal of the shifter; And a limit value substitution unit which replaces the output signal of the rounding unit with a value within a range that can be processed by the PCM calculator. The method of claim 1, wherein the PCM calculation unit, An adder configured to perform an addition operation with a specific value (Ox20) on the signal output from the limit value substitution unit of the sample calculator; A limit value substitution unit for replacing an output signal of the adder with a value within a range that can be processed by a digital-to-analog converter (DAC) of an AC-3 decoder; A longval / fractval calculator for calculating fractval and longval using the output signal of the limit value substitution unit; A comparison unit comparing the fractval and longval calculated by the longval / fractval calculation unit; An inspecting unit which checks the value compared by the comparing unit and outputs it to the shifter; And a shifter configured to shift the output signal of the test unit by 6 bits.