JP2617207B2 - Adaptive differential pulse code modulation encoding / decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial application field) The present invention is used for a solid-state recording / reproducing system, a transmission system of a telephone digital line, and the like. The present invention relates to an adaptive differential pulse code modulation (hereinafter, referred to as ADPCM) encoding / decoding device for performing conversion into a modulation code and inverse conversion thereof.

(Prior Art) Conventionally, this type of ADPCM encoding / decoding device is described in Oki Electric R & D, 47 [1] (January 1, 1980) Oki Electric Industry Co., Ltd., pp. 61-66. There was something to be done. Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a block diagram showing a configuration example of a conventional ADPCM encoding / decoding device.

This ADPCM encoding / decoding apparatus has an input terminal 1 for inputting an analog waveform such as audio or image.
Includes a sample-and-hold circuit 2, an analog / digital converter (hereinafter, referred to as an A / D converter) 3, a digital subtractor 4, and an encoder 5 for converting a digital signal into an ADPCM code. Have been. The output side of the encoder 5 is connected to the input side of the encoder 5 via the quantizer 6 and to the input / output terminal 7 of the ADPCM code. A decoder 8 for converting an ADPCM code into a digital signal is connected to each output side of the encoder 5 and the quantization width unit 6, and further, an output side of the decoder 8 is
An adder 9, a data storage register 10, a digital / analog converter (hereinafter, referred to as a D / A converter) 11, and an analog reproduction waveform output terminal 12 are connected in cascade. The output side of the register 10 is connected to the subtractor 4 and the adder 9.

Next, the operation of the ADPCM encoder / decoder is described in (i)
The case of operating as an encoding device and the case of (ii) operating as a decoding device will be described separately.

(I) In the case of operating as an encoding device The analog waveform such as voice or image input from the input terminal 1 is converted into a step waveform in which the peak value of the waveform changes every predetermined sampling cycle by the sample and hold circuit 2. It is changed and input to the A / D converter 3. The A / D converter 3 converts the input step waveform into a digital signal for each step. This digital signal is pulse code modulated (hereinafter referred to as PC
The signal is referred to as “input PCM code” hereinafter. Here, among the input PCM codes obtained for each predetermined sampling period, the n-th input PCM code is defined as _Xn . Input PCM code _Xn and PCM playback value output from register 10
The _n-1, given to a subtracter 4, its subtractor 4 difference d _n of the two inputs is taken, the difference value d _n is given to the encoder 5. The difference value is given by d _n (1).

_{d n = X n - n-} 1 ... (1) encoder 5 receives the difference value d _n, as the quantization width value delta _n input signals as the output signals from the quantization width unit 6, ADPCM
To code L _n output.

Here, the encoder 5 is, for example, a 4-bit ADPCM code L _n
The process of creating is described. 4-bit ADPCM code L
_n is represented by a digital code (1 or 0) of L _n1 , L _n2 , L _n3 , L _n4 in order of importance. First, the difference value
It checks whether d _n is a positive value (including 0) or a negative value, and determines the ADPCM code L _n1 . For example, if the value is positive, L _n1 = 0, and if the value is negative, L _n1 = 1. This calculation equation is shown in equation (2).

Then, the difference value d _n absolute value | for comparing the quantization width value delta _n | d _n. Expression (3) shows how L _n2 is determined as a result of magnitude comparison between | d _n | and Δn / 2.

The absolute value | d _n | a, (3) delta to L _n2 obtained by expression _n / 2
, And a value obtained by adding Δ _n / 4 (L _n2 × Δ _n /
2 + delta _n / 4) and then compares the illustrates that L _n3 is determined by the results in (4) below.

Δ _n / 4 is added to the absolute value | d _n | and L _n3 obtained by equation (4).
And a value obtained by adding Δ _n / 8 to the product (L _n2 × Δ _n /
_{2 + L n3 × Δ n /} 4 + Δ n / 8) and by magnitude comparison are shown in state (5) formula L _n4 is determined by the result.

The ADPCM code L _n (L
_n1 , _Ln2 , _Ln3 , _Ln4 ) are output from the input / output terminal 7 and input to the decoder 8. Decoder 8 calculates the difference demodulator q _n receives the quantization width value delta _n outputted from the quantization width unit 6 as another input, give it to the adder 9.
The basic formula for calculating the difference demodulated values q _n shown in equation (6).

_{q n = Δ n × (L} n +1/16) ... (6) also shows a calculation formula for q _n with L _n1 ~L _n4 (7).

The adder 9 calculates the difference demodulated value q as shown in Expression (8).
_n and the PCM playback value _n-1 output from the register 10 are added to output a new PCM playback value _n , which is then stored in the register 1
Store to 0. _{n = n-1 + q n} ... (8) On the other hand, ADPCM code L _n that is output from the encoder 5 is inputted to the quantization width unit 6. In the quantization width unit 6, as shown in Expression (9), the coefficient M determined by the ADPCM code L _n
(L _n) and to form a delta _{n + 1} by multiplying the quantization width value delta _n.

Δ _{n + 1} = Δ _n × M (L _n ) (9) The above is the process executed by the N-th input PCM code X _n , but the same applies to the next sampling period (N + 1) -th. The ADPCM code Ln _{+ 1} is formed through the following steps.

ADPCM code L _n when acting as (ii) decoding apparatus is input to the decoder 8 from output terminal 7. Decoder 8, the other input and receiving the quantization width value delta _n outputted from the quantization width unit 6 calculates the difference demodulated values q _n, and gives the value q _n to adder 9. The basic formula for calculating the difference demodulated values q _n shown in equation (10). The equation (10) is the same as the equation (6).

_{q n = Δ n × (L} n +1/16) ... (10) adder 9 as shown in (11), a differential demodulation value q _n,
The PCM reproduction value _n-1 output from the register 10 is added to output a new PCM reproduction value _n , which is stored in the register 10. _{n = n-1 + q n} ... (11) PCM reproduction values X _n of the updated register 10, D / A converter 11
Is converted into an analog reproduction waveform, and output from the output terminal 12.

On the other hand, the ADPCM code L _n input from the input / output terminal 7 is
It is supplied to the quantization width unit 6, and the quantization width unit 6 creates a new quantization width value Δn _{+ 1} as shown in the above equation (9).

The above is a process executed by the n-th input ADPCM code L _n, the analog reproduction waveform are sequentially output from an output terminal 12 through a similar process follows.

(Problems to be Solved by the Invention) However, the apparatus having the above configuration has the following problems.

In the ADPCM encoding / decoding apparatus shown in FIG.
At the time of conversion from an analog waveform to a digital signal (input PCM code) by the / D converter 3, at the time of conversion from a digital signal (input PCM code) by the encoder 5 to an ADPCM code, conversion from the ADPCM code by the decoder 8 to digital When converting to a digital signal (PCM code) by the D / A converter 11
(Sign) to an analog reproduction waveform, respectively, causes signal distortion. Since such signal distortion has an adverse effect on reproduced sound quality and reproduced image quality, it is desirable to reduce the signal distortion as much as possible. It was extremely difficult to reduce the content to 3% or less.

As one method for reducing the signal conversion distortion, the resolution of the A / D converter 3 and the D / A converter 11 is set, for example, from 8 bits to 1 bit.
Although it is conceivable to reduce the signal conversion distortion by increasing the signal conversion to two bits, there is a problem that the circuit scale is increased and the cost of the device is increased.

The present invention provides an ADPCM encoding / decoding apparatus which solves the problem of the prior art that it is difficult to reduce signal conversion distortion without increasing the cost of the apparatus due to an increase in circuit scale. Is provided.

(Means for Solving the Problems) In order to solve the above problems, a first aspect of the present invention provides an ADPCM encoding / decoding device which encodes an analog waveform into an ADPCM code and decodes the ADPCM code. A sample and hold circuit that samples a waveform and holds it for a certain period of time, a D / A converter that converts an addition result consisting of a PCM reproduction value output by an adder to an analog reproduction value, and an output of the sample and hold circuit And an analog comparator for comparing the output of the D / A converter and outputting a signal corresponding thereto, a first register for storing the output of the analog comparator, and the first register for encoding. AD which is the output of
An input / output terminal for outputting a PCM code and externally inputting an ADPCM code in a decoding process, and inputting an output of the analog comparator in a coding process, and performing first control based on an output of the analog comparator. Outputting a signal and a second control signal, and inputting the externally input ADPCM code in a decoding process;
An encoding control circuit for outputting a third control signal and a fourth control signal based thereon, and an input of the first control signal and the output of the first register in an encoding process, and A quantization width generator that generates a predetermined quantization width, receives the third control signal and the externally input ADPCM code in a decoding process, and generates a predetermined quantization width based on the input; Storing an addition result output from the adder based on the second control signal in an encoding process, and storing an addition result output from the adder based on the fourth control signal in a decoding process. A second register; and the adder that adds an output of the quantization width unit and an output of the second register and outputs an addition result.

According to a second aspect of the present invention, there is provided an ADPCM encoding / decoding device which encodes an analog waveform into an ADPCM code and decodes the ADPCM code. A D / A converter that converts the addition result consisting of the PCM playback value output by the adder to an analog playback value, and compares the output of the sample and hold circuit with the output of the D / A converter and responds accordingly. An analog comparator that outputs a signal, an input / output terminal that outputs an ADPCM code that is an output of the analog comparator in a coding process, and inputs an ADPCM code from the outside in a decoding process, and the analog in a coding process. An output of a comparator is input, a first control signal and a second control signal are output based on an output of the analog comparator, and an ADPCM code input from the outside is input in a decoding process. Based on And a coding control circuit for outputting a control signal and a fourth control signal, and in a coding process, the first control signal and the output of the analog comparator, and a predetermined quantization width is set based on the input. Generating and decoding, in the decoding step, the third control signal and the externally input ADPCM code, and a quantization width generator for generating a predetermined quantization width based thereon; and A register for storing an addition result output from the adder based on a second control signal, and storing an addition result output from the adder based on the fourth control signal in a decoding process; The adder for adding the output of the width unit and the output of the register and outputting an addition result.

(Operation) According to the first invention, since the ADPCM encoding / decoding device is configured as described above, when encoding an analog waveform, the analog waveform is sampled by the sample / hold circuit, and the analog comparator is sampled. And the output of the analog comparator is stored in the first register. The quantization width unit receives the first control signal from the encoding control circuit and the output of the first register and generates a predetermined quantization width. This quantization width and the output of the second register are added by an adder, and the PCM reproduction value that is the result of the addition is converted into an analog reproduction value by a D / A converter, and fed back to an analog comparator. . The analog comparator compares the output of the sample and hold circuit with the analog reproduction value and outputs an ADPCM code corresponding to the output, and the ADPCM code is output from the input / output terminal via the first register.

When decoding the ADPCM code input from the outside to the input / output terminal, the quantization width unit uses the third signal from the coding control circuit.
, And a predetermined quantization width is generated based on the control signal and the ADPCM code input from the outside. The quantization width and the output of the second register are added by an adder, and the PCM reproduction value that is the result of the addition is converted into an analog reproduction value by a D / A converter and output.

According to the second aspect, when encoding an analog waveform, the analog waveform is sampled by the sample and hold circuit and sent to the analog comparator. The quantization width unit receives the first control signal from the encoding control circuit and the output of the analog comparator, and generates a predetermined quantization width.
The quantization width and the output of the register are added by an adder, and the PCM reproduction value as the result of the addition is converted into an analog reproduction value by a D / A converter, and is fed back to an analog comparator. The analog comparator compares the output of the sample-and-hold circuit with the analog reproduction value, and
The PCM code is output, and the ADPCM code is output from the input / output terminal.

When decoding the ADPCM code input to the input / output terminal from the outside, the quantization width unit determines a predetermined quantization based on the third control signal from the coding control circuit and the ADPCM code input from the outside. Generate a pass width. The quantization width and the output of the register are added by an adder, and the result of the addition is obtained.
The PCM playback value is converted to an analog playback value by a D / A converter and output.

(Embodiment) FIG. 1 is a block diagram showing the configuration of an ADPCM encoding / decoding apparatus according to an embodiment of the present invention.

This ADPCM encoding / decoding device is a device which is composed of, for example, a MOS transistor or the like, and whose overall operation is controlled by timing control signals a to e output from the timing control signal generation circuit 20. The ADPCM encoding / decoding device has an input terminal 21 for inputting an analog waveform A _in such as audio or image, and the input terminal 21 samples the analog signal A _in by a timing control signal a and makes it constant. The sample hold circuit 22 for holding time is connected, and the output signal S22 of the circuit 22 is output together with the output signal S30 to the analog comparator.
23 is entered. Analog comparator 23
Is a circuit that compares the two output signals S22 and S30 and outputs an output signal S23 composed of an ADPCM code corresponding to the output signals S22 and S30. The output signal S23 is input to the first register 24.

The first register 24 is a circuit for storing the output signal S23 in accordance with the timing control signal b, and its output side is an input / output terminal 25 of an ADPCM code, an encoding control circuit 26, and a
Connected to 27. The encoding control circuit 26 receives the output signal S23 of the analog comparator 23 in the encoding process based on the timing control signal C, and inputs the ADPCM code in the decoding process to control signals S26a and S26b for encoding control. Is a circuit that outputs. The operation of the quantizer 27 is controlled by the timing control signal d. The output signal of the first register 24 or the ADPCM code in the decoding process is input to the control signal S.
This circuit generates a predetermined quantization width based on 26a, and its output signal S27 is input to the adder 28 together with the output signal S29 of the second register 29. The output signal S28 of the adder 28 is input to the second register 29 and the input side of the D / A converter 30.

The adder 28 adds the output signal S27 of the quantization width unit 27 and the output signal S29 of the second register 29, and outputs an output signal S28 composed of a PCM reproduction value to the second register 29 and the D / A converter 30. Circuit. The second register 29 has a function of adding the output signal S28 of the adder 28 based on the control signal S26b. The D / A converter 30 is a circuit for converting the output signal S28 of the adder 28 into an analog reproduction value based on the timing control signal e. The output signal S30 is input to the analog comparator 23 and the analog reproduction waveform The signal is output to the output terminal 31 of A _out .

Next, the operation of the ADPCM encoding / decoding device will be described with reference to FIGS. 3 (1), (2) and 4, while (i) operating as an encoding device, and (ii) decoding device. The operation will be described separately. FIG. 3 (1),
(2) is an encoding timing chart of FIG. 1, and FIG. 4 is a decoding timing chart of FIG.

(I) When Operating as an Encoding Device The analog waveform A _in input from the input terminal 21 is converted into a sample-and-hold circuit 22 operated by a timing control signal a.
As a result, a constant analog value is held within a predetermined sampling period. The held analog value _Xn is the output signal S2
2 is supplied to one input side of the analog comparator 23. PCM playback value [ _n-1 ] stored in register 29
And the value [ _n-1 ] obtained by adding 0 by the adder 28 to D / A
The analog reproduction value _n-1 obtained by inputting to the converter 30 is
The output signal S30 is supplied to the other input side of the analog comparator 23. Then, the analog comparator 23 makes a comparison as shown in Expression (12), and supplies the result of the comparison to the register 24 and the encoding control circuit 26 in the subsequent stage in the form of an output signal S23.

The register 24 stores L _n1 as it is by the timing control signal b. The coding control circuit 26 outputs a control signal S26a based on the timing control signal C. If L _n1 = 0, the encoding control circuit 26 prompts the quantization width unit 27 to output [+ Δ _n / 2] and outputs L + _{n 1}
If = 1, to output the [-Δ _n / 2] from the quantization width 27.

The adder 28 outputs [ _n-1 ], which is the output signal S29 of the register 29, and [± Δ], which is the output signal S27 of the quantization width unit 27.
_n / 2] and adds, supplied to the D / A converter 30 in the form of its addition result _{[n-1 ± Δ n /} 2] the output signal S28. D / A converter 30
, Based on the timing control signal e, and supplies its output signal S30 to the other input side of the analog comparator 23 converts the output signal S28 to an analog value _{n-1 ± Δ n / 2} . Since the analog comparator 23 uses one of the inputs _Xn held by the sample-and-hold circuit 22 in the preceding stage, the analog comparator 23 outputs a comparison result as shown in Expression (13).

_{X n n-1 ± Δ n} / 2 X n ≧ n-1 + Δ n / 2 if _{L n2 = 1 X n <n} -1 + Δ n / 2 if _{L n2 = 0 X n ≧ n} -1 -Δ _n / 2 if _{L n2 = 0 X n <n} -1 -Δ n / 2 if L _n2 = 1 ... (13) downstream of the register 24 stores L _n2. Encoding control circuit 26 inputs the L _n2, L _n2 = 1 if the register 29 provides a control signal S26b for storing previous addition result of the adder _{28 [n-1 ± Δ n} / 2], If L _n2 = 0, the control signal S26b is not output to the register 29, and the register 29 holds the previous value as it is. Then, the quantizer 27 is prompted by the control signal S26a, and if L _n1 = 1, [+ Δ _n / 4] is added to L _n1
= 0, to output [-Δ _n / 4].

Then the adder 28 is the output signal S29 in the register 29 and _{[n-1 ± L n2 ×} Δ n / 2], the output signal S27 in the quantization width 27
In a [± Δ _n / 4] and adding, the addition result [X _n-1 ± L
The _{n2 × Δ n / 2 ± Δ} n / 4] in the form of the output signal S28 supplied to the D / A converter 30. The D / A converter 30 and the analog comparator 23 perform the operation as described above, and as a result, output a comparison result as shown in Expression (14).

_{X n n-1 ± L n2} × Δ n / 2 ± Δ n / 4 X n ≧ n-1 + L n2 × Δ n / 2 + Δ n / 4 if _{L n3 = 1 X n <n} -1 + L n2 × Δ _n / 2 + _{Δ n} / 4 if _{L n3 = 0 X n ≧ n} -1 -L n2 × Δ n / 2-Δ n / 4 if _{L n3 = 0 X n <n} -1 -L n2 × Δ n / 2-Δ _n / 4 if L _n3 = 1 ... (14) Then, the subsequent register 24 stores L _n3. The encoding control circuit 26 inputs L _n3 and sends the result to the register 29 based on the addition result of the previous adder 28 and the result of L _n3 [ _n−1 ± L _n2
× provides control signals S26b for storing _{Δ n / 2 ± L n3 ×} Δ n / 4].

Similarly, the adder 28 outputs the output value [ _n-1
± L and _{n2 × Δ n / 2 ± L} n3 × Δ n / 4], and adds the output value ± delta _n / 8 of the quantization scale 27, the addition result _{[n-1 ± L n2 ×} Δ n / 2
± give _{L n3 × Δ n / 4 ±} Δ n / 8] to the D / A converter 30. The D / A converter 30 and the analog comparator 23 perform the operation described above, and output a comparison result as shown in Expression (15).

_{X n n-1 ± L n2} × Δ n / 2 ± L n3 × Δ n / 4 ± Δ n / 8 Xn ≧ n-1 + L n2 × Δ n / 2 + L n3 × Δ n / 4 + Δ n / 8 If L _{n4 = 1 Xn <n-1} + L n2 × Δ n / 2 + L n3 × Δ n / 4 + Δ n / 8 If _{L n4 = 0 Xn ≧ n-} 1 -L n2 × Δ n / 2-L n3 × Δ n / 4-Δ _n / 8 If L _n4 = 0 Xn <if _{n-1 -L n2 × Δ n} / 2-L n3 × Δ n / 4-Δ n / 8 L n4 = 1 ... (15) and subsequent Register 24 stores L _n4 . The encoding control circuit 26 receives L _n4 and inputs the result to the register 29 according to the result of the previous addition performed by the adder 28 and the result of L _n4 [ _n-1 ± L _n2 × Δ _{n
/ 2 ± L n3 × Δ n} / 4 control signals S26b for storing _{± L n4 × Δ n / 8} ]
give.

The encoding control circuit 26 uses the control signal S26a to
Encourage 27 causes out an output value of [± Δ _n / 16], the register 29
The output value _{[n-1 ± L n2 ×} Δ n / 2 ± L n3 × Δ n / 4 ± L n4 × Δ n /
8] in the adder 28, and the addition result [ _n-1 ±
_{L n2 × Δ n / 2 ±} L n3 × Δ n / 4 ± L n4 × Δ n / 8 ± Δ n / 16] again, providing a control signal S26b for causing stored in the register 29.

The value stored in the register 29 is used as a comparison operation with the next analog input value _{Xn + 1} as [ _n ].

L _n1 , L _n2 , L _n3 , L _n4 sequentially stored in the register 24 are ADP
Output by output terminal 25 as a CM code L _n. At the same time, L _n is input to the quantizer 27, and Δn _{+ 1} is calculated by the equation (9).

The above is the calculation process performed within one sampling period, and the ADPCM code is sequentially generated for each sampling.

(Ii) ADPCM code L _n input than output terminal 25 operating as the decoding device is input to the encoding control circuit 26 by the timing control signal c.
The encoding control circuit 26 sets the output signal S27 of the quantization width unit 27 to always a negative value if L _n1 is 1, and sets the output signal S27 to a positive value if L _n1 is 0. Control. Next, the encoding control circuit 26 determines whether L _n2 is 1 or 0,
A control signal S26b for updating or not updating the result of adding 8 is given to the register 29. Hereinafter, the L _n3, the L _n4 running similar operation also _{L n (L n1, L n2} , L n3, L n4), register 2 to store the PCM reproduction values, such as (16) become.

_{[N-1 ± L n2 ×} Δ n / 2 ± L n3 × Δ n / 4 ± L n4 × Δ n / 8 ± Δ n / 16] ... (16) which is obtained by coding process of the device It is the same as [ _n ].

Thereafter, the value [ _n ] stored in the register 29 is output by the adder 28 as a result [ _n ] obtained by adding the other input to 0, and is supplied to the D / A converter 30. D
The / A converter 30 converts [ _n ] into an analog reproduction value _n , and outputs this from the output terminal 31 in the form of a signal _Aout . Then, the quantization width 27, from delta _n before and inputted L _n, (9) to calculate the delta _{n + 1} as in equation be provided to the input of the next ADPCM code L _{n + 1} become.

The present embodiment has the following advantages (a) to (c).

(A) Instead of the conventional A / D converter 3, an analog comparator 23
And the output signal S30 of the D / A converter 30 used for analog reproduction is commonly used in the process of encoding and decoding, so that the ADPCM using the conventional A / D converter 3 is used. It has an advantage that it has a simpler circuit configuration than the encoding / decoding device and can perform ADPCM operation in almost the same operation process.

(B) A / A that affected the signal conversion distortion of the entire device
The removal of the D converter 3 and the use of the D / A converter 30 in both the encoding process and the decoding process to cancel the distortion can substantially reduce the signal conversion distortion between the PCM and the ADPCM. And the distortion due to the resolution of the D / A converter 30 can be suppressed only to
Due to this, the signal distortion of the entire apparatus can be accurately reduced.

(C) In both the encoding and decoding processes, the encoding control circuit 2
6.Since the circuit configuration is such that the quantization width unit 27, the adder 28, the register 29, and the D / A converter 30 are shared, the circuit scale of the entire device can be reduced by reducing extra circuits due to the shared use. In addition, the cost can be reduced.

(Effects of the Invention) As described in detail above, according to the first and second inventions, an analog comparator is provided, and the D / D
Since the output of the A-converter is commonly used in the encoding and decoding processes, the signal conversion distortion is reduced by removing the conventional A / D converter, and the output of the D / A converter is encoded. Thus, the distortion can be reduced by using the same in the decoding process to cancel the distortion, and thereby the signal conversion distortion can be accurately reduced.

Furthermore, in the first invention, the circuit configuration is such that the encoding control circuit, the quantization width unit, the adder, the second register, and the D / A converter are used in both the encoding and decoding processes. As a result, the circuit scale of the entire device can be reduced and the cost can be reduced by reducing extra circuits due to dual use.

Similarly, in the second invention, the encoding control circuit, the quantizer, the adder, the register,
And a circuit configuration that also serves as a D / A converter,
The reduction of the extra circuit due to the dual use can reduce the circuit scale of the entire device and can reduce the cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an ADPCM encoding / decoding device showing an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional ADPCM encoding / decoding device, and FIGS. 3 (1) and (2). Is the first
FIG. 4 is an encoding timing diagram, and FIG. 4 is a decoding timing diagram of FIG. 21 ... input terminal, 22 ... sample-and-hold circuit, 23 ...
... Analog comparators, 24,29 ... First and second registers, 25
... I / O terminals, 26 ... Encoding control circuit, 27 ... Quantization width unit, 28 ... Adder, 30 ... D / A converter, 31 ... Output terminal.

Claims (2)

(57) [Claims] 1. An adaptive differential pulse code modulation encoding / decoding device for encoding an analog waveform into an adaptive differential pulse code modulation code and decoding the adaptive differential pulse code modulation code, wherein the analog waveform is sampled. A sample-and-hold circuit for holding the same for a certain period of time; a digital / analog converter for converting an addition result consisting of a pulse code modulation reproduction value output from the adder to an analog reproduction value; The digital /
An analog comparator that compares the output of the analog converter and outputs a signal corresponding to the output; a first register that stores the output of the analog comparator; and an output of the first register in an encoding process. An input / output terminal for outputting an adaptive differential pulse code modulation code from outside in a decoding process, and an output of the analog comparator in an encoding process, A first control signal and a second control signal are output based on the output of the device, and during the decoding process, the adaptive differential pulse code modulation code input from the outside is input, and a third control An encoding control circuit that outputs a signal and a fourth control signal; and, in an encoding process, receives the first control signal and the output of the first register, and generates a predetermined quantization width based on the input. And decrypt In the quantization step, the third control signal and the adaptive differential pulse code modulation code input from the outside are input, and a quantization width generator that generates a predetermined quantization width based on the input signal; A second register for storing an addition result output from the adder based on the second control signal, and storing an addition result output from the adder based on the fourth control signal in a decoding process; An adaptive difference pulse code modulation encoding / decoding apparatus, comprising: an adder that adds an output of the quantization width unit and an output of the second register to output an addition result. . 2. An adaptive differential pulse code modulation encoding / decoding device for encoding an analog waveform into an adaptive differential pulse code modulation code and decoding the adaptive differential pulse code modulation code, wherein the analog waveform is sampled. A sample-and-hold circuit for holding the same for a certain period of time; a digital / analog converter for converting an addition result consisting of a pulse code modulation reproduction value output from the adder into an analog reproduction value; and an output of the sample-and-hold circuit. The digital /
An analog comparator that compares the output of the analog converter and outputs a signal corresponding to the output; and outputs an adaptive differential pulse code modulation code that is an output of the analog comparator in a coding process, and outputs an external signal in a decoding process. An input / output terminal for inputting a more adaptive differential pulse code modulation code; an input of an output of the analog comparator in an encoding process; a first control signal and a second control based on an output of the analog comparator; A coding control circuit that outputs a signal, and in the decoding process, receives the externally input adaptive differential pulse code modulation code, and outputs a third control signal and a fourth control signal based on the adaptive difference pulse code modulation code; In the encoding process, the first control signal and the output of the analog comparator are input, a predetermined quantization width is generated based on the input, and in the decoding process, the third control signal and the external Entered A differential width pulse code modulation code, and a quantization width generator that generates a predetermined quantization width based on the input signal; and an addition result output by the adder based on the second control signal in an encoding process. A register for storing and storing an addition result output by the adder based on the fourth control signal in a decoding process, and adding an output of the quantizer and an output of the register to obtain an addition result. An adaptive differential pulse code modulation encoding / decoding device, comprising: the adder for outputting.