JP2603631B2 - Voice analysis and synthesis device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a DPCM (Differential Coded Modulation) system and an ADPCM
The present invention relates to a digital recording / reproducing apparatus based on (adaptive differential coding and modulation) system.

<Prior Art> Conventionally, as a digital recording / reproducing apparatus, there is an ADM method (adaptive delta modulation method) in which hardware is simplified by a simple quantization method. This ADM method
Using a quantization width that can adaptively change according to the amplitude of the audio, the level of the sampled audio signal is 1
A pulse of “+1” is output when the level of the quantization width exceeds the level before the sample by one or more steps, and a pulse of “−1” (or “0”) is output when the level decreases by one or more steps.

<Problems to be Solved by the Invention> However, the above-mentioned conventional ADM digital recording / reproducing apparatus uses the peak value of the sampled audio signal as
The hardware is very simple because it quantizes with a step wave that can only be changed by one quantization width,
There is a problem that the quantization error is large and the sound quality of the encoded audio signal is poor. On the other hand, a digital recording / reproducing apparatus created with emphasis on sound quality has a problem that its hardware is very complicated.

Therefore, an object of the present invention is to use an ADPCM method or a DPCM method, which has a large information compression effect, in order to obtain high sound quality, and to configure a circuit for quantization with simple hardware at that time, thereby achieving a simple operation. It is an object of the present invention to provide a speech analyzing / synthesizing apparatus capable of obtaining a synthesized speech having good sound quality with the configuration.

<Means for Solving the Problems> In order to achieve the above object, a speech analysis / synthesis device of the present invention analyzes and encodes a sampled input speech signal, and converts a coded speech signal into a synthesized speech signal. In the speech analysis / synthesizing apparatus having a quantizer for decoding, the quantizer is shared between the encoding and the decoding, and in the case of encoding, the wave of the sampled adjacent input speech signal is used. The difference value between the high value and the predicted peak value and the quantization width are input to output a quantization code and a quantization error, and the predicted peak value is obtained based on the peak value and the quantization error, while decoding In the case of quantization, a quantization code and a quantization width are input and a prediction difference value is output.

Also, when performing the encoding, the quantizer repeatedly performs the operation or addition of the quantization width on the difference value until the polarity of the result is reversed, and the final operation result is quantized. While outputting as an error, when performing the decoding, an addition / subtraction means for repeatedly adding or subtracting the quantization width by the number of times based on the quantization code and outputting a final result as the prediction difference value; Counting means for counting the number of repetitions of subtraction or addition by the means and outputting the count result in the case of the encoding as the quantization code.

Further, the quantizer, when performing the encoding,
The calculation of the quantization code and the calculation of the quantization error are performed based on a common control signal.

<Operation> According to the present invention, a quantizer is shared for encoding and decoding. In encoding, a current predicted peak value is obtained based on an input speech signal and a quantization error, Since the difference value is obtained from the high value and the predicted peak value before the present, a synthesized voice with good sound quality can be obtained with a simple configuration.

In addition, the quantizer includes an addition / subtraction unit and a counting unit in order to obtain an output result of a quantization code, a quantization error, and a prediction difference value.

Further, since the quantizer calculates the quantization code and the quantization error based on the common control signal, the coding (calculation of the quantization code) and the quantization (calculation of the quantization error) can be performed with a simple configuration. Can be run in parallel.

<Example> Hereinafter, the present invention will be described in detail with reference to an illustrated example.

FIG. 1 is a block diagram showing the encoding and decoding of an ADPCM-type speech analysis / synthesis apparatus according to the present invention. This speech analysis / synthesis apparatus operates as follows.

At the time of sign, as shown in FIG.
The sampled peak value Xn of the current audio waveform and the predicted sample value n− ₁ one sample before are input. As a result, a difference value dn is calculated and output to the quantizer 11. Meanwhile, 1
Quantized code Cn obtained by quantizing the difference value before sample
When _-1 is input to the Δ control circuit 12, the Δ control circuit 12
Determines the quantization width Δn based on the quantization code Cn− ₁ of the difference value one sample before, and outputs it to the quantizer 11.
The quantizer 11 to which the difference value dn and the quantization width Δn are input quantizes the difference value dn, and as a result, the current difference value dn
Is output, and a quantization error en for obtaining the current predicted peak value n is calculated from the current peak value Xn and output to the adder 14. The quantization code Cn of the difference value dn is used to determine the next quantization width as described above, and is recorded on a memory medium (not shown) as a quantization code for speech synthesis, or not shown. Sent to the communication line. The quantization error en output from the quantizer 11 and the sampled current peak value Xn are input to the adder 14, and the quantization error en is subtracted from the current peak value Xn to obtain a predicted peak value n. Is calculated. This predicted peak value n is subtracted from the next sample peak value as described above, and the difference value input to the quantizer 11 is obtained.

Thus, the encoding system of FIG. 1 sequentially outputs the quantized code Cn by sequentially inputting the input sample waveform values Xn. Here, the Δ control circuit 12 adaptively controls the size of the current quantization width Δn according to the size of the quantifier code Cn- ₁ which is the quantization code of the difference value one sample before, and obtains the original waveform. It is used to improve the following performance.

At the time of decoding, as shown in FIG. 1 (b), an input quantization code Cn 'read from a memory medium or received from a communication line is input to a quantizer 11, while C
n'- quantization width Derutaenu'- ₁ determined by the Δ control circuit 12 on the basis of ₁ is input to the quantizer 11, the quantizer 11 based on this, the prediction difference value Is generated and output to the adder 15. The adder 15 receives the input prediction difference value When one sample before the predicted peak value (composite value) _n'1 and adds the outputs the calculated current expected peak value (composite value) n '. As described above, the encoding system shown in FIG. 1B sequentially outputs the predicted peak value (synthetic value) n 'by sequentially inputting the quantization code Cn'. In FIG. ₁ , n represents the current sample time, and n- ₁ represents the time one sample before. The symbol ∧ represents the data after quantization. FIG. 2 shows the correspondence between each symbol in FIG. 1 and the input waveform.

FIG. 3 shows a block diagram of the quantizer 11 in FIG. The input quantization width Δn is input to one input terminal of the adder / subtractor 22 via the shift circuit 21. The difference value dn that is input only at the time of sign is latched as the initial value at the time of sign.
Held at 23. The output of the latch 23 is applied to the adder / subtractor 22.
The adder / subtracter 22 performs addition and subtraction based on the input quantization width Δn and the data input from the latch 23, and outputs the result to the latch 23. After the difference value dn is held in the latch 23 as an initial value, the output of the adder / subtractor 22 is input to the latch 23, and the clock pulse CCK input from the clock circuit 24 is input to the output from the adder / subtractor 22. Is held. After being held in the latch 23 as an initial value, the difference value dn is disconnected from the input terminal of the latch 23, and is not input to the latch 23 thereafter. The difference value dn is held in the latch 23 (asynchronously) regardless of the clock pulse CCK of the clock circuit 24.

The clock circuit 24 supplies the quantizer with a quantization width Δn
Is input to the output of the signal SC from the adder / subtracter 22, and at the time of decoding, the quantization width Δ
From the time when n 'is input, the borrow signal BR is output from the counter 25.
Clock pulse CC at regular intervals until
Outputs K. Then, the signal SC or the borrow signal BR
Is input, one more clock pulse is continuously generated.
While outputting CCK, a control signal SFT for halving the output of the shift circuit 21 is output to the shift circuit 21. The clock pulse CCK is a clock signal for the latch 23 and also a clock signal for the counter 25. Above counter
Numeral 25 operates as an up-counter using the clock pulse CCK as a clock at the time of code, and at the end of counting, adds the MSB of dn to the MSB of its output to obtain a quantized code Cn. Further, the counter 25 operates as a down counter using the clock pulse CCK as a clock at the time of decoding, and as an initial value.
The countdown is performed using the clock pulse CCK as a clock until the quantization code Cn 'excluding the MSB is input and its value becomes 0. The counter 25 uses the borrow signal BR as a stop signal when the count reaches 0,
24, the output of the clock pulse CCK is stopped, and the control signal SFT is output.

Shift circuit 21 normally outputs data equal to the input data. However, when the control signal SFT output from the clock circuit 24 is input, the input data is shifted by one bit, and the output data becomes half the value of the input data. This operation has an intermediate rise (mid-riser (mid
−riser)) method (see FIG. 4), so that 1/1 of the quantization width Δn required to calculate the quantization error en is used.
This is done to get a magnitude value of 2. Adder / subtractor 22
Operates as follows depending on the sign of the difference value dn at the time of sign. That is, when the sign of the difference value dn is positive, the latch 23
When the sign of the difference value dn is negative, it operates as an adder that adds the quantization width Δn to the data input from the latch 23 when the sign of the difference value dn is negative. I do. Also, at the time of decoding, the MSB of the input quantization code Cn 'is similarly determined by the MSB of the input quantization code Cn'.
Operates as an adder when is 0, and operates as a subtractor when it is 1. The output signal SC of the adder / subtractor 22 is output only at the time of sign, and is output when the sign of the difference value dn (0 when positive or 0, 1 when negative) and the carrier of the adder / subtractor 22 match. This signal SC is a clock pulse input to the clock circuit 24 and output from the clock circuit 24.
The output of CCK is stopped, and the control signal SFT is output.

 The quantizer having the above configuration operates as follows.

A. Signing When the difference value dn is dn ≧ 0, the input quantization width Δn is repeatedly subtracted from the input difference value dn to obtain dn−Δn−
The calculation of Δn−Δn... Is performed, and the number of operations until the calculation result becomes negative (signal SC is output) is counted by the counter 25. By loading −1 into the counter 25 in advance as an initial value, , A number which is one less than the number of operations is output from the counter 25 as the quantization code Cn. The signal SC is output from the adder / subtractor 22 at the moment when the operation result becomes negative, and as a result, the clock circuit 24 outputs the control signal SFT, and before the latch 23 holds the negative operation result, The quantization width Δ
n is multiplied by 1/2, and the adder / subtracter 22 uses the value Δn / 2 to perform the operation again, and holds the obtained value in the latch 23, and the latch 23 stores the value held last. Is output as the quantization error en, and the calculation routine of Cn, en stops.

On the other hand, when the difference value dn is dn <0, the adder / subtractor 22 outputs dn +
The calculation of Δn + Δn + Δn +... Is performed until the result becomes positive (the signal SC is output), and the number smaller than the number of operations is output from the counter 25 as the quantization code Cn. In the last round, Δn / 2 is added as in the case of dn ≧ 0, and the result is held in the latch 23. The latch 23 outputs the last held value as the quantization error en.

B. At the time of decoding When the MSB of the input quantization code Cn 'is 1,
The value of the difference value Δn input by the number of times of the value excluding the MSB of the input quantization code Cn ′ is subtracted to obtain −Δn−Δn−Δn− ·
・ ・ Operation, and finally subtract Δn / 2,
The result is held in the latch 23. The latch 23 uses the last value held as the predicted difference value. Output as When the MSB of the input quantization code Cn ′ is 0, Δn is added by the number of times excluding the MSB of the input quantization code Cn ′, and finally, Δn / 2 is added to the value,
Use that value as the prediction difference value Output as The process of calculating by multiplying the quantization width Δn by 1/2 is the same as that at the time of encoding, but as described above, the clock circuit
In order to output the control signal SFT to the shift circuit 21 from 24,
When decoding, the counter 25 counts down and counts 0, and outputs a borrow signal to the clock circuit 24.

Here, the operation of the quantizer will be described with a specific example.

(A) At the time of coding In the case of the difference value dn = 7 and the quantization width Δn = 3, as shown in FIG.
Is 2 and the quantization error en is 0 (cut off after the decimal point). As described above, dn = 7 is held as the initial value of the latch 23, and 3 is set as the quantization width Δn in the shift circuit 21.
Is input to the adder / subtractor 22 via the. When the quantization width Δn = 3 is input, the adder / subtracter 22 calculates 7−3 = 4 and outputs data “4”, and the clock circuit 24 outputs the quantization width Δn.
= 3, the output of the clock pulse CCK starts, and the first clock pulse CCK is latched.
Input to 3 and data "4" is held. This data “4”
Becomes the input data of the adder / subtractor 22 at the same time as being held in the latch 23, and the second operation 4-3 = 1 is performed. This data "1" is the next clock pulse output from the clock circuit 24 to the latch 23. It is held in the latch 23 by CCK. Further, the third calculation 1-3 = -2 is performed. At this time, the signal SC is output from the adder / subtractor 22 to the clock circuit 24, and the holding of the data "-2" in the latch 23 is stopped. Then, the clock circuit 24 outputs the control signal SFT to the shift circuit 21, and
The quantization width Δn = 3 is multiplied by 1/2 (cut to the decimal point),
Instead of 1-3 = -2 in the above operation, Is performed. The clock circuit 24 receives the signal SC and outputs the last clock pulse CCK.
3 latches the data "0". The final operation result “0” held in the latch 23 is latched as the quantum
Output from 23. During that time, the counter 25 has a clock circuit
The counter 25, to which three clock pulses CCK are input from 24 and loaded with -1 as an initial value, counts up three times, and as a result, outputs "2" which is one less than the counted number as the quantization code Cn. . Therefore, the same Cn = 2, en = 0 as the above logical value can be obtained.

(B) Decoding When the quantization width Δn ′ = 3 and the input quantization code Cn ′ = 2, the counter 25 is loaded with Cn ′ = 2 in advance, and the latch 23 is cleared by the latch 23. Dn = 0 is held as an initial value for performing the operation. Shift circuit 21 in adder / subtractor 22
When the quantization width Δn ′ = 3 is input via
Since it is 0, the adder / subtractor 22 performs addition 0 + 3 = 3 to obtain data "3". At the same time, a clock pulse CCK starts to be output from the clock circuit 24. When the first clock pulse CCK is input to the latch 23, the latch 23 holds the data "3" and the clock circuit 24
The counter 25 is counted down by outputting the clock pulse CCK to the above, and the content of the counter 25 is set to 1. At the same time, the adder / subtractor 22 performs an operation of 3 + 3 = 6, and the latch 23 outputs data "6" by the same operation as described above, and the counter 25 counts down again to 0. counter
When 25 becomes 0, the counter 25 outputs the borrow signal BR to the clock circuit 24, and the clock circuit 24 outputs the control signal SFT to the shift circuit 21. When the control signal SFT is input to the shift circuit 21, the quantum width Δn ′ is halved, and the decimal part is cut off to become “1”. The addition / subtraction circuit 22 calculates the last operation 6
+ Δn / 2 (cut off after the decimal point) = 7, and outputs “7”. This data “7” is held in the latch 23 at the last clock pulse CCK of the clock circuit 24, and the predicted difference value Is output as

As described above, by providing the ADPCM-type speech analysis / synthesis apparatus with a simple hardware quantizer, it is possible to obtain a synthesized speech having a simple structure and good sound quality.

In the above embodiment, an ADPCM digital recording / reproducing apparatus is used. However, a DPCM digital recording / reproducing apparatus using a difference value between sampled adjacent audio signals may be used similarly to the ADPCM method.

<Effects of the Invention> As is clear from the above, according to the present invention, it is possible to obtain a speech analysis / synthesis device that outputs a synthesized speech signal of good sound quality with simple hardware.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of a speech analysis / synthesis apparatus according to the present invention, FIG. 2 is a diagram showing correspondence between signals and input waveforms in FIG. 1, and FIG. FIG. 4 is a block diagram of a quantizer in the example, and FIG. 4 is a diagram showing a quantization method of an intermediate rising system. 11: Quantizer, 12: Δ control circuit, 21: Shift circuit, 22: Adder / subtractor, 23: Latch, 24: Clock circuit, 25: Counter.

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Tomokazu Morio 22-22 Nagaike-cho, Abeno-ku, Osaka City Inside Sharp Corporation (56) References JP-A-61-182699 (JP, A) JP-A-59-49616 (JP, B2) Digital Speech Processing Sada Furui, written by Mori, September 1985, Tokai University Press, P.S. 105− 106

Claims (3)

(57) [Claims] 1. A speech analyzing / synthesizing apparatus having a quantizer for analyzing and encoding a sampled input speech signal, while decoding the encoded speech signal into a synthesized speech, wherein the quantizer comprises: When the encoding and the decoding are shared and the encoding is performed, the difference value and the quantization width between the peak value and the predicted peak value of the sampled adjacent input audio signal are input and the quantization code is input. Along with outputting the quantization error, the predicted peak value is obtained based on the peak value and the quantization error, while when decoding, a quantization code and a quantization width are input and the prediction difference value is calculated. A speech analysis / synthesis device characterized by outputting. 2. The encoding device according to claim 1, wherein, when performing the encoding, the quantizer repeats the subtraction or addition of the quantization width with respect to the difference value until the polarity of the result is reversed. While outputting as the quantization error, when performing the decoding, adding or subtracting means for repeatedly adding or subtracting the quantization width by the number of times based on the quantization code, and outputting a final result as the prediction difference value; And a counting means for counting the number of repetitions of subtraction or addition by said addition / subtraction means, and outputting a count result in said encoding as said quantization code. A speech analysis / synthesis apparatus according to item 1. 3. The quantizer according to claim 1, wherein, when performing said encoding, said quantizer calculates said quantization code and said quantization error based on a common control signal. The speech analysis / synthesis device according to claim 1.