JP3200875B2 - ADPCM decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ADPCM decoder and, more particularly, to an ADPCM decoder used for speech synthesis.

[0002]

2. Description of the Related Art A conventional ADPCM decoder, as shown in FIG. 4, determines an L register 1 for latching ADPCM code data, and the amount of movement of a quantization width pointer by decoding the value of the L register 1. A decoder 2 which latches the output of the decoder 2 and the value of the quantization width pointer
A register 4, an adder / subtracter 11 for performing addition and subtraction between the output of the A register 4 and the output of the decoder 2, a limiter 3 for limiting the result of addition and subtraction to a range between an upper limit and a lower limit of a quantization width pointer, and an L register 1 Value data table ROM 5 for selecting an address by the A register 4 and outputting a difference value of the next sampling point, an X register 7 for latching the result of sequentially accumulating the difference values, and a value of the X register 7 An adder / subtracter 6 that adds or subtracts the output of the difference value data table ROM 5 to calculate the amplitude value of the next sampling point, and a DA converter 8 that converts the output of the X register 7 into an analog signal.

[0003] The ADPCM method is a data compression method using the strength of correlation between adjacent samplings of audio.
In this method, a difference between amplitude values at successive sampling points is to be compression-coded. A difference value selected by the current quantization width pointer and the amplitude data of the ADPCM code, with the ADPCM code being a 4-bit code consisting of a bit representing positive and negative polarities and a 3-bit representing amplitude, and having a quantization width pointer of 3 bits. The amplitude value of the next sampling point is calculated by adding or subtracting the data to the amplitude value of the current sampling point according to the value of the polarity bit of the ADPCM code, and the value obtained by multiplying the current quantization width by the prediction coefficient is calculated as the following value. Instead of performing the multiplication processing using the quantization width of the sampling point, the multiplication result is stored in advance as a table in the ROM as difference value data.

Before decoding the ADPCM code, the initial value 0 is put in the A register 4 and the midpoint data 80 of the output waveform is stored in the 8-bit X register 7 for accumulating the amplitude data.
Add H. To find the amplitude value of the first sampling point, the ADPCM code data of L register 1 and A
The value of the quantization width pointer of the register 4 is input as the address of the difference value data table ROM5, and the output of the difference value data table ROM5 outputs the difference data of the maximum of 8 bits determined by the amplitude data of the ADPCM code and the current quantization width. The amplitude data and 1-bit positive / negative sign data are output.

The contents of the difference value data table ROM 5 are as shown in Table 1 below, and adding or subtracting the value of the A register is equivalent to multiplying the difference value data by a prediction coefficient. I have.

[0006]

[Table 1]

The X register 7 is set according to the value of the sign data.
And the amplitude data output from the difference value data table ROM 5 are added or subtracted, the result is latched in the X register 7, and the DA converter 8 outputs an analog signal. After the X register latch signal Sx is set to low level and the value of the X register 7 is latched, 3 bits of the amplitude data of the ADPCM code are decoded by the decoder 2 as shown in Table 2 below, and the output of the decoder 2 and the A register 4 The value is added or subtracted. If the operation result becomes a negative value by the limiter 3, 0 is inputted to the A register 4, and if the operation result becomes a value of 8 or more, 7 is inputted to the A register 4.

[0008]

[Table 2]

As described above, the value from 0 to 7 is stored in the A register 4 and is used as a quantization width pointer for selecting the difference value data multiplied by the prediction coefficient of the next sampling point.

As described above, each time new ADPCM code data comes, a difference value is selected from the L register 1 and the A register 4 as an address of the difference value data table ROM 5 and added to or subtracted from the X register 7. ,
The amplitude value of the next sampling point is obtained and the DA converter 8
Outputs an analog signal, latches the value of the X register 7 and then decodes the value of the L register 1 by the decoder 2 to A
ADPCM is repeated by repeating the operation of updating the value of the quantization width pointer by adding or subtracting from the register 4.
Data decryption processing can be performed.

[0011]

SUMMARY OF THE INVENTION The conventional ADPCM
In the system decoder, when a large amplitude original sound waveform as shown in FIG. 5 is sampled and subjected to ADPCM encoding, the difference value Δ2 is added to the sampling value S1 to obtain the sampling value S2.
After obtaining 2, the next sampling point is obtained. At this time, if the value of the quantization width pointer is large, the absolute value of the difference value data will change greatly, and there may be cases where only Δ3 ′ and Δ3 can be selected as the amplitude data of the ADPCM code. It becomes smaller when Δ3 is selected than Δ3 ′. Even if Δ3 is selected and ADPCM encoded to reduce the error with the original sound waveform,
Since the ADPCM code is data obtained by compressing the difference value, even if the amplitude data obtained by accumulating the difference value exceeds the maximum value of FFH, it can be encoded as it is.

On the other hand, after subtracting the difference value Δ8 from the sampling value S7 to obtain the sampling value S8, the amplitude data of the ADPCM code is converted to Δ9 ′ and Δ9 ′ at the next sampling point.
When only 9 can be selected, the error from the original sound is smaller when .DELTA.9 is selected than when .DELTA.9 '. Even if Δ9 is selected and ADPCM-coded to reduce the error from the original sound waveform, even if the amplitude data in which the difference values are accumulated becomes smaller than the minimum value of 0, the coding can be performed as it is.

When the ADPCM data obtained by encoding the amplitude data from S1 to S12 in FIG. 5 is reproduced by the decoder in FIG. 4, as shown in the waveform diagram in FIG.
Is added to X2, and when Δ3 is added to X2, the added value exceeds FFH, so that X3 becomes a value close to 0. On the other hand, the value obtained by subtracting Δ8 from X7 becomes X8, and X
When Δ9 is subtracted from 8, a borrow occurs, the subtraction value X9 becomes a value close to FFH, and as the decoded waveform of the portion from X1 to X12, a completely different value is generated in which the amplitude values of X3 and X9 are exactly opposite to the original sound. There is a problem that a large amplitude change is generated in the decoded waveform which is not present in the original sound waveform.

An object of the present invention is to solve the above problem and to provide an ADPCM decoder capable of decoding a faithful original sound waveform by removing distortion of a decoded waveform.

[0015]

According to the present invention, an ADP is provided.
The CM code data and the difference value selected by the quantization width pointer are sequentially accumulated by the adder / subtractor and held in the first register.
In the ADPCM decoder, the output is converted into an analog signal by an n-bit DA converter and output, and the ADPCM code data is decoded by a decoder to sequentially update the value of a quantization width pointer. The accumulator of the difference value is performed up to (n + 1) bits by a calculator, the difference value up to the current sampling point is accumulated, and the difference value at the next sampling point is added or subtracted (n +
1) a second register for outputting a cumulative value of bits,
When the most significant bit of the second register overflows, the lower n bits of the accumulated value are not transferred to the n-bit DA converter, and the n-bit DA converter overflows.
The value before over left to held in the first register
And a controlling gate circuit.

[0016]

FIG. 1 is a block diagram showing an embodiment of the present invention. This embodiment is different from the conventional example in that the S register 9 and A
An ND gate 10 is added.

That is, an L register 1 for latching ADPCM code data, a decoder 2 for decoding the value of the L register 1 to determine the moving amount of the quantization width pointer, and an A for latching the value of the quantization width pointer. A register 4; an adder / subtracter 11 for performing addition and subtraction between the output of the A register and the output of the decoder 2; a limiter 3 for limiting the result of addition and subtraction to a range between an upper limit and a lower limit of a quantization width pointer; A difference value data table ROM 5 for selecting an address by the register 4 and outputting a difference value of the next sampling point, an (n + 1) -bit S register 9 for latching the result of sequentially accumulating the difference values, and an S register An adder / subtractor 6 that adds or subtracts the output of the difference value data table ROM 5 to the value of 9 to calculate the amplitude value of the next sampling point , AND gate 10 for taking an X register 7 which data of the lower n bits of the S register 9 are inputted, the AND logic of the inverted signal and the X register latch signal Sx signal S _{n + 1} most significant bits of the S register 9 And converts the output of the X register 7 into an analog signal by using the output of the AND gate 10 as a latch signal of the X register 7.
A converter 8 is provided.

Next, the operation of the ADPCM decoder will be described. According to this embodiment, it is assumed that a large amplitude original sound waveform shown in FIG. 2 is sampled and ADPCM encoded. In this case, after the difference value Δ2 is added to the sampling value S1 to obtain the sampling value S2, Δ3 having the smallest error from the original sound waveform is selected as the next difference value, and ADPCM is performed.
After encoding, the amplitude of S3 in which the difference value is accumulated is the maximum value of F3.
FH will be exceeded.

On the other hand, after subtracting the difference value Δ8 from the sampling value S7 to obtain the sampling value S8, the next difference value is selected as Δ9, which has the smallest error from the original sound waveform, and ADP is selected.
When the CM coding is performed, the amplitude of S9 in which the difference values are accumulated becomes equal to or smaller than the minimum value of 0.

When ADPCM data obtained by encoding the amplitude data from S1 to S12 in FIG. 2 is reproduced by a decoder with n = 8, as shown in FIG. 3, the value obtained by adding Δ2 to X1 is X2 When Δ3 is added to X2, the addition value exceeds FFH. However, since the adder / subtractor 6 and the S register 9 for latching the operation result have 9 bits, the most significant bit signal _{Sn + 1} of the S register is the lower 8 bits. It becomes 1 due to carry.

When the signal Sn _{+ 1} becomes 1, the AND gate 1
Since the output of 0 is fixed to 0 irrespective of the value of the X register latch signal Sx, the latch signal of the X register 7 is not generated, and the lower 8 bits of the S register latching the accumulated value of the difference value are not generated. The value is not transferred to the X register 7, and X3 keeps the same amplitude value as X2.

Next, the signal S _{n + 1} the amplitude value obtained by accumulating the Subtracting difference value Δ4 becomes less FFH from S3 0
Becomes When the signal _{Sn + 1} becomes 0, an X register latch signal Sx is output to the output of the AND gate 10, and the value obtained by accumulating the difference values of the lower 8 bits of the S register is stored in the X register 7.
Performs a normal operation of being latched as X4 and being output as an analog signal by the DA converter 8.

In FIG. 3, the value obtained by subtracting .DELTA.8 from X7 becomes X8. When .DELTA.9 is subtracted from X8, the subtracted value becomes 0H or less. Therefore, the highest bit signal S _{n + 1} of the S register 9 is obtained. When the signal _{Sn + 1} becomes 1, AN
Since the output of the D gate 10 is fixed to 0 irrespective of the value of the X register latch signal Sx, no latch signal of the X register 7 is generated and the lower 8 bits of the S register 9 latching the accumulated value of the difference value. The value of the bit is not transferred to the X register 7, and the amplitude of X9 remains the same as that of X8.

Next, when .DELTA.10 is added to S9, the adder / subtractor 6 carries, and the arithmetic output becomes a value of 0H or more, so that the signal Sn _{+ 1} becomes 0. When the signal S _{n + 1} becomes 0, A
An X register latch signal Sx is output to the output of the ND gate 10, and a value obtained by accumulating the difference values of the lower 8 bits of the S register 9 is latched in the X register 7 as X10.
Converter 8 performs a normal operation of outputting an analog signal.

[0025]

As described above, the ADPC of the present invention
When the decoding process is performed by the M-system decoder, a decoded waveform that is faithful to the sampling waveform is obtained. Even if the amplitude value obtained by encoding the original sound and accumulating the difference values exceeds the scale, a large amplitude change that is not present in the decoded waveform. Does not occur. Furthermore, the conventional ADPCM decoder is completely AD
PCM code data is compatible, and even if the value obtained by accumulating the difference values exceeds the output range of the DA converter, the correct amplitude value is always output except at the sampling point where the difference value exceeds the output range, and only a simple circuit needs to be added. Therefore, it is easy to make a semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a waveform diagram of original sound waveform coded data for explaining FIG. 1;

FIG. 3 is a waveform chart of signal processing of the encoded data of FIG. 2 by the decoder of FIG. 1;

FIG. 4 is a block diagram showing an example of a conventional ADPCM decoder.

FIG. 5 is a waveform chart of original sound waveform coded data for explaining FIG. 4;

FIG. 6 is a waveform chart of the encoded data of FIG. 5 decoded by the decoder of FIG. 4;

[Explanation of symbols]

 Reference Signs List 1 Latch of L register 2 Decoder 3 Limiter 4 Latch of A register 5 Difference value data table ROM 6,11 Adder / subtracter 7 Latch of X register 8 DA converter 9 Latch of S register 10 AND gate

Claims (1)

(57) [Claims] 1. An ADPCM code data and a difference value selected by a quantization width pointer are sequentially accumulated by an adder / subtracter, and are sequentially accumulated .
1 is converted into an analog signal by an n-bit DA converter and output.
In an ADPCM decoder in which M code data is decoded by a decoder and the value of a quantization width pointer is sequentially updated, the adder / subtractor performs the accumulation operation of the difference value up to (n + 1) bits and performs the operation up to the current sampling point. The difference value is accumulated, and the difference value at the next sampling point is added or subtracted, and the (n + 1) -bit accumulated value is output .
And second register, the most significant bit of the second register
When the overflow occurs, the lower n bits of the accumulated value are not transferred to the n-bit D / A converter, and the value before the n-bit D / A converter overflows is stored in the first register.
And a gate circuit for controlling the ADPCM decoder while holding it .