JP3029963B2 - Burst waveform generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst waveform generator used in a transmission section of digital mobile communication, and more particularly to a burst waveform generator controlled by a ramp with a small power consumption and a small circuit scale. It is what was constituted.

[0002]

2. Description of the Related Art In a transmission section of digital mobile communication, data is converted into a discrete burst signal using a burst waveform generator in order to transmit data in a time-division manner.
At this time, if the signal is cut out in a rectangular shape, the spectrum spread in transmission becomes large. To suppress this, ramp control for smoothly changing the waveform at both ends of the burst signal is performed.

As shown in FIG. 7, a conventional burst waveform generator includes an input terminal 1 to which transmission data is applied, a waveform data generation circuit 2 for outputting binary waveform data corresponding to the transmission data, A ramp control circuit 7 for performing ramp control on the output of the data generation circuit 2, a D / A converter 4 for converting binary code data output from the ramp control circuit 7 into an analog sampled value signal, / A converter 4
And a post-filter 5 for smoothing the output waveform of FIG.

The ramp control circuit 7 includes a window function generating circuit 71 for generating a window function and a multiplier 72 for multiplying the output of the waveform data generating circuit 2 by a window function generated from the window function generating circuit 71. Is provided.

In this burst waveform generator, when binary data to be transmitted is applied to the input terminal 1, the waveform data generator 2 outputs waveform data corresponding to the binary data to the ramp control circuit 7. , The ramp control circuit 7 multiplies the binary waveform data by a window function as shown in FIG. 8B obtained from the window function generator 71 through a multiplier 72 to determine the rise and fall of the burst. Deforms smoothly.

The output of the ramp control circuit 7 is converted into an analog sampled value signal by a D / A converter 4 and then smoothed by a post filter 5 and sent out from an output terminal 6 as an output of a burst waveform generator. Is done.

FIG. 8A shows an output waveform of the burst waveform generator when the ramp control is not performed.
When the ramp control is performed on this, the output waveform of the burst waveform generating device is transformed into a burst waveform in which the rising and falling changes are smooth as shown in FIG.

[0008]

However, since the conventional burst waveform generator uses a multiplier for the ramp control circuit, there is a problem that the power consumption is large and the circuit scale is large. .

In order to solve such a conventional problem, the present inventors have come up with the idea of realizing ramp control by bit-shifting digital data, and have proposed a burst waveform provided with a ramp control means by bit shift. The generator is proposed as Japanese Patent Application No. 5-104964.

In this device, the amplitude level of the digital waveform data during the rising and falling periods of the burst signal is changed. Therefore, the waveform data during this period is shifted by one bit. 3 bits, 2 bits, 1
In the order of bits, and conversely, at the time of falling, the bits are shifted in the order of 1 bit, 2 bits, and 3 bits. This device is
Since a multiplier is not required, lamp control can be performed with low power consumption and a small circuit scale.

When the 8-bit binary data is shifted by one bit by the ramp control means of the apparatus, the waveform data is reduced to half of the original value, and when the binary data is shifted by two bits, It is reduced to 1/2 ² . That is, in general, the binary data of the waveform data can be shifted by k bits and reduced to 1/2 ^{k of the} original value.

However, this device has a drawback that the width of the decrease in the waveform data cannot be changed to other than 1/2 ^k , and the ramp characteristics during the rising and falling periods cannot be set finely.

The present invention has been made in order to improve such a point, and provides a burst waveform generator which can perform ramp control with small power consumption and a small circuit scale and can arbitrarily set its ramp characteristics. It is intended to provide.

[0014]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a burst waveform generator for performing a ramp control on digital data to form a burst waveform, wherein one burst of digital data is sampled for n times (where n is a positive integer). )
Bit shifting means for performing bit shifting of digital data by changing the number of shifts for each of the n divided times;
The bit shift means is provided with a calculating means for sequentially calculating the output value for each time divided by n, and an output means for taking out the value calculated by the calculating means as an output for each sample time.

Further, the calculating means includes an adding means, and the adding means is configured to accumulate and add the output values of the bit shift means.

The arithmetic means includes a subtraction means, and the subtraction means is configured to subtract the previous operation result of the subtraction means from the output value of the bit shift means.

Further, the calculating means includes an adding / subtracting means,
The addition / subtraction means is configured to add or subtract the previous operation result of the addition / subtraction means from the output value of the bit shift means.

[0018]

Therefore, a plurality of bit shifts are performed by time division during one sample of the waveform data, and successive addition or subtraction or addition and subtraction is performed on the time-shifted bit shift output for each time. Is performed, and the calculation result is output every sample time. The amplitude of the output waveform data is M / 2 ^{K of the} original amplitude.
It is a multiple (M, K; a positive integer). By changing the number of bit shifts for each time-division time, the multiple can be arbitrarily adjusted and the lamp characteristics can be set smoothly.

[0019]

【Example】

(First Embodiment) A burst waveform generator according to an embodiment of the present invention outputs an input terminal 1 to which transmission data is applied and digital waveform data corresponding to the transmission data, as shown in FIG. A waveform data generation circuit 2 and a ramp control circuit 3 for performing a lamp control by changing the amplitude level by performing a bit shift on the output of the waveform data generation circuit 2
And a D / A converter 4 for converting digital data output from the lamp control circuit 3 into an analog sampled value signal.
And a post-filter 5 for smoothing the output waveform of the D / A converter 4.

As shown in FIG. 1, the ramp control circuit 3 time-divides one sample time of the output data of the waveform data generation circuit 2 into n (n: a positive integer). A bit shift circuit 31 that performs bit shift on the output data of the waveform data generation circuit 2 while changing the bit shift value to change the amplitude level, and outputs the output of the bit shift circuit and a first D-FF (D-flip An adder 32 for adding the output of the flop) unit 34 and a reset circuit 33 for resetting the output of the adder 32 every sample time
A first D-FF unit 34 for taking out the output of the reset circuit 33 every time the n is divided, and a second D-FF unit for taking out the output of the first D-FF unit every one sample time. D-FF
And a unit 35.

This device operates as follows. When digital data to be transmitted is applied to the input terminal 1, the waveform data generation circuit 2 outputs digital waveform data corresponding to the transmission data, and the ramp control circuit 3 responds to this output as follows. Is subjected to lamp control data processing.

FIG. 5 shows a timing chart of data processing in the lamp control circuit 3. In FIG. 5, the output data of the waveform data generation circuit 2 is DATA (i)
(I: positive integer), one sample time of DATA (i) is T
_The time-divided _S and T _S are divided into n pieces by T _B , and the output of the bit shift circuit 31 for performing the bit shift on DATA (i) by changing the bit shift value for each T _B is represented by B ₁ , B ₂ , ‥,
B _n , and the output of the lamp control circuit 3 is DATA ′ (i)
It is represented by Therefore, the lamp control circuit 3 converts the input DATA (i) into DATA '(i) and outputs the data.

The clock cycle for the first D-FF section 34 is T _B , and the clock cycle for the second D-FF section 35 is T _B
S , the period of the reset circuit signal is T _S, and these are given at the timing shown in FIG. When the reset circuit signal is H, the output of the reset circuit 33 is forcibly set to 0, and when it is L, the output of the adder 32 is output as it is.

The bit shift circuit 31, the digital waveform data DATA (i), shifts the T _S only K ₁ bit at the first time divided into n. This shift, the waveform data is converted into the pre-shift 1/2 ^K1 times the value, output from the bit shift circuit 31 as B _1.

The next adder 32, but adds the outputs B ₁ and the first D-FF 34 of the bit shift circuit 31, the output of the first first D-FF 34 is 0 Because there is an adder
The output of 32 is B _1. Thereafter, the signal B ₁ passes through the reset circuit 33 and is sent to the first D-FF section 34 by the first D-F section.
It is taken in synchronization with the rising of the clock for the F section. First
D-FF 34 of the holds between the value of the B ₁ of T _B.

Next, the bit shift circuit 31 outputs the waveform data D
The ATA (i), in the first second of time that the T _S divided into n, shifted by K ₂ bits, and outputs a 1/2 ^K2 times the value of the waveform data as the output B ₂ bit shift circuit 31. The next adder 32 adds the output B ₁ of the output B ₂ to the first D-FF 34 of the bit shift circuit 31, and outputs the addition value B ₁ + B _2.

The signal B ₁ + B ₂ then passes through the reset circuit 33 and is taken into the first D-FF section 34 in synchronization with the rise of the first D-FF section clock. D-
The FF unit 34 holds the value of the output B ₁ + B ₂ for T _B.

These operations are repeated, and the bit shift circuit 31 shifts the waveform data DATA (i) by K _n-1 bits at the ( _n-1 ) -th time obtained by dividing T _S by n, thereby dividing the waveform data by 1 / _n. The value of 2 ^Kn-1 times is output as _Bn-1 , and the next adder 32 outputs the output _Bn-1 of the bit shift circuit 31 and the first Dn.
−Addition of the output B ₁ + B ₂ + ‥ + B _{n−2 of the} FF unit 34 and B
₁ + B ₂ + ‥ + B _n-1 is output. This output B ₁ + B ₂ + ‥
After that, + B _n-1 passes through the reset circuit 33 and is taken into the first D-FF unit 34 in synchronization with the rising of the first D-FF unit clock. The unit 34 holds this output value for T _B.

On the other hand, the second D-FF unit 34 outputs the output value B ₁ + B ₂ + of the _first D-FF unit 34 at this time in synchronization with the rising of the second D-FF unit clock. ‥ + B _n−1 is fetched, and this is held for T _S as DATA ′ (i) = B ₁ + B ₂ + ‥ + B _n-1 .

Therefore, the ramp control circuit 3 outputs DATA ′ (i) = B ₁ + B ₂ + ‥ + B _n−1 to the D / A converter 4. This DATA ′ (i) converts DATA (i) to (1
^{/ 2 K1 +1/2 K2 + ‥ +} 1/2 Kn-1) is a value obtained by multiplying,
Since the value of 1/2 ^K1 +1/2 ^K2 + ‥ + 1/2 ^Kn-1 can be generally expressed as M / 2 ^K (M, K; positive integer), the lamp control circuit 3 This means that the data is output with the amplitude controlled to M / ^2K times.

The reset circuit 33 includes a second D-FF
After DATA ′ (i) is taken into the unit 35, the addition result so far is reset in synchronization with the reset circuit signal,
Prepare for the next operation. Also, the bit shift circuit at this time
The output _Bn of 31 has no relation to the operation.

As an example, n = 4, K ₁ = 2, K ₂ =
3, when K ₃ = 4, the amplitude of the waveform data input to the lamp control circuit 3 is controlled to 7/16 times.

The lamp control circuit 3 performs such control,
In the ramp time (the rising and falling periods of the burst signal), the number of bit shifts K ₁ , K ₂ , ‥, Kn _-1
Is executed several times while changing. Thereby, the amplitude level of the waveform data at the ramp time rises or falls stepwise.

The output of the ramp control circuit 3 is converted into an analog sample value signal by a D / A converter 4, then smoothed by a post filter 5, and output from an output terminal 6 as an output of a burst waveform generator. .

FIG. 6 (a) shows the output waveform of the burst waveform generator when no ramp control is performed, and FIG.
The output waveform shown in (b) is obtained.

As described above, in the burst waveform device of the first embodiment, in order to obtain the ramp characteristic, instead of multiplying the window function by using the multiplier, the waveform data is time-divided a plurality of times during one sample. Bit shifting is performed, and the results are sequentially added to change the amplitude level at the ramp time. Therefore, a multiplier becomes unnecessary, power consumption and circuit scale can be reduced, and a change in amplitude level during a ramp time can be arbitrarily set, so that a smooth ramp characteristic can be obtained.

(Second Embodiment) As shown in FIG. 3, the burst waveform generator of the second embodiment is a subtractor 36 for subtracting the output of the first D-FF section 34 from the output of the bit shift circuit 31.
Is provided. Other configurations are the same as those of the first embodiment (FIGS. 1 and 2).

In this device, the bit shift circuit 31 outputs
_At the first time when _S is divided by n, the digital waveform data DA
TA (i) is shifted by K ₁ bit, before shift 1 /
When the waveform data converted to a value of 2 ^K1 times is output as B ₁ , the first D-FF unit 34 is output as in the case of the first embodiment.
But, taking in the B _1.

Next, the bit shift circuit 31 sets the digital waveform data DATA at the second time obtained by dividing T _S by n.
(i) is shifted by K ₂ bits, before shifting 1/2 ^K2
And outputs the waveform data converted to double values as B _2,
The subtractor 36 outputs the first signal from the output B ₂ of the bit shift circuit 31.
Of subtracts the output B ₁ of the D-FF 34, the subtraction value B ₂ -
And outputs the B _1. This output B ₂ -B ₁ is output to the reset circuit 33.
After passing through, incorporated into the first D-FF 34 in synchronization with the rise for the first D-FF section clock is held between the T _B.

The above-described sequential subtraction is repeated, and the bit shift circuit 31 obtains the (n-1) -th time obtained by dividing T _S by n.
When the waveform data DATA (i) is shifted by K _n−1 bits and a value that is 1/2 ^Kn−1 times the waveform data is output as B _n−1 , the subtractor 36 outputs the output B _{n of the} bit shift circuit 31 ₋₁ to the output B _n−2 − (B _n−3 − (B _n−4 −) of the first D-FF unit 34
(‥ − (B ₂ −B ₁ ))), and subtracts B _n−1 − (B _n−2 − (B _n−3 − (B _n−4 − (‥ − (B ₂ −
B ₁ )))) is output. This output is output to reset circuit 3
3 and is taken into the first D-FF section 34 in synchronization with the rising of the first D-FF section clock, and
The FF unit 34 holds this output value for T _B.

On the other hand, at this time, the second D-FF unit 34 synchronizes with the rising edge of the second D-FF unit clock and outputs the output value B _n−1 − of the first D-FF unit 34. (B _n−2 − (B _n−3 −
(B _n−4 − (‥ − (B ₂ −B ₁ ))))) is taken, and the data is taken as DATA ′ (i) = B _n−1 − (B _n−2 − (B _n−3 − (B
_n− 4− (‥ − (B ₂ −B ₁ ))))) and is held for T _S.

Therefore, the ramp control circuit 3 supplies the D / A converter 4 with DATA ′ (i) = B _n−1 − (B _n−2 − (B
_n−3− (B _n−4 − (‥ − (B ₂ −B ₁ ))))) is output. This DATA ′ (i) is obtained by converting DATA (i) to (1/2).
^Kn-1 -1/2 ^Kn-2 +1/2 ^Kn-3- ‥ -1 / 2 ^K1 ) times this value, and this 1/2 ^Kn-1 -1/2 ^Kn-2 +1/2 ^Kn-3 −
Since the value of ‥ -２ ^K1 can be generally expressed as M / 2 ^K (M, K; positive integer), the ramp control circuit 3 controls the amplitude of the waveform data to M / 2 ^K times. Output.

As an example, n = 4, K ₁ = 4, K ₂ =
2. When K ₃ = 0 is set, the amplitude of the waveform data input to the lamp control circuit 3 is controlled to 13/16 times.

The lamp control circuit 3 performs such control,
In the ramp time, the number of bit shifts K ₁ , K ₂ , ‥,
The execution is performed a plurality of times while changing K _n−1 , thereby increasing or decreasing the amplitude level of the waveform data at the ramp time in a stepwise manner.

In the device of the second embodiment, the amount of change in the amplitude level in this step can be set smaller than in the device of the first embodiment.

(Third Embodiment) The burst waveform generator of the third embodiment adds or subtracts the output of the bit shift circuit 31 and the output of the first D-FF unit 34, as shown in FIG. An adder / subtractor 37 is provided. Other configurations are the same as those of the first embodiment (FIGS. 1 and 2).

This adder / subtractor 37 is operated according to a preset setting.
The output of the bit shift circuit 31 and the output of the first D-FF unit 34 are added for a certain time for each of the n divided times,
For a certain time, the output of the first D-FF unit 34 is subtracted from the output of the bit shift circuit 31.

In this device, in the sequential calculation, the bit shift circuit 31 shifts the waveform data DATA (i) by K _n−1 bits at the ( _n−1 ) -th time obtained by dividing T _S by n, and shifts the waveform data by ₁ bit. When the value of / 2 ^Kn−1 times is output as B _n−1 , the adder / subtracter 37 outputs the output B _n−1 of the bit shift circuit 31 and the output B _n−2 ± (B _n-3 ± (B _n-4 ±
(‥ ± (B ₂ ± B ₁ )))) and B _n-1
± (B _n-2 ± (B _n-3 ± (B _n-4 ± (‥ ± (B ₂ ±
B ₁ )))) is output.

The second D-FF section 35 outputs this output to the DAT in synchronization with the rising of the second D-FF section clock.
A ′ (i) = B _n−1 ± (B _n−2 ± (B _n−3 ± (B _n−4 ± (‥ ±
(B ₂ ± B ₁ ))))) and hold for T _S.

Therefore, the ramp control circuit 3 supplies the D / A converter 4 with DATA '(i) = B _n-1 ± (B _n-2 ± (B
_{n-3 ± (B n-} 4 ± (‥ ± (B 2 ± B 1))))) and outputs the. This DATA ′ (i) is obtained by converting DATA (i) to (1/2).
^{Kn-1 ± 1/2 Kn} -2 ± 1/2 Kn-3 ± ‥ ± 1/2 K1) is multiplied by the value, the ^{1/2 Kn-1 ± 1/2} Kn-2 ± 1/2 Kn ^-3 ±
Since the value of ‥ ± 1/2 ^K1 can be generally expressed as M / 2 ^K (M, K; positive integer), the lamp control circuit 3
This means that the waveform data is output with the amplitude controlled to M / ^2K times.

As an example, n = 4, K ₁ = 4, K ₂ = 2,
If K ₃ = 0 and the addition and subtraction circuit 37 is set to perform addition for the first and second calculations and subtraction for the third calculation, the waveform data input to the lamp control circuit 3 is 11 The amplitude is controlled to / 16 times.

The lamp control circuit 3 performs such control as follows:
In the ramp time, the number of bit shifts K ₁ , K ₂ , ‥,
The execution is performed a plurality of times while changing the order of Kn _-1 or the addition and subtraction, whereby the amplitude level of the waveform data at the ramp time is stepped up or down.

In the device according to the third embodiment, the amplitude level in this step can be varied in various ways.

In each embodiment, the number of steps of the change in the amplitude level during the ramp time may be one.

[0055]

As is apparent from the above description of the embodiment, the burst waveform generator of the present invention performs the ramp control without using the multiplier, so that the power consumption and the circuit scale are reduced. can do.

Further, the ramp characteristics at the rise and fall of the burst can be arbitrarily set, and a smooth change in the amplitude level can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a ramp control circuit used in a burst waveform generator according to a first embodiment of the present invention;

FIG. 2 is a block diagram showing the overall configuration of a burst waveform generator according to the first embodiment;

FIG. 3 is a block diagram of a ramp control circuit used in a burst waveform generator according to a second embodiment;

FIG. 4 is a block diagram of a ramp control circuit used in a burst waveform generator according to a third embodiment;

FIG. 5 is a timing chart of data processing in the lamp control circuit of each embodiment;

FIG. 6 shows an output (a) when the ramp control is not performed and an output (b) when the ramp control is performed in the burst waveform generator of the embodiment;

FIG. 7 is a block diagram showing a configuration of a conventional burst waveform generator.

FIG. 8 shows an output (a) when ramp control is not performed, a waveform diagram (b) of a window function, and an output (c) when ramp control is performed in the conventional burst waveform generator.

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 waveform data generation circuit 3, 7 ramp control circuit 31 bit shift circuit 32 adder 33 reset circuit 34 first D-FF section 35 second D-FF section 36 subtractor 37 adder / subtracter 4 D / A Converter 5 Post filter 6 Output terminal 71 Window function generator 72 Multiplier

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kazuhiro Umezu 4-3-1 Tsunashima Higashi, Kohoku-ku, Yokohama City, Kanagawa Prefecture Inside Matsushita Communication Industrial Co., Ltd. (56) References JP-A-6-296183 (JP, A) JP-A-7-58784 (JP, A) JP-A-3-213029 (JP, A) JP-A-2-207620 (JP, A) JP-A-2-20911 (JP, A) A Method of Lamp Control ”, Proc. Of the 1993 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers, p. 321 (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38 H03B 28/00

Claims (4)

(57) [Claims] 1. A burst waveform generator for performing a ramp control on digital data to form a burst waveform, wherein one sample time of the digital data is time-divided into n (n: positive integer), and the n-division is performed. Bit shifting means for performing a bit shift of the digital data by changing the number of shifts for each of the calculated times, calculating means for sequentially calculating the output value of the bit shifting means for each time divided into n, and the calculating means Output means for taking out a value calculated by the means as an output every sample time. 2. The burst waveform generator according to claim 1, wherein said arithmetic means includes an adding means, and said adding means accumulates and adds the output values of said bit shift means. 3. The arithmetic unit according to claim 1, wherein the arithmetic unit includes a subtraction unit, and the subtraction unit subtracts a previous operation result of the subtraction unit from an output value of the bit shift unit. Burst waveform generator. 4. The arithmetic means comprises an addition / subtraction means,
2. The burst waveform generator according to claim 1, wherein the addition / subtraction unit adds or subtracts a previous operation result of the addition / subtraction unit from an output value of the bit shift unit.