KR20000072995A - Stack type semiconductor chip package and manufacturing method thereof - Google Patents

Stack type semiconductor chip package and manufacturing method thereof Download PDF

Info

Publication number
KR20000072995A
KR20000072995A KR1019990015997A KR19990015997A KR20000072995A KR 20000072995 A KR20000072995 A KR 20000072995A KR 1019990015997 A KR1019990015997 A KR 1019990015997A KR 19990015997 A KR19990015997 A KR 19990015997A KR 20000072995 A KR20000072995 A KR 20000072995A
Authority
KR
South Korea
Prior art keywords
semiconductor chip
external connection
pads
semiconductor chips
pad
Prior art date
Application number
KR1019990015997A
Other languages
Korean (ko)
Inventor
조민교
Original Assignee
윤종용
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1019990015997A priority Critical patent/KR20000072995A/en
Publication of KR20000072995A publication Critical patent/KR20000072995A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A method for manufacturing a stack type semiconductor chip package is to provide a slim type semiconductor chip package by using a widthwise stack, and to maximize a mounting density by a chip-to-chip direct bonding method. CONSTITUTION: Bonding pads(43a,43b) and external connection pads(41a,41b) are arranged in a symmetrical type in semiconductor chips, which is a mirror type semiconductor chip package. The bonding pads(43a,43b) are directly bonded to the mirror type semiconductor chips, and the mirror type semiconductor chips are disposed at the outside of the semiconductor chip to which the external connection pads are adhered. Either one of an upper or lower semiconductor chip is electrically connected to an external connection pad of another semiconductor chip in a different layer adjacent to the semiconductor chip, which form a stack of two layer.

Description

적층형 반도체 칩 패키지와 그 제조 방법{Stack type semiconductor chip package and manufacturing method thereof}Stack type semiconductor chip package and manufacturing method

본 발명은 반도체 장치에 관한 것으로서, 더욱 상세하게는 복수의 반도체 칩을 적층하여 구성되는 형태로서 박형화에 적합한 구조를 갖는 적층형 반도체 칩 패키지와 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a stacked semiconductor chip package having a structure suitable for thinning as a form formed by stacking a plurality of semiconductor chips and a method of manufacturing the same.

반도체 소자와 그에 대한 패키지 기술은 상호 부합되어 고밀도화, 고속도화, 소형화 및 박형화를 목표로 계속적인 발전을 거듭해 왔다. 패키지 구조에 있어서 핀 삽입형에서 표면실장형으로 급격히 진행되어 회로기판에 대한 실장밀도를 높여 왔으며, 최근에는 베어 칩(bare chip)의 특성을 그대로 패키지 상태에서 유지하면서도 취급이 용이하고 패키지 크기도 줄이는 칩 크기 패키지(CSP; Chip Scale Package)라는 반도체 장치에 대한 활발한 연구가 진행되고 있다. 또한, 용량과 실장밀도의 증가를 위하여 여러 개의 단위 반도체 소자 또는 단위 반도체 칩 패키지를 적층시킨 형태의 3차원 적층 기술도 주목을 받게 되었다. 그 중에서 3차원 적층 기술을 이용하는 적층 칩 패키지를 소개하기로 한다.Semiconductor devices and their packaging technologies have been matched to each other and have continued to develop with the goal of increasing density, high speed, miniaturization and thinning. The package structure has been rapidly progressed from the pin insertion type to the surface mount type, thereby increasing the mounting density of the circuit board. Recently, the chip is easy to handle and reduces the package size while maintaining the bare chip characteristics in the package state. Active research is being conducted on semiconductor devices called chip scale packages (CSPs). In addition, three-dimensional stacking technology in which a plurality of unit semiconductor devices or unit semiconductor chip packages are stacked in order to increase capacity and mounting density has also attracted attention. Among them, a multilayer chip package using a 3D stacking technology will be introduced.

3차원 적층 기술을 이용하는 적층형 반도체 칩 패키지는 패키지되지 않은 반도체 소자를 여러 개 적층시키거나, 개별적으로 조립공정이 완료된 단위 반도체 칩 패키지를 여러 개 적층하여 구성된다. 동일한 기억용량의 반도체 칩 또는 반도체 칩 패키지를 3차원적으로 다수 개 적층한 반도체 칩 패키지에 대한 일 실시예가 도 1에 도시되어 있다.The stacked semiconductor chip package using the 3D stacking technology is formed by stacking a plurality of unpacked semiconductor devices or by stacking a plurality of unit semiconductor chip packages in which an assembly process is completed. An embodiment of a semiconductor chip package having a plurality of three-dimensionally stacked semiconductor chips or semiconductor chip packages having the same storage capacity is shown in FIG. 1.

도 1은 종래 기술에 따른 적층형 반도체 칩 패키지의 일 실시예를 나타낸 단면도이다.1 is a cross-sectional view showing an embodiment of a stacked semiconductor chip package according to the prior art.

도 1을 참조하면, 이 적층형 반도체 칩 패키지(100)는 일반적인 리드프레임의 다이패드(121) 상에 반도체 칩(111)이 실장되고, 그 반도체 칩(111)의 본딩패드(도시안됨)와 내부리드(122)가 도전성 금속선(131)으로 와이어 본딩(wire bonding)되어 전기적 접속을 이루며, 반도체 칩(111)을 포함하여 전기적인 접합부위가 외부 환경요소로부터의 보호를 위하여 에폭시 성형 수지(EMC; Epoxy Molding Compound)와 같은 봉지 수지로 패키지 몸체(141)가 형성된 반도체 칩 패키지(110)를 일개소 단위로 하여 적어도 2개 이상 수직으로 적층하여 이루어지는 구조이다. 이때, 각 단위 반도체 칩 패키지(110)들의 외부리드(123)가 전기적으로 연결된다.Referring to FIG. 1, in the stacked semiconductor chip package 100, a semiconductor chip 111 is mounted on a die pad 121 of a general lead frame, and a bonding pad (not shown) and an inside of the semiconductor chip 111 are mounted. The lead 122 is wire bonded to the conductive metal wire 131 to form an electrical connection, and the electrical bonding portion including the semiconductor chip 111 is epoxy-molded resin (EMC) for protection from external environmental elements. The semiconductor chip package 110 in which the package body 141 is formed of an encapsulation resin such as epoxy molding compound) is formed by vertically stacking at least two or more units. In this case, the external leads 123 of the unit semiconductor chip packages 110 are electrically connected to each other.

이와 같은 적층형 반도체 칩 패키지는 적층된 반도체 칩 패키지의 수가 증가할수록 패키지 전체 두께가 증가하여 박형화가 용이하지 않다. 각 단위 반도체 칩 패키지들이 반도체 칩과 리드간의 전기적 연결이 와이어 본딩에 이루어지고 봉지 수지에 의해 패키징(packaging)이 이루어지기 때문에 기본적으로 각 단위 반도체 칩 패키지들을 구성하기 위해 필요한 기본적인 두께가 필요하기 때문이다. 이는 단위 반도체 칩 패키지를 적층하여 구성되는 경우뿐만 아니라 반도체 칩을 적층하여서 구성되는 경우도 마찬가지이다.In such a stacked semiconductor chip package, as the number of stacked semiconductor chip packages increases, the overall thickness of the package increases, thereby making it difficult to reduce the thickness. This is because each unit semiconductor chip package basically requires the basic thickness necessary to configure each unit semiconductor chip package since electrical connection between the semiconductor chip and the lead is made by wire bonding and packaging is performed by the encapsulation resin. . This applies not only to the case where the unit semiconductor chip packages are stacked but also to the case where the semiconductor chips are stacked.

또한, 이러한 적층형 반도체 칩 패키지는 반도체 칩의 크기가 커지면 패키지 크기를 증가시키지 않고서는 패키지의 신뢰성 확보가 매우 어려워지기 때문에 적층면적도 증가하게 되어 경박단소화가 어렵다.In addition, as the stacked semiconductor chip package increases in size, it becomes very difficult to secure reliability of the package without increasing the package size.

한편, 제조 공정에 있어서 종래의 적층형 반도체 칩 패키지에서는 기존의 조립 공정을 그대로 적용할 수는 있지만, 이 단위 반도체 칩 패키지를 적층할 때에는 기존 조립 공정과 다른 별도의 공정이 요구된다.In the manufacturing process, the conventional assembly type semiconductor chip package can be applied to an existing assembly process as it is. However, when the unit semiconductor chip package is laminated, a separate process different from the existing assembly process is required.

이상과 같이 종래의 적층형 반도체 칩 패키지들이 갖는 문제점들 때문에, 패키지의 크기를 증가시키지 않으면서도 기존의 적층형 반도체 칩 패키지가 가지고 있는 여러 장점들을 제공해 주는 적층형 반도체 칩 패키지의 개발에 대한 필요성이 대두되고 있다.As described above, due to the problems of the conventional stacked semiconductor chip packages, there is a need for the development of a stacked semiconductor chip package that provides various advantages of the conventional stacked semiconductor chip package without increasing the size of the package. .

본 발명의 목적은 기존의 적층형 반도체 칩 패키지보다 경박단소화가 가능하고 그 제조 공정이 단순하고 용이하여 제조단가 측면에서도 유리한 구조를 갖는 적층형 반도체 칩 패키지와 그 제조 방법을 제공하는 데에 있다.An object of the present invention is to provide a laminated semiconductor chip package and a method for manufacturing the same, which have a structure that is advantageous in terms of manufacturing cost because the manufacturing process is simpler and easier than the conventional laminated semiconductor chip package.

도 1은 종래 기술에 따른 적층형 반도체 칩 패키지의 일 실시예를 나타낸 단면도.1 is a cross-sectional view showing an embodiment of a stacked semiconductor chip package according to the prior art.

도 2a 내지 도 2c는 본 발명에 따른 적층형 반도체 칩 패키지의 미러형 반도체 칩을 얻기 위한 제조 공정 진행에 따른 반도체 칩들의 상태를 나타낸 평면도.2A to 2C are plan views illustrating states of semiconductor chips as a manufacturing process proceeds to obtain mirrored semiconductor chips of a stacked semiconductor chip package according to the present invention.

도 3a 내지 도 3e는 본 발명에 따른 적층형 반도체 칩 패키지의 제조 공정 중에서 재배선 과정을 나타낸 공정도.3A to 3E are flowcharts illustrating a rewiring process in a manufacturing process of the stacked semiconductor chip package according to the present invention.

도 4a내지 도 4c는 결합된 미러형의 반도체 칩들을 적층하여 기판에 실장한 상태를 나타낸 단면도.4A to 4C are cross-sectional views illustrating a state in which bonded mirror semiconductor chips are stacked and mounted on a substrate.

도 5는 본 발명에 따른 적층형 반도체 칩 패키지의 다른 실시예를 나타낸 단면도.Figure 5 is a cross-sectional view showing another embodiment of a stacked semiconductor chip package according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100; 적층형 반도체 칩 패키지 11,11a,11b; 반도체 칩100; Stacked semiconductor chip packages 11, 11a, 11b; Semiconductor chip

13a,13b; 전극패드 15; 패시베이션막13a, 13b; Electrode pads 15; Passivation film

21; 제 1비전도층 23; 제 2비전도층21; A first non-conductive layer 23; 2nd non-conductive layer

25; 제 3비전도층 31; 제 1금속배선25; Third nonconductive layer 31; First metal wiring

32a,32b; 입출력 단자 33; 제 2금속배선32a, 32b; Input / output terminal 33; Second metal wiring

41,41a,41b; 외부 접속패드 43,43a,43b; 접합패드41,41a, 41b; External connection pads 43,43a and 43b; Bonding pad

51a,51b; 빔 리드(beam lead) 60; 주회로기판51a, 51b; Beam lead 60; Main circuit board

이와 같은 목적을 달성하기 위한 본 발명에 따른 적층형 반도체 칩 패키지는 전극패드와 금속배선으로 연결되어 형성되어 재배치된 접합패드와 그 접합패드가 형성된 면의 가장자리 일측부에 위치하도록 형성된 외부 접속패드를 갖는 반도체 칩들이 2층으로 적층되어 구성된다. 여기서, 상층의 반도체 칩과 하층의 반도체 칩은 접합패드와 외부 접속단자가 서로 대칭성을 갖는 미러형(mirror type) 반도체 칩이다.The stacked semiconductor chip package according to the present invention for achieving the above object has a bonding pad which is formed and rearranged by being connected to the electrode pad and the metal wiring and an external connection pad formed to be located at one side edge of the surface on which the bonding pad is formed. The semiconductor chips are stacked in two layers. Here, the upper semiconductor chip and the lower semiconductor chip are mirror type semiconductor chips in which the bonding pads and the external connection terminals have symmetry.

그리고, 상층의 반도체 칩의 외부 접속패드가 그 반도체 칩의 접합패드가 부착된 하층 반도체 칩의 외측에 위치하고, 하층의 반도체 칩의 외부 접속패드가 그 반도체 칩의 접합패드가 부착된 상층 반도체 칩의 외측에 위치하도록 하여 상층의 반도체 칩과 하층의 반도체 칩이 동일한 단자에 해당하는 접합패드가 직접 접합되어 적층되어 있다. 상층의 반도체 칩들과 하층의 반도체 칩들 중에서 어느 한층의 반도체 칩들이 그와 이웃하는 다른 층의 반도체 칩과 외부 접속패드가 접합되어 전기적으로 연결되며, 가장 바깥쪽에 위치한 반도체 칩들의 외부 접속패드들이 외부 실장 수단과 전기적 연결수단에 의해 접합된다.The external connection pads of the upper semiconductor chip are located outside the lower semiconductor chip to which the bonding pads of the semiconductor chip are attached, and the external connection pads of the lower semiconductor chip are of the upper semiconductor chip to which the bonding pads of the semiconductor chip are attached. Bonding pads corresponding to the same terminal are stacked by directly bonding the semiconductor chip in the upper layer and the semiconductor chip in the lower layer so as to be located outside. Among the semiconductor chips of the upper and lower semiconductor chips, one of the semiconductor chips is electrically connected by connecting the semiconductor chip of the other layer adjacent to it and the external connection pads, and the external connection pads of the outermost semiconductor chips are externally mounted. By means of electrical connection.

또한, 본 발명에 따른 적층형 반도체 칩 패키지 제조 방법은, ⒜ 전극패드를 갖는 동일한 반도체 칩들을 각각의 반도체 칩이 전극패드와 금속배선으로 연결되도록하여 재배치된 접합패드를 형성하고 그 접합패드가 형성된 면의 가장자리 일측부에 위치하도록 외부 접속패드를 형성하며, 이때 반도체 칩들간에 접합패드와 외부 접속패드가 대칭형으로 배치시키는 미러형 반도체 칩 제조 단계와, ⒝ 그 미러형의 반도체 칩들을 접합패드가 직접 접합되도록 하고, 외부 접속패드가 부착되는 반도체 칩의 외측에 위치하도록 하고 상층과 하층 중 어느 하나의 반도체 칩이 그와 이웃하는 다른 층의 반도체 칩의 외부 접속패드와 전기적으로 연결되도록 하여 2층으로 적층시키는 칩 본딩 단계를 포함하는 것을 특징으로 한다.In addition, the method for manufacturing a stacked semiconductor chip package according to the present invention comprises: (i) the same semiconductor chips having electrode pads so that each semiconductor chip is connected to the electrode pads by metal wiring to form a rearranged bonding pad and a surface on which the bonding pad is formed; Forming an external connection pad so as to be positioned at one side of the edge of the semiconductor chip, wherein a step of manufacturing a mirror-type semiconductor chip in which the bonding pads and the external connection pads are symmetrically disposed between the semiconductor chips is performed; To be bonded to each other, and positioned outside the semiconductor chip to which the external connection pad is attached, and the semiconductor chip of either the upper layer or the lower layer is electrically connected to the external connection pad of the semiconductor chip of the other layer adjacent thereto. It characterized in that it comprises a chip bonding step of laminating.

이하 첨부 도면을 참조하여 본 발명에 따른 적층형 반도체 칩 패키지와 그 제조 방법을 상세하게 설명하기로 한다.Hereinafter, a multilayer semiconductor chip package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

먼저, 동일한 반도체 칩들을 전극패드가 대칭되어 배치되도록 재배선하여 전극패드와 전기적으로 연결된 접합패드와 외부 접속단자를 가장자리 일측부에 배치되도록 하는 미러형 반도체 칩 제조 단계를 진행한다.First, the same semiconductor chips are rearranged so that the electrode pads are symmetrically disposed, and thus the mirror type semiconductor chip manufacturing step of arranging the bonding pad and the external connection terminal electrically connected to the electrode pads is disposed at one side of the edge.

도 2a 내지 도 2c는 본 발명에 따른 적층형 반도체 칩 패키지의 미러형 반도체 칩을 얻기 위한 제조 공정 진행에 따른 반도체 칩들의 상태를 나타낸 평면도이다.2A to 2C are plan views illustrating states of semiconductor chips according to a manufacturing process of obtaining a mirrored semiconductor chip of a stacked semiconductor chip package according to the present invention.

본 발명에 따른 적층 칩 패키지를 얻기 위해서는 먼저 미러형 반도체 칩의 제조가 필요하다. 일반적인 웨이퍼 제조 공정(fabrication)을 거쳐 제조되는 반도체 칩들(11a,11b)은 도 2a에 도시된 것과 같이 동일한 위치에 전극패드(13a,13b)가 배치되어 있는 구조를 갖고 있다. 이와 같은 반도체 칩들(11a,11b)은 재배선 공정을 거쳐 1차적으로 도 2b에 도시된 것과 같이 전극패드(13a,13b)로부터 제 1금속배선(31a,31b)으로 연결되어 입출력 단자를 각 반도체 칩(11a,11b)의 상면 전체에 분포되도록 한다. 이때, 두 반도체 칩들(11a,11b)의 입출력 단자(32a,32b)가 서로 대칭적으로 배치되도록 한다.In order to obtain the stacked chip package according to the present invention, first, manufacturing of a mirror type semiconductor chip is required. The semiconductor chips 11a and 11b manufactured through a general wafer fabrication process have a structure in which electrode pads 13a and 13b are disposed at the same position as illustrated in FIG. 2A. The semiconductor chips 11a and 11b are first connected to the first metal wirings 31a and 31b from the electrode pads 13a and 13b through the redistribution process, as shown in FIG. It distributes to the whole upper surface of the chip | tip 11a, 11b. At this time, the input and output terminals 32a and 32b of the two semiconductor chips 11a and 11b are arranged to be symmetrical to each other.

이렇게 구성된 반도체 칩들(11a,11b)은 다시 재배선 공정을 거쳐 도 2c에 도시된 것과 같이 각각의 반도체 칩(11a,11b) 상면에서 상기 입출력 단자(32a,32b)의 상부에 접합패드(43a,43b)를 형성하고, 그 접합패드(43a,43b)와 제 2금속배선(33a, 33b)으로 접합되어 전기적인 연결을 이루도록 하여 가장자리 일측부에 길이방향으로 열을 이루도록 외부 접속패드(41a,41b)를 형성하면 두 반도체 칩들(11a,11b)은 서로 대칭적인 접합패드 배열을 갖는 반도체 칩들이 된다. 즉, 왼쪽에 도시된 반도체 칩(11a)과 오른쪽에 도시된 반도체 칩(11b)은 서로 포개질 때 서로 동일한 기능을 하는 접합패드(32a,32b)가 상호 접촉되도록 대칭적으로 형성되어 있는 미러형의 반도체 칩이 된다. 각각의 반도체 칩(11a,11b)은 다음과 같은 세부적인 공정에 의해서 제조될 수 있다.The semiconductor chips 11a and 11b configured as described above are subjected to the redistribution process again, and as shown in FIG. 2C, the bonding pads 43a and the upper portion of the input / output terminals 32a and 32b are disposed on the upper surfaces of the semiconductor chips 11a and 11b, respectively. 43b), and are connected to the bonding pads 43a and 43b and the second metal wires 33a and 33b to form an electrical connection so that the external connection pads 41a and 41b are formed in the longitudinal direction at one edge thereof. ), The two semiconductor chips 11a and 11b are semiconductor chips having a symmetrical bonding pad array. That is, the semiconductor chip 11a shown on the left side and the semiconductor chip 11b shown on the right side are mirror-type which are symmetrically formed so that the bonding pads 32a and 32b which have the same function when they overlap each other are mutually contacted. To become a semiconductor chip. Each of the semiconductor chips 11a and 11b may be manufactured by the following detailed process.

도 3a 내지 도 3e는 본 발명에 따른 적층형 반도체 칩 패키지의 제조 공정 중에서 재배선 과정을 나타낸 공정도이다.3A to 3E are flowcharts illustrating a rewiring process in a manufacturing process of the stacked semiconductor chip package according to the present invention.

일반적인 웨이퍼 제조 공정을 거쳐 제조되는 반도체 칩(11)은 도 3a에 도시된 것과 같이 전극패드(13)의 상면부가 개방되도록 하여 패시베이션막(15)이 형성되어 있는 구조이다.The semiconductor chip 11 manufactured through a general wafer manufacturing process has a structure in which a passivation film 15 is formed by opening the upper surface of the electrode pad 13 as shown in FIG. 3A.

이 반도체 칩 상태에서 도 3b에서와 같이 제 1비전도층(dielectric layer; 21)을 형성한 후 에칭(etching)을 통하여 전극패드(13)를 개방시키고, 개방된 전극패드(13)와 전기적으로 연결되는 제 1금속배선(31)과 그로부터 이격되도록 하여 입출력 단자(32)를 그 비전도층(21)의 상면에 형성한다. 이때, 제 1금속배선(31)은 전극패드(13)와 연결되고, 입출력 단자(32)는 반도체 칩(11)의 가장자리 일측에 일렬로 배치된다.In this semiconductor chip state, as shown in FIG. 3B, after forming the first dielectric layer 21, the electrode pad 13 is opened by etching and electrically connected to the opened electrode pad 13. The input / output terminal 32 is formed on the upper surface of the non-conductive layer 21 by being spaced apart from the first metal wiring 31 to be connected. In this case, the first metal wiring 31 is connected to the electrode pad 13, and the input / output terminals 32 are arranged in one line at one edge of the semiconductor chip 11.

제 1금속배선(31)과 입출력 단자(32)를 형성한 후에 도 3c와 같이 제 1금속배선(31)과 입출력 단자(32)를 덮도록 하여 제 2비전도층(23)을 형성하고, 제 1금속배선(31)의 소정 부분과 입출력 단자의 상부를 개방시킨 후, 제 1금속배선(31)과 입출력 단자(32)를 연결하는 제 2금속배선(33)을 형성한다. 이에 따라, 입출력 단자(32)는 전극패드(13)와 전기적으로 연결된다.After the first metal wiring 31 and the input / output terminal 32 are formed, the second non-conductive layer 23 is formed by covering the first metal wiring 31 and the input / output terminal 32 as shown in FIG. 3C. After opening a predetermined portion of the first metal wiring 31 and the upper portion of the input / output terminal, a second metal wiring 33 connecting the first metal wiring 31 and the input / output terminal 32 is formed. Accordingly, the input / output terminal 32 is electrically connected to the electrode pad 13.

제 2금속배선(33)을 형성한 후에 도 3d와 같이 다시 제 2금속배선(33)을 덮도록 하여 제 3비전도층(25)을 형성하여 외부로부터의 물리적 또는 화학적 손상으로부터 보호하고, 다시 입출력 단자(32)의 상부와 소정 부분의 제 1금속배선(31) 상부에 해당하는 제 2금속배선(33)의 상부를 개방시킨다.After the second metal wiring 33 is formed, the third non-conductive layer 25 is formed by covering the second metal wiring 33 again as shown in FIG. 3D to protect it from physical or chemical damage from the outside, and again. The upper portion of the second metal interconnection 33 corresponding to the upper portion of the input / output terminal 32 and the upper portion of the first metal interconnection 31 of the predetermined portion is opened.

제 2금속배선(33)을 형성한 후에 도 3e와 같이 개방된 부분에 범프를 형성하여 외부 접속패드(41)와 접합패드(43)를 형성한다. 이때, 범프 재료는 구리(Cu), 니켈(Ni), 솔더(solder) 등 여러 금속이 사용될 수 있으며, 재배선에 사용되는 금속으로 티타늄(Ti), 크롬(Cr), 구리(Cu) 등을 이용하여 구성할 수 있다.After the second metal wiring 33 is formed, bumps are formed in an open portion as shown in FIG. 3E to form an external connection pad 41 and a bonding pad 43. In this case, the bump material may be a metal such as copper (Cu), nickel (Ni), solder (solder), and the metal used for redistribution, such as titanium (Ti), chromium (Cr), copper (Cu), etc. It can be configured using.

이상과 같은 재배선 과정으로 전극패드가 같은 위치에 있는 동일 반도체 칩들이 서로 대칭되는 위치에 전극패드와 전기적으로 연결된 접합패드가 형성된 미러형의 반도체 칩이 제조된다. 이와 같은 미러형의 반도체 칩을 얻기 위한 재배선 과정은 동일한 웨이퍼 상에서 이루어질 수도 있고, 각각의 웨이퍼에 독립적으로 이루어질 수도 있다.Through the redistribution process as described above, a mirror-type semiconductor chip having a junction pad electrically connected to the electrode pad is formed at a position where the same semiconductor chips having the same electrode pads are symmetrical with each other. The redistribution process for obtaining such a mirror-shaped semiconductor chip may be performed on the same wafer or may be performed independently of each wafer.

도 4a내지 도 4c는 결합된 미러형의 반도체 칩들을 적층하여 기판에 실장한 상태를 나타낸 단면도이다.4A to 4C are cross-sectional views illustrating a state in which bonded mirror semiconductor chips are stacked and mounted on a substrate.

도 4a를 참조하면, 재배선 과정으로 미러형의 반도체 칩들(11a,11b)이 제조되면 이들을 서로 부착하는 칩 본딩 단계를 진행한다. 상층에 위치한 반도체 칩(11b)과 하층에 위치한 반도체 칩(11a)을 외부 접속패드(41a,41b)가 다른 층에 위치한 반도체 칩의 외측에 위치하도록 하여 각각의 반도체 칩들(11a,11b)에 형성된 접합패드(43a,43b)를 상호 접합하여 부착한다. 접합된 접합패드(43a,43b)는 상층의 반도체 칩(11b)과 하층의 반도체 칩(11a)의 동일한 입출력 신호의 경로가 된다.Referring to FIG. 4A, when mirror-shaped semiconductor chips 11a and 11b are manufactured by a redistribution process, a chip bonding step of attaching them to each other is performed. The semiconductor chip 11b on the upper layer and the semiconductor chip 11a on the lower layer are formed on the semiconductor chips 11a and 11b so that the external connection pads 41a and 41b are positioned outside the semiconductor chip on the other layer. Bonding pads 43a and 43b are bonded to each other and attached. The bonded pads 43a and 43b serve as the paths of the same input / output signals between the upper semiconductor chip 11b and the lower semiconductor chip 11a.

여기서, 상층 반도체 칩(11b)과 주회로기판(60)은 은 에폭시와 같이 일반적으로 반도체 칩을 기판에 부착시킬 때 사용하는 접착제에 의해 이루어진다. 그리고, 상층 반도체 칩(11b)과 하층 반도체 칩(11a)의 접합패드(43a,43b)의 접합 방법은 도 4a에서와 같이 열압착(Thermosetting)에 의해 접합패드(43a,43b)를 직접 접합시키는 방법, 도 4b에 도시된 것과 같이 각 반도체 칩(11a,11b)의 접합패드(43a,43b)에 각각 솔더(45)를 형성하고 리플로우(reflow)를 거쳐 접합시키는 솔더 리플로우(solder reflow) 방법이나, 도 4c에 도시된 것과 같이 상층 반도체 칩(11b)과 하층 반도체 칩(11a)의 사이에 이방성 전도 필름(ACF; Anisotropic Contact Film;46)을 개재하여 접합시키는 방법 등 여러 가지 방법을 사용할 수 있다.Here, the upper semiconductor chip 11b and the main circuit board 60 are made of an adhesive which is generally used to attach a semiconductor chip to a substrate, such as silver epoxy. In the bonding method of the bonding pads 43a and 43b of the upper semiconductor chip 11b and the lower semiconductor chip 11a, the bonding pads 43a and 43b are directly bonded by thermosetting as shown in FIG. 4A. A method of solder reflow in which a solder 45 is formed on each of the bonding pads 43a and 43b of each semiconductor chip 11a and 11b and bonded through a reflow, as shown in FIG. 4B. As shown in FIG. 4C, various methods, such as a method of bonding an anisotropic contact film (ACF) 46 between the upper semiconductor chip 11b and the lower semiconductor chip 11a, may be used. Can be.

그리고, 상층 반도체 칩(11b)과 하층 반도체 칩(11a)의 외부 접속패드(41a, 41b)는 빔 리드(51a,51b)를 이용하는 탭(TAB; Tape Atomated Bonding) 방법에 의해 주회로기판(60)에 전기적으로 연결된다. 이때, 탭 방법외에 소켓(socket) 방법 등 여러 가지 방법이 적용될 수 있다. 그리고, 주회로기판(60)은 적층된 반도체 칩들을 고정시키기 위한 것으로 일반적인 회로기판이나 모듈(module)을 적용할 수 있다. 여기서, 빔 리드(51a,51b)는 같은 기능을 하는 접합패드(43a,43b)들에 연결되어 있으므로 어느 한 쪽만 연결하여도 구동이 가능하며 적층시에는 연결패드로 사용한다.In addition, the external connection pads 41a and 41b of the upper semiconductor chip 11b and the lower semiconductor chip 11a are connected to the main circuit board 60 by a tape Atomated Bonding (TAB) method using the beam leads 51a and 51b. Is electrically connected). In this case, various methods such as a socket method may be applied in addition to the tap method. In addition, the main circuit board 60 is for fixing the stacked semiconductor chips, and a general circuit board or module may be applied. Here, the beam leads 51a and 51b are connected to the bonding pads 43a and 43b having the same function, and thus, the beam leads 51a and 51b can be driven by connecting only one of them.

이와 같이 반도체 칩이 적층된 형태의 반도체 칩 패키지를 구성함에 있어서 패키지 신뢰성 향상을 위하여 적층된 반도체 칩 사이의 공간을 에폭시 성형 수지와 같은 봉지재로 언더필(underfill)시켜 줄 수 있다.As described above, in forming a semiconductor chip package in which semiconductor chips are stacked, the space between the stacked semiconductor chips may be underfilled with an encapsulant such as an epoxy molding resin in order to improve package reliability.

이상의 실시예에서 설명한 본 발명에 따른 적층형 반도체 칩 패키지는 동일한 반도체 칩의 입출력 단자가 동일한 위치에 있기 때문에 재배선 작업을 통해 입출력 단자의 위치를 대칭이 되도록 형성하고 있기 때문에 가능하다. 즉, 전극패드의 재배선 작업을 통해 얻어진 미러형의 반도체 칩을 대칭의 칩 전면을 서로 맞붙게 하는 것이 가능해진다.The stacked semiconductor chip package according to the present invention described in the above embodiments is possible because the positions of the input / output terminals are symmetrical through the redistribution operation because the input / output terminals of the same semiconductor chip are located at the same position. That is, the mirror-shaped semiconductor chip obtained through the rewiring operation of the electrode pads can be brought into contact with the symmetrical chip fronts.

또한, 이상과 같은 제조 방법에 의해 제조되는 적층형 반도체 칩 패키지는 반도체 칩들이 적층될 때 상층의 반도체 칩과 하층의 반도체 칩이 대응되는 접합패드가 상호 접합되어 적층되고, 상층 반도체 칩과 하층 반도체 칩이 어긋난 형태로 접합되어 부착되는 반도체 칩의 외측에 외부 접속패드가 위치하도록 구성되기 때문에 경박단소화에 유리하고, 전기적 경로가 짧아 고속 소자의 실장에도 유리하다. 그리고, 제조 공정에 있어서 종래의 단위 반도체 칩 패키지를 적층할 때 필요한 공정들이 필요가 없고, 기존의 반도체 칩을 적층하기 위한 공정을 그대로 이용할 수 있다.In addition, in the stacked semiconductor chip package manufactured by the above manufacturing method, when the semiconductor chips are stacked, the bonding pads corresponding to the upper semiconductor chip and the lower semiconductor chip are laminated to each other, and the upper and lower semiconductor chips are stacked. Since the external connection pad is positioned outside the semiconductor chip to be bonded and attached in this misaligned form, it is advantageous in light and short and short, and the electrical path is short, which is advantageous in mounting high-speed devices. In the manufacturing process, the processes required for stacking the conventional unit semiconductor chip package are not required, and the process for stacking the conventional semiconductor chip can be used as it is.

한편, 본 발명에 따른 적층형 반도체 칩 패키지와 그 제조 방법은 위에 소개한 실시예에 한정되지 않고 본 발명의 기술적 중심사상을 벗어나지 않는 범위 내에서 다양한 형태로 변형실시가 가능하다. 예를 들어, 2개 이상의 반도체 칩들로 구성되는 적층형 반도체 칩 패키지를 소개하기로 한다.Meanwhile, the stacked semiconductor chip package and the method of manufacturing the same according to the present invention are not limited to the above-described embodiments, and may be modified in various forms without departing from the technical spirit of the present invention. For example, a stacked semiconductor chip package including two or more semiconductor chips will be introduced.

도 5는 본 발명에 따른 적층형 반도체 칩 패키지의 다른 실시예를 나타낸 단면도이다.5 is a cross-sectional view showing another embodiment of a stacked semiconductor chip package according to the present invention.

도 5를 참조하면, 복수의 단위 반도체 칩들(71)이 수평 방향으로 2층의 구조를 이루며 어긋난 형태로 적층된 구조를 가지고 있다. 상층의 반도체 칩(71b)들과 하층의 반도체 칩(71a)들은 직접 접합패드(43a,43b)가 접합되어 적층되어 있기 때문에 패키지 박형화에 유리하다. 그리고, 상위의 반도체 칩(71b)들이 하위의 반도체 칩(71a)들보다 오른쪽으로 이동된 형태로 부착되어 외부 접속패드(41a)가 이웃하는 다른 층의 외부 접속패드(41b)와 접합되어 전기적으로 연결되며, 가장 외측에 위치하는 반도체 칩들(72a,72b)의 외부 접속단자(41c,41d)는 빔 리드(51a,51b)로 접합되어 주회로기판(60)에 실장되어 있어서 더욱 박형화에 유리하다.Referring to FIG. 5, a plurality of unit semiconductor chips 71 form a two-layer structure in a horizontal direction and have a stacked structure in a displaced form. The upper semiconductor chips 71b and the lower semiconductor chips 71a are advantageous in package thinning because the direct bonding pads 43a and 43b are bonded and stacked. The upper semiconductor chips 71b are attached to the right side of the lower semiconductor chips 71a so that the external connection pads 41a are joined to the external connection pads 41b of another layer adjacent to each other. The external connection terminals 41c and 41d of the semiconductor chips 72a and 72b, which are located at the outermost side, are joined to the beam leads 51a and 51b and mounted on the main circuit board 60, which is advantageous for further thinning. .

이상과 같은 본 발명에 따른 적층형 반도체 칩 패키지와 그 제조 방법에 따르면, 높이 방향이 아닌 넓이 방향으로의 적층이라 박형(slim)화가 용이하며, 칩 대 칩의 직접 본딩 방식이라 패키지의 실장면적을 최소화하여 실장밀도를 극대화시켜줄 뿐만 아니라 전기적 경로가 기존 적층형 반도체 칩 패키지에 비해 짧기 대문에 고속 소자의 실장에도 유리하며, 반도체 칩의 적층시 기존 공정을 사용할 수 있어 제조 단가면에서 유리하다.According to the stacked semiconductor chip package and the method of manufacturing the same according to the present invention as described above, stacking is performed in the width direction rather than the height direction, thereby making it slimmer, and minimizing the mounting area of the package due to the direct bonding method of the chip to the chip. In addition to maximizing the mounting density, the electrical path is shorter than that of the conventional multilayer semiconductor chip package, which is advantageous for mounting high-speed devices.

Claims (4)

전극패드에 금속배선으로 연결되어 형성되어 재배치된 접합단자와 상기 접합단자가 형성된 면의 가장자리 외측에 위치하도록 형성된 외부 접속패드를 갖는 반도체 칩들이 2층으로 적층되어 구성되는 적층형 반도체 칩 패키지로서,A stacked semiconductor chip package comprising two layers of semiconductor chips having a junction terminal formed by being connected to an electrode pad and rearranged by a metal wiring and an external connection pad formed outside the edge of a surface on which the junction terminal is formed. 상층의 반도체 칩과 하층의 반도체 칩은 상기 접합패드와 상기 외부 접속패드가 서로 대칭성을 갖는 미러형 반도체 칩이며,The upper semiconductor chip and the lower semiconductor chip are mirror type semiconductor chips in which the bonding pad and the external connection pad are symmetrical with each other. 상기 상층의 반도체 칩의 외부 접속패드가 그 반도체 칩의 접합패드가 부착된 하층 반도체 칩의 외측에 위치하고, 상기 하층의 반도체 칩의 외부 접속패드가 그 반도체 칩의 접합패드가 부착된 상층 반도체 칩의 외측에 위치하도록 하여, 상기 상층의 반도체 칩과 하층의 반도체 칩이 동일한 단자에 해당하는 접합패드가 직접 상호 접합되어 적층되어 있고,The external connection pad of the upper semiconductor chip is located outside the lower semiconductor chip to which the bonding pad of the semiconductor chip is attached, and the external connection pad of the lower semiconductor chip is of the upper semiconductor chip to which the bonding pad of the semiconductor chip is attached. Bonding pads corresponding to the same terminal of the upper semiconductor chip and the lower semiconductor chip are directly bonded to each other and stacked so as to be located outside, 상기 상층의 반도체 칩들과 하층의 반도체 칩들중에서 어느 한 층의 반도체 칩들이 그와 이웃하는 다른 층의 반도체 칩의 외부 접속패드와 접합되어 전기적으로 연결되며,Among the semiconductor chips of the upper layer and the semiconductor chip of the lower layer, any one of the semiconductor chips is bonded and electrically connected to the external connection pads of the semiconductor chips of the other layer adjacent thereto, 가장 바깥쪽에 위치한 반도체 칩들의 외부 접속패드들이 외부 실장 수단과 전기적 연결 수단에 의해 접합되는 것을 특징으로 하는 적층형 반도체 칩 패키지.A stack type semiconductor chip package, wherein external connection pads of the outermost semiconductor chips are bonded by an external mounting means and an electrical connection means. 제 1항에 있어서, 상기 상층 반도체 칩과 하층 반도체 칩들은 각각 하나씩인 것을 특징으로 하는 적층형 반도체 칩 패키지.The multilayer semiconductor chip package of claim 1, wherein each of the upper and lower semiconductor chips is one. ⒜ 전극패드를 갖는 동일한 반도체 칩들을 각각의 반도체 칩이 전극패드와 금속배선으로 연결되도록하여 재배치된 접합패드를 형성하고 그 접합패드가 형성된 면의 가장자리 일측부에 위치하도록 외부 접속패드를 형성하며, 이때 반도체 칩들간에 접합패드와 외부 접속패드가 대칭형으로 배치시키는 미러형 반도체 칩 제조 단계와, ⒝ 그 미러형의 반도체 칩들을 접합패드가 직접 접합되도록 하고, 외부 접속패드가 부착되는 반도체 칩의 외측에 위치하도록 하고 상층과 하층 중 어느 하나의 반도체 칩이 그와 이웃하는 다른 층의 반도체 칩의 외부 접속패드와 전기적으로 연결되도록 하여 2층으로 적층시키는 칩 본딩 단계를 포함하는 것을 특징으로 하는 적층형 반도체 칩 패키지 제조 방법.(B) forming the rearranged bonding pads by connecting the same semiconductor chips having the electrode pads to each of the semiconductor chips with the electrode pads and forming an external connection pad so as to be located at one side edge of the surface on which the bonding pads are formed; At this time, the manufacturing method of the mirror type semiconductor chip in which the bonding pads and the external connection pads are symmetrically arranged between the semiconductor chips, and the bonding pads are directly bonded to the mirror type semiconductor chips, and the outside of the semiconductor chip to which the external connection pads are attached. And a chip bonding step of stacking the semiconductor chip of any one of the upper layer and the lower layer so as to be electrically connected to the external connection pads of the semiconductor chip of the other layer adjacent thereto. Chip package manufacturing method. 제 3항에 있어서, 상기 미러형 반도체 칩 제조 단계는,The method of claim 3, wherein the mirror type semiconductor chip manufacturing step, (a-1) 전극패드의 소정 부분이 개방되도록 하여 패시베이션막이 형성되어 있는 동일한 반도체 칩에 비전도층을 상기 전극패드가 개방되도록 하여 상기 반도체 칩의 상면에 형성하는 단계;(a-1) forming a non-conductive layer on an upper surface of the semiconductor chip by opening a predetermined portion of the electrode pad to open the non-conductive layer on the same semiconductor chip on which a passivation film is formed; (a-2) 상기 전극패드와 전기적으로 연결되는 제 1금속배선과 그로부터 이격되도록 하여 반도체 칩의 가장자리 일측부에 입출력 단자를 형성하는 단계;(a-2) forming an input / output terminal on one side of an edge of the semiconductor chip by being spaced apart from the first metal wire electrically connected to the electrode pad; (a-3) 상기 제 1금속배선의 소정부분과 상기 입출력 단자가 개방되도록 하여 비전도층을 형성하고, 상기 제 1금속배선과 입출력 단자를 연결하는 제 2금속배선을 형성하는 단계;(a-3) forming a non-conductive layer by opening a predetermined portion of the first metal wiring and the input / output terminal, and forming a second metal wiring connecting the first metal wiring and the input / output terminal; (a-4) 상기 입출력 단자의 상부와 소정부분의 제 1금속배선 상부에 해당하는 제 2금속배선의 상부가 개방되도록 하여 비전도층을 형성하는 단계; 및(a-4) forming a non-conductive layer by opening an upper portion of the second metal interconnection corresponding to an upper portion of the input / output terminal and an upper portion of the first metal interconnection of a predetermined portion; And (a-5) 개방된 부분에 범프를 형성하여 외부 접속패드와 접합패드를 형성하는 단계;를 포함하는 것을 특징으로 하는 적층형 반도체 칩 패키지 제조 방법.(A-5) forming a bump in the open portion to form an external connection pad and a bonding pad.
KR1019990015997A 1999-05-04 1999-05-04 Stack type semiconductor chip package and manufacturing method thereof KR20000072995A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990015997A KR20000072995A (en) 1999-05-04 1999-05-04 Stack type semiconductor chip package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990015997A KR20000072995A (en) 1999-05-04 1999-05-04 Stack type semiconductor chip package and manufacturing method thereof

Publications (1)

Publication Number Publication Date
KR20000072995A true KR20000072995A (en) 2000-12-05

Family

ID=19583722

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990015997A KR20000072995A (en) 1999-05-04 1999-05-04 Stack type semiconductor chip package and manufacturing method thereof

Country Status (1)

Country Link
KR (1) KR20000072995A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101534680B1 (en) * 2009-02-23 2015-07-07 삼성전자주식회사 Stack type semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101534680B1 (en) * 2009-02-23 2015-07-07 삼성전자주식회사 Stack type semiconductor package

Similar Documents

Publication Publication Date Title
US6803254B2 (en) Wire bonding method for a semiconductor package
KR100626618B1 (en) Semiconductor chip stack package and related fabrication method
US6906415B2 (en) Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US8120186B2 (en) Integrated circuit and method
KR101653856B1 (en) Semiconductor device and manufacturing method thereof
US7679178B2 (en) Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof
US20070096265A1 (en) Multiple die integrated circuit package
US8786083B2 (en) Impedance controlled packages with metal sheet or 2-layer RDL
JPH08213427A (en) Semiconductor chip and multi-chip semiconductor module
TWI599009B (en) Semiconductor chip package, semiconductor module, method of fabricating the semiconductor chip package and method of fabricating the semiconductor module
WO2012082177A1 (en) Enhanced stacked microelectronic assemblies with central contacts
KR20030000529A (en) Package device with a number of chips stacked and having central electrode pads and manufacturing method thereof
US9917073B2 (en) Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
US20030085463A1 (en) Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method fo formation and testing
US10354978B1 (en) Stacked package including exterior conductive element and a manufacturing method of the same
CN114823651A (en) Radio frequency system module packaging structure with filter and method
KR100673379B1 (en) Stack package and manufacturing method thereof
KR20000072995A (en) Stack type semiconductor chip package and manufacturing method thereof
KR20010073345A (en) Stack package
KR100437821B1 (en) semiconductor package and metod for fabricating the same
KR20050027384A (en) Chip size package having rerouting pad and stack thereof
KR101811738B1 (en) Enhanced stacked microelectric assemblies with central contacts
CN108831875B (en) Packaging structure with embedded filter chip and external electrode and manufacturing method thereof
KR100199287B1 (en) Chip scaled package using clip lead
KR200283421Y1 (en) Stacked chip ceramic package device and stacked package device stacking the same

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid