KR20000072323A - Digital Signal Processing Apparatus and it's Interfacing Method for Automatic Control - Google Patents

Abstract

PURPOSE: A digital signal processing apparatus for automatic control and an interface method thereof are provided, in which the digital signal processing apparatus can be easily interfaced with a host computer without changing of user application programs according to the bus type of the host computer. CONSTITUTION: A digital signal processing apparatus includes a bus controller(120) and a system controller(140). The bus controller interfaced with a host computer(100) to perform transmission of data or control command between the bus of the host computer and the inner system bus(160) of the digital signal processor based on the bus type of the host computer. The system controller processes a control signal from the digital signal processor to generate a control signal for controlling external input/output devices interfaced to an analog circuit processor and the digital signal processor.

Description

Digital Signal Processing Apparatus and Interface Method for Automatic Control {Digital Signal Processing Apparatus and it's Interfacing Method for Automatic Control}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device for automatic control and an interface method thereof. The present invention relates to a digital signal processing processor (DSP) for digitally processing a signal input from an external input device and outputting a control signal to an external output device. The present invention relates to a digital signal processing apparatus for control and a method thereof.

Background Art Conventionally, a control board incorporating a digital signal processing processor (DSP) has been widely used as a control system for controlling an output device including an actuator such as a motor in real time based on information input from various sensors.

In addition, in order to process a large amount of digital data such as audio and image data, a control board having a digital signal processing processor (DSP) must be used.

The digital signal processing device for automatic control is widely adopted because it can be adapted to various application fields by changing the software, and the system can be easily changed or monitored by the interface with the host computer. It is becoming.

In addition, the digital signal processing device for automatic control has recently been maximized in accordance with the development of processor technology for digital signal processing, and the access speed is increased according to the development of memory technology. The trend is getting wider.

However, the existing digital signal processing apparatus for automatic control is designed differently depending on the application field or the bus type of the host computer. In other words, according to the characteristics of the analog signal input and output, additional hardware had to be provided separately or the overall design change had to be made, and the digital signal processing apparatus for automatic control used according to the bus type of the host computer had to be separately configured.

Accordingly, since the firmware or user application controlling the same has to be separately designed or changed according to the characteristics of the input / output analog signal and the bus type of the host computer, there is a problem that excessive design cost or time is required.

The present invention further embodies the bus control unit and the control unit of the invention, which is proposed in the patent application No. 2000-25441 (May 12, 2000), which is a prior application of the applicant, and is provided through an input / output slot of a host computer. In the control area that is not easy to interface, serial and parallel port controllers are added to easily support the interface without changing the design of the user application program.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an automatic control digital signal processing apparatus and an interface method thereof that can interface with a bus type of a host computer.

In addition, another object of the present invention is a digital signal processing apparatus for automatic control that can easily support the interface without changing the design of the user application in the control field that is not easy to interface through the input and output slots (I / O Slot) of the host computer And an interface method thereof.

1 is a block diagram showing the overall configuration of the apparatus of the present invention;

FIG. 2 is a block diagram illustrating a configuration of a bus controller in FIG. 1. FIG.

3 is a block diagram illustrating a configuration of a system controller of FIG. 1;

4 is a block diagram showing the configuration of the serial and parallel port control unit of FIG.

5 is a flowchart illustrating an operation of a bus control unit according to the present invention.

6A is a flowchart for serially transmitting data transmitted from a host computer by serial and parallel port controllers to a digital signal processing apparatus.

Figure 6b is a flow chart for serial transmission of data transmitted from the digital signal processing apparatus by the serial and parallel port control unit to the host computer

7A is a flow chart for parallel transmission of data transmitted from a host computer by serial and parallel port controllers to a digital signal processing apparatus.

7B is a flowchart for parallel transmission of data transmitted from a digital signal processing apparatus by a serial and parallel port controller to a host computer.

FIG. 8 is a list of control signals in FIG.

9 is a list of control signals in FIG.

FIG. 10 is a list of control signals in FIGS. 6A to 7B.

<Description of the symbols for the main parts of the drawings>

100: host computer 110: host computer bus

120: bus control unit 121: bus latch unit

122: host bus decoder unit 123: system bus decoder unit

124: interrupt generator 130: DSP CPU

140: system control unit 141: clock generation unit

142: analog controller 143: system interrupt signal generator

144: system decoder unit 150: analog circuit processing unit

160: internal system bus of the digital signal processing device

170: serial and parallel port control unit 171: port control unit

172: serial port control unit 173: parallel port control unit

As a solution for achieving the above object, the present invention is interfaced to a host computer (Interface), the internal system of the host computer bus and the digital signal processing apparatus according to the bus type (Bus Type) of the host computer A bus controller for transmitting data or control commands between system buses; A bus type of a host computer by including a system controller for processing a control signal from a digital signal processor (DSP) and outputting a control signal for controlling an external input / output device interfaced to the analog circuit processor and the digital signal processor. Its feature is that it can be interfaced independently of it.

In addition, as an additional aspect of the present invention, a port control unit which receives a control signal from the internal system bus of the digital signal processing device, initializes a serial port and a parallel port, and detects an operation state thereof, and transmits and receives data through the serial port. The host computer and interface are further included by including a serial port controller for controlling the operation of the serial port, and a parallel port controller for controlling the operation of the parallel port to transmit and receive data through the parallel port. It is characterized in that it can be run without changing the design of the user application in the field that is not easy.

Hereinafter, with reference to the accompanying drawings will be described in detail to enable those skilled in the art to understand and easily implement the configuration and operation of the present invention.

Figure 1 is a block diagram showing the overall configuration of the apparatus of the present invention, the present invention is interfaced to a host computer 100 having a host computer bus 110 of ISA or PCI type, the type of the host computer bus 110 ( A bus controller 120 for transmitting data or control commands between the host computer bus and the internal system bus of the digital signal processing apparatus according to the bus type; DSP which controls the whole device, transmits the processed data to the host computer 100 by the bus control unit 120, and controls to receive the data processed by the host computer 100 through the bus control unit 120. CPU 130; A system controller which processes a control signal from a digital signal processor (DSP) and outputs a control signal for controlling an external input / output device (not shown) interfaced to the analog circuit processor 150 and the digital signal processor ( 140); An analog circuit processor 150 for receiving an analog signal input from an external input device (not shown), converting the digitally processed signal into an analog signal, and outputting the analog signal to an external output device (not shown); It is configured to include a serial and parallel port control unit 170 to drive without changing the design of the user application in the field where the interface with the host computer 100 is not easy

FIG. 2 is a block diagram showing the configuration of the bus controller of FIG. 1. The bus controller 120 of the present invention interfaces with the host computer bus 110 and transmits data or commands transmitted from the host computer 100 to the digital signal processing apparatus. A bus latch 121 for transmitting data transmitted from the internal system bus 160 of the digital signal processing apparatus or the data transmitted from the internal system bus 160 of the digital signal processor to the host computer 100; The bus latch unit may receive a control signal from the computer 100 and transmit data or commands transmitted from the host computer 100 to the internal system bus 160 of the digital signal processing apparatus according to the bus type of the host computer 100. A host bus decoder 122 for generating a predetermined control signal for controlling 121; and a host computer receiving a control signal from the digital signal processing apparatus. A system for generating a predetermined control signal for controlling the bus latch unit 121 to transmit data transmitted from the internal system bus 160 of the digital signal processing apparatus to the host computer 100 according to the bus type of 100. Interrupt signal for executing this command by receiving a system bus decoder 123 and a series of command bits for controlling the digital signal processing apparatus from the host computer 100 It comprises a interrupt generator 124 for generating a.

FIG. 5 is a flowchart illustrating an operation of the bus control unit according to the present invention, and FIG. 8 is a list of control signals in FIG. 5. The operation steps and flow of the bus control unit 120 will be described with reference to FIGS. 5 and 8.

The bus controller 120 detects a bus type signal of the host computer (S100), and when the bus type detected in the step S100 is a PCI bus, sets the bus type variable to '1'. Step S110a of setting the length of the host data bus to 32 bits after setting to &quot;, &quot; the bus type if the bus type detected in the step S100 is an ISA bus. A bus type determination routine for determining a bus type of the host computer including setting a variable to '0' and setting the length of the host data bus to 16 bits (S110b); Determining an operation state to be performed in the digital signal processing apparatus by detecting the command bit transmitted from the host computer (S200), and if the command bit detected in the step (S200) is '00' Digital signal processing apparatus Transmitting the command from the host computer to a bus latch unit (S210a) and storing the data necessary for the operation performed in the digital signal processing apparatus when the command bit detected in the step S200 is '01'. Transmitting the data from the host computer to a bus latch unit (S210b) and if the command bit detected in the step (S200) is '10', the digital signal processing apparatus transmits the completed data to the host computer. Instruction bits that comprise the step of transmitting from the digital signal processor for backup and storing in the bus latch unit (S210c) An analysis routine; Generating a system interrupt for processing a command and data stored in the digital signal processing device according to the command bit processed in the command bit interpreting routine (S300), and the interrupt variable generated in the step (S300) In case of '0', generating an instruction execution interrupt to execute the instruction stored in the step S210a in the digital signal processing apparatus, and then storing the instruction stored in the bus latch unit in a memory block of the digital signal processing apparatus (S310a). And, if the interrupt variable generated in the step (S300) is '1' and the bus after generating a data read interrupt (Data Read Interrupt) to perform the data stored in the step (S210b) in the digital signal processing device Storing the data stored in the latch unit in a memory block of the digital signal processing apparatus (S310b); If the interrupt variable generated in S300 is '2', the data write interrupt is generated after the data write interrupt is generated to transfer the data processed by the digital signal processing apparatus stored in the step S210c to the host computer. If the system bus busy flag is busy at step S310c and step S310a and step S310b, step S310a and step S310b are repeated. If the Idle state ends (S320a), and if the host bus busy flag is busy in step S310c, step S310c is repeated, and if the idle state is idle, It has a data processing routine comprising the step S320c of terminating.

That is, the bus controller 120 first determines the type of the bus type by detecting a bus signal in order to determine the bus type of the host computer.

If the detected bus type is a PCI bus, set the bus type variable #BUS_TYPE to '1' and set the length of the host data bus to 32 bits in the digital signal processor. If the detected bus type is an ISA bus, set the bus type variable #BUS_TYPE to '0' and set the length of the host data bus to 16 bits in the digital signal processor.

Thereafter, the command bit CMD_BIT transmitted from the host computer is detected to determine an operation state to be performed in the digital signal processing apparatus.

In this case, when the detected command bit CMD_BIT is '00', the command executed in the digital signal processing apparatus is transmitted from the host computer and stored in the bus latch unit. When the detected command bit CMD_BIT is '01', the digital signal processing is performed. Transfer the data necessary for the operation performed in the device from the host computer and store it in the bus latch unit.When the detected command bit CMD_BIT is '10', the digital signal processing device backs up the operation completed data to the host computer. The data is transmitted from the digital signal processor and stored in the bus latch unit.

After the instruction or data transmitted from the host computer is stored in the bus latch unit or the data processed by the digital signal processing unit is stored in the bus latch unit, the digital signal processing apparatus according to the command bit processed in the system bus decoder unit as described above. Generates a system interrupt SINTR to process commands and data stored in the system.

In this case, when the generated interrupt variable SINTR is '0', the instruction execution interrupt INSTR is generated to execute an instruction transmitted from the host computer latched in the bus latch unit in the digital signal processing apparatus, and then the instruction stored in the bus latch unit. Is stored in the memory block of the digital signal processing apparatus.

Meanwhile, when the generated interrupt variable SINTR is '1', a data read interrupt DATAR is generated in order to perform data transmitted from the host computer stored in the bus latch unit in the digital signal processing apparatus, and then the bus latch is executed. The data stored in the unit is stored in a memory block (not shown) of the digital signal processing apparatus.

If the above-mentioned interrupt variable SINTR is '0' or '1', the operation is repeated if the System Bus Busy Flag SBF is busy, and ends if it is idle. do.

On the other hand, when the generated interrupt variable SINTR is '2', a data write interrupt DATAW is generated to transfer the data processed by the digital signal processing apparatus stored in the bus latch unit to the host computer, and then the data is generated. Transfer to the host computer.

When the generated interrupt variable SINTR is '2', the operation is repeated when the host bus busy flag HBF is busy, and ends when the idle state is idle.

3 is a block diagram showing the configuration of the system control unit in FIG. 1, and FIG. 9 is a control signal list in FIG. 3, wherein the system control unit 140 of the present invention generates a clock frequency used in the digital signal processing apparatus of the present invention. A clock generator 141; An analog controller 142 for processing an analog signal input from an external input device (not shown); A system interrupt signal generator 143 for monitoring the operation of the clock generator 141 and the analog controller 142 and generating an interrupt signal for controlling the operation flow thereof; And a system decoder 144 for decoding input and output devices (not shown) used in the digital signal processing apparatus of the present invention.

Specifically, the clock generation unit 141 receives the clock CLKIN from the DSP CPU 130 of the digital signal processor and uses the serial port for determining the transmission speed of the serial data transmitted through the serial port. Generates a clock signal (COMCLK) and a clock signal (CLKOUT) used in the analog controller 142, and the analog-to-digital converter (not shown) and the digital-to-analog converter (not shown) of the analog circuit processing unit 150. Generate a clock to determine a conversion time and a sampling frequency of

The analog controller 142 receives a clock for the conversion time and the sampling frequency generated by the clock generator 141 and determines the conversion start time and the conversion end time of the analog-digital converter of the analog circuit processor 150. Then, the DSP CPU 130 in the digital signal processing apparatus receives the system address and outputs a selection signal for determining the channel of each converter.

The system interrupt signal generator 143 receives a conversion start and conversion end time and a user interrupt request signal USR_INT generated by the analog controller 142 and receives an interrupt request signal from the DSP CPU 130. Generates (SYS_INT).

The system decoder (Systen Decoder) unit 144 receives a system address of the digital signal processing apparatus and selects a system device to control a device device (not shown) interfaced to the digital signal processing apparatus. Generate the signal SYS_CS.

FIG. 4 is a block diagram showing the configuration of the serial and parallel port controllers of FIG. 1. The serial and parallel port controllers 170 of the present invention receive a control signal from an internal system bus 110 of the digital signal processing apparatus. A port control unit 171 for initializing the serial port and the parallel port and detecting an operation state thereof, a serial port control unit 172 for controlling the operation of the serial port to transmit and receive data through the serial port, and a parallel port through the parallel port. And a parallel port controller 173 for controlling the operation of the parallel port to transmit and receive data.

The operation of the serial and parallel port controllers will be described with reference to FIGS. 6A to 7B and 10.

FIG. 6A is a flowchart for serially transmitting data transmitted from a host computer by serial and parallel port controllers to a digital signal processing apparatus. In this case, the operation in this case includes a serial including a transmission speed, a transmission method, and the like. Initializing the state of the port (S500); When the host computer to be transmitted detects the COM_RDY control signal COM_RDY on the serial port and the COM_RDY signal is deactivated, that is, when the host computer is not ready to transmit data, the digital signal processing unit performs other tasks until the COM_RDY signal is activated. Performing or waiting (S510); Transmitting a serial data transmission activation control signal COM_STB to the host computer indicating that the port control unit 171 of the digital signal processing apparatus performs a transmission when the COM_RDY signal is activated (S520); The host computer detects the serial port compatibility decision control signal COM_INT to maintain the compatibility of the user application program. If this signal is disabled, the host computer outputs an error message indicating that the user application program cannot be executed. Clearing and then ending (S530); When the COM_INT signal is activated, it receives and processes the necessary data from the host computer until the end of the data to be received (until the serial data transmission end control signal SER_END is activated). Then, if the end of the data to be received is detected, that is, When the SER_END signal is activated, the control unit operates according to the step S540 of clearing and terminating all control signals.

FIG. 6B is a flowchart for serially transmitting data transmitted from the digital signal processing apparatus by the serial and parallel port controllers to the host computer. The operation in this case includes a serial including a transmission speed, a transmission method, and the like in the port controller 171. Initializing the state of the port (S600); Transmitting the serial data transmission activation control signal COM_STB to the host computer to perform transmission by the port controller 171 of the digital signal processing apparatus (S610); When the host computer to be transmitted detects the COM_RDY control signal COM_RDY on the serial port and the COM_RDY signal is deactivated, that is, when the host computer is not ready to transmit data, the digital signal processing unit performs other tasks until the COM_RDY signal is activated. Performing or waiting (S620); When the COM_RDY signal is enabled, the host computer detects the serial port compatibility decision control signal COM_INT to maintain the compatibility of the user application program, and outputs an error message that the user application cannot be executed when this signal is disabled. And terminating after clearing all control signals (Clear); When the COM_INT signal is activated, it receives and processes the necessary data from the host computer until the end of the data to be received (until the serial data transmission end control signal SER_END is activated), and when the end of the data to be received is detected, that is, When the SER_END signal is activated, the control unit operates according to the step S640 of clearing and terminating all control signals.

FIG. 7A is a flowchart in which data transmitted from a host computer by serial and parallel port controllers is transmitted in parallel to a digital signal processing apparatus. In this case, the operation of the port controller 171 includes parallel transmission speeds, transmission methods, and the like. Initializing the state of the port (S700); When the host computer to be transmitted detects the activation control signal CEN_ACK of the parallel port and the CEN_ACK signal is deactivated, that is, when the host computer is not ready to transmit data, the digital signal processing device performs other tasks until the CEN_ACK signal is activated. Performing or waiting (S710); When the CEN_ACK signal is activated, transmitting the parallel data transmission activation control signal CEN_STRB to the host computer indicating that the port control unit 171 of the digital signal processing apparatus performs transmission (S720); When the host computer detects the compatibility decision control signal CEN_ERR of the parallel port to maintain the compatibility of the user application program, it outputs an error message that the user application cannot be executed when this signal is deactivated, and outputs all control signals. Clearing and then ending (S730); When the CEN_ERR signal is activated, the received data is received and processed until the end of the data to be received by the host computer (until the parallel data transmission end control signal SEN_BF is activated), and when the end of the data to be received is detected, that is, When the SEN_BF signal is activated, the control unit operates according to the step S740 of clearing and terminating all control signals.

7B is a flowchart in which data transmitted from the digital signal processing apparatus by the serial and parallel port controllers are transmitted in parallel to the host computer. In this case, the operation of the port controller 171 includes the transmission speed, the transmission method, and the like. Initializing the state of the port (S800); Transmitting the parallel data transmission activation control signal CEN_STRB to the host computer indicating that the port controller 171 of the digital signal processing apparatus performs transmission (S810); When the COM_RDY signal is deactivated by detecting the activation control signal CEN_ACK of the parallel port at the host computer to be transmitted, that is, when the host computer is not ready to transmit data, the digital signal processing device performs other tasks until the CEN_ACK signal is activated. Performing or waiting (S820); When the CEN_ACK signal is activated, the host computer detects the parallel port compatibility decision control signal CEN_ERR to maintain the compatibility of the user application program, and outputs an error message that the user application cannot be executed when this signal is deactivated. And terminating after clearing all control signals (Clear); When the CEN_ERR signal is activated, the received data is received and processed until the end of the data to be received by the host computer (until the parallel data transmission end control signal SEN_BF is activated), and when the end of the data to be received is detected, that is, When the SEN_BF signal is activated, the control unit operates according to the step S840 of clearing and terminating all control signals.

Maintaining the compatibility of the user's application in the above means that the application, which is designed on the host computer and downloaded to the digital signal processing device interfaced with the ISA or PCI bus, is executed without modification through the serial port or the parallel port. It means you can download and run it.

Thus, by the above it can be achieved the object of the present invention presented in the present invention.

Effects obtained by the present invention having the configuration and operation relationship as described above can be interfaced regardless of the bus type of the host computer, and interface through the I / O slot of the host computer It has a very useful effect such as being able to easily support the interface without changing the design of the user application program in the difficult control field.

Claims (5)

In the digital signal processing device for automatic control incorporating a digital signal processing processor (DSP) for processing a signal input from an external input device through an analog circuit processing unit to output a control signal to an external output device, Interfaced to a host computer to transfer data or control commands between the host computer bus and the internal system bus of the digital signal processing device according to the bus type of the host computer. A bus controller; And a system controller for processing a control signal from a digital signal processor (DSP) and outputting a control signal for controlling an external input / output device interfaced to the analog circuit processing unit and the digital signal processing device. Digital signal processing device for automatic control. The method of claim 1, The bus control unit: Bus Latch (Bus), which interfaces with the host computer bus to transfer data or instructions from the host computer to the internal system bus of the digital signal processor, or to the host computer for data transmitted from the internal system bus of the digital signal processor. Latch), A host bus that receives a control signal from the host computer and generates a predetermined control signal for controlling the bus latch unit to transmit data or instructions transmitted from the host computer to the internal system bus of the digital signal processing apparatus according to the bus type of the host computer Decoder (Host Bus Decoder) section, A system bus that receives a control signal from the digital signal processing apparatus and generates a predetermined control signal for controlling the bus latch to transfer data transmitted from the internal system bus of the digital signal processing apparatus to the host computer according to the bus type of the host computer. Decoder (System Bus Decoder) section, And an interrupt generator for receiving a series of command bits for controlling the digital signal processing apparatus from the host computer and generating an interrupt signal for executing the command. Signal processing device. The method of claim 1, The system control unit: The clock signal (CLKOUT) used in the serial port and the clock signal used in the analog controller to determine the transfer rate of serial data transmitted through the serial port by receiving the clock (CLKIN) from the DSP CPU of the digital signal processor. A clock generator for generating a clock for determining a conversion time and sampling frequency of the analog-digital converter and the digital-analog converter of the analog circuit processor; The conversion start time and the conversion end time of the analog-to-digital converter of the analog circuit processing unit are determined by receiving the clock for the conversion time and the sampling frequency generated by the clock generation unit, and the system address is input from the DSP CPU in the digital signal processing device. An analog controller for receiving and outputting a selection signal for determining a channel of each converter; A system interrupt signal generator for receiving a conversion start and conversion end time and a user interrupt request signal USR_INT generated by the analog controller to generate an interrupt request signal SYS_INT from a DSP CPU; And a system decoder (Systen Decoder) for generating a system device selection signal SYS_CS to receive a system address of the digital signal processing device and to control a device device interfaced to the digital signal processing device. Digital signal processing device for automatic control, characterized in that. The method according to claim 1 or 2 or 3, A port controller which receives a control signal from an internal system bus of the digital signal processor and initializes a serial port and a parallel port and detects an operation state thereof; A serial port controller for controlling the operation of the serial port to transmit and receive data through the serial port; And a serial and parallel port control unit having a parallel port control unit for controlling the operation of the parallel port to transmit and receive data through the parallel port. Detecting a bus type signal of a host computer (S100); and setting the bus type variable to '1' when the bus type detected in the step S100 is a PCI bus. And setting the length of the host data bus to 32 bits (S110a), and setting the bus type variable to '0' when the bus type detected in the step S100 is an ISA bus. A bus type determination routine for determining the bus type of the host computer including setting (S110b) the length of the host data bus to 16 bits after setting; Determining an operation state to be performed in the digital signal processing apparatus by detecting the command bit transmitted from the host computer (S200), and if the command bit detected in the step (S200) is '00' Digital signal processing apparatus Transmitting the command from the host computer to a bus latch unit (S210a) and storing the data necessary for the operation performed in the digital signal processing apparatus when the command bit detected in the step S200 is '01'. Transmitting the data from the host computer to a bus latch unit (S210b) and if the command bit detected in the step (S200) is '10', the digital signal processing apparatus transmits the completed data to the host computer. Instruction bits that comprise the step of transmitting from the digital signal processor for backup and storing in the bus latch unit (S210c) An analysis routine; Generating a system interrupt for processing a command and data stored in the digital signal processing device according to the command bit processed in the command bit interpreting routine (S300), and the interrupt variable generated in the step (S300) In case of '0', generating an instruction execution interrupt to execute the instruction stored in the step S210a in the digital signal processing apparatus, and then storing the instruction stored in the bus latch unit in a memory block of the digital signal processing apparatus (S310a). And, if the interrupt variable generated in the step (S300) is '1' and the bus after generating a data read interrupt (Data Read Interrupt) to perform the data stored in the step (S210b) in the digital signal processing device Storing the data stored in the latch unit in a memory block of the digital signal processing apparatus (S310b); If the interrupt variable generated in S300 is '2', the data write interrupt is generated after the data write interrupt is generated to transfer the data processed by the digital signal processing apparatus stored in the step S210c to the host computer. If the system bus busy flag is busy at step S310c and step S310a and step S310b, step S310a and step S310b are repeated. If the Idle state ends (S320a), and if the host bus busy flag is busy in step S310c, step S310c is repeated, and if the idle state is idle, An interface method of an automatic control digital signal processing apparatus, comprising: a data processing routine including a terminating step (S320c).