JP2988879B2 - Bus converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus converter for transferring data between two devices having different bus interfaces.

[0002]

2. Description of the Related Art Conventionally, a floppy disk drive,
There are peripheral devices such as a hard disk drive and a CD-ROM drive. Many peripheral devices are connected to and used by a personal computer via a bus. Recently, there have been many standardized bus types, and ATA-2 (AT At
tachment-2) or SCSI (Small Computer System I
nterface) is widely used. Note that AT
The A-2 bus has IDE (Integrated Drive Electron)
ics) or ATAPI (AT Attachment Packet Interface)
e) Peripheral equipment equipped with the interface of the above can be connected and used.

[0003] When comparing the ATA-2 bus and the SCSI bus, there are the following differences. Two peripheral devices can be connected to one ATA-2 bus, and seven peripheral devices can be connected to one SCSI bus. Therefore, when connecting a plurality of peripheral devices to a personal computer, the SCSI interface is more suitable. The IDE interface has a simpler circuit because it has a specification closer to the PC system bus than the SCSI interface. For this reason, peripherals connected to the ATA-2 bus are less expensive. In the ATA-2 bus, the cable connecting peripheral devices is up to 46 cm, and in the SCSI bus, the total length of the cable is up to 6 m. Therefore, the SCSI interface is more suitable as an external peripheral device for a personal computer.

[0004]

From the above-described differences, when purchasing a peripheral device, the user considers the cost of purchasing the peripheral device and the use environment of the system to which the peripheral device is connected, and considers the ATA. In this case, the user has to select whether to connect a peripheral device with the -2 bus or a peripheral device with the SCSI bus. However, when a newly purchased peripheral device is additionally installed and the usage environment changes,
If you want to change the peripheral device connected to the TA-2 bus to be used by connecting to the SCSI bus,
There may be a case where a user wants to change the peripheral device connected to the I bus to the ATA-2 bus for use. However,
Such a connection change could not be made because the interfaces provided in the peripheral device were different.

[0005] Recently, peripheral devices for IDE interfaces, which are inexpensive, have become mainstream and have been mass-produced.
Costs are even lower. On the other hand, the number of peripheral devices of the SCSI interface is decreasing. For this reason, the price difference between the peripheral device of the IDE interface and the peripheral device of the SCSI interface is further increased. Therefore, recently, there has been an increasing demand for a bus converter that enables peripheral devices having an IDE interface to be used by connecting them to a SCSI bus.

However, the bus converters proposed so far temporarily take in all the transfer data from a device (the data transfer side) connected to one of the buses, and then transfer the stored data to the other. However, there is a problem that the time required for data transfer is long.

An object of the present invention is to provide a bus converter capable of inputting and outputting data between devices connected to buses of different standards at high speed.

[0008]

Means for Solving the Problems] bus converting apparatus of the present invention, the two interfaces are connected to two buses with different standards, One of the above two buses
Between the input and output buses
And input and output bus switching means for performing, the input and output bus switching means
FIF transfer data but input from bus that the input side
And data writing means for writing the O, and data output means for outputting transfer data written in the FIFO to the bus to the output bus switching means has an output side, at startup,
For a device connected via the bus, the device
Is the slowest specified in the standard of the bus to which it is connected
A transfer rate acquiring means for acquiring the data transfer rate of the upper limit to which the device supports and access speed, the transfer
Transfer the upper limit data transfer speed acquired by the speed acquisition means to the bus
Set as the access speed for the connected device
Access speed setting means. One side
A command converting means for converting the input from the bus command compatible command to the other bus standards, and command output means for outputting a command converted by the co <br/> command conversion means to the other bus , Is provided.

[0009] In addition, one of the previous SL bus is a SCSI bus, another bus is ATA-2 bus.

FIG. 11 is a block diagram showing the functions of the bus converter according to the present invention. 100 and 101 are two interfaces connected to buses of different standards. Reference numeral 102 denotes a first control unit that controls input / output in one interface, and reference numeral 103 denotes a second control unit that controls input / output in the other interface. A control signal conversion unit 104 converts the input control signal into a control signal conforming to a bus standard opposite to the input side. Reference numeral 105 denotes a direct transfer unit that stores data input from one of the buses on the input side and outputs the stored data to the other bus on the output side. The direct transfer unit 105 is provided with a FIFO. In the bus converter having this configuration, a process of temporarily storing data input via one interface in the direct transfer unit 105 and outputting the data temporarily stored in the direct transfer unit 105 to the other bus And can be performed independently without synchronization. Therefore, data input from one interface and temporarily stored in the direct transfer unit 105 can be sequentially output from the other interface. Thus, the time it takes to transfer data Ru is greatly reduced. In addition, bus conversion device, start-up (ie,
The power supply when on) for the device connected to the bus, contact
The slowest speed specified in the following bus standard
The maximum data supported by the device accessed by
If you get the transfer speed, the maximum transfer speed you got here
Is set as a subsequent access speed to the device.
You. That is, data transfer is performed by a device connected to the bus.
At the maximum data rate supported by the device.
Thus, data transfer can be performed most efficiently. Moreover, the bus
Upper limit data supported by the device connected to
When you get the transfer speed, the device is connected
Access at the slowest speed specified by the bus standard
Useless access to the device.
Also do not do. Further, the interfaces 100, 1
01 and via direct transfer unit 105 (FIFO)
The transfer direction of the transferred transfer data can be switched.
Can be. That is, data can be transferred in both directions.
You.

[0011]

FIG. 1 is a diagram showing the configuration of a system to which a bus converter according to an embodiment of the present invention is applied. Reference numeral 1 denotes a personal computer, which operates as an initiator. A plurality of SCSI devices 2 operating as peripheral devices (targets) are connected to the personal computer 1 via a SCSI bus. The personal computer 1 is also connected to the bus converter 3 according to the embodiment of the present invention via a SCSI bus. 4 is IDE
It is an IDE device provided with an interface, and is connected to the bus converter 3 via the ATA-2 bus. In this system, the personal computer 1 handles the bus converter 3 and the IDE device 4 as one target. Note that the initiator is a device that starts an input / output operation, and the target is a device that executes the started input / output operation. In the system shown in FIG. 1, data transfer between the personal computer 1 and the SCSI device 2 is performed based on a known SCSI standard.

Hereinafter, the operation of the bus converter 3 according to the embodiment of the present invention will be described in detail. FIG. 2 is a block diagram showing the configuration of the bus converter according to the embodiment of the present invention. In this figure, the parts constituting the interfaces 100 and 101, the first control unit 102, the second control unit 103, the control signal conversion unit 104, and the direct transfer unit 105 shown in FIG. Are given. Reference numeral 11 denotes a CPU, and reference numeral 12 denotes a ROM that stores a program to be executed by the CPU 11. The CPU 11 has a built-in RAM 11a used as a work area necessary for executing the program. Note that the RAM 11a
May not be built in the CPU 11 (the CPU 11
May be attached externally). An ID setting unit 13 sets an ID number as a SCSI device. 14
Is an ATA-2 connector connected to the ATA-2 bus, and 15 is a SCSI connector connected to the SCSI bus. A PIO mode setting unit 16 sets a transfer mode with the IDE device 4. Reference numeral 17 denotes a pulse generation unit that generates a pulse signal of the mode set in the PIO mode setting unit 16. Reference numeral 18 denotes an I / O switching unit that outputs the pulse signal generated by the pulse generation unit 17 to the ATA-2 bus as IOW or IOR. 19 is a data transfer direction (from the personal computer 1 to the IDE device 4,
Or, from the IDE device 4 to the personal computer 1)
Is a transfer direction setting unit for setting the transfer direction. Reference numeral 20 denotes an IDE stop unit that stops the operation of the pulse generation unit 17. 21
Is an address generator for selecting an I / O register of the IDE device 4. Reference numeral 22 denotes a direct transfer setting unit for setting direct data transfer. Reference numeral 23 denotes a transfer data number counter for counting the number of transferred data. 24 is IDE
An IDE input / output control unit that takes in information emulated by the CPU 11 from the device 4 and outputs information emulated by the CPU 11 to the IDE device 4. Reference numeral 25 denotes a SCSI offset unit for setting a SCSI offset value in the synchronous transfer. Reference numeral 26 denotes an REQ cycle setting unit that sets the cycle of the REQ signal in the synchronous transfer. Reference numeral 27 denotes a transfer mode setting unit for setting synchronous transfer and asynchronous transfer. 28 is C from the SCSI bus
Importing information to be emulated by PU11, S
A SCSI input / output control unit that outputs information emulated by the CPU 11 to the CSI bus. 29
Is to capture control signals on the SCSI bus,
This is a SCSI control signal input / output unit that outputs a control signal to the bus. An SC 30 stops capturing data on the SCSI bus or outputting data on the SCSI bus.
This is an SI stop circuit. 31 is R when data is directly transferred.
This is a REQ generation circuit that generates an EQ signal. When not directly transferring data, the SCSI control signal input / output unit 29 generates a REQ signal. Reference numeral 32 denotes an input bus switching unit that switches a bus to which data is to be taken between a SCSI bus and an ATA-2 bus. Reference numeral 33 denotes an output bus switching unit that switches a data output bus between a SCSI bus and an ATA-2 bus. 34 is a SCSI bus or AT
A-2 F for temporarily storing data fetched from the bus
IFO. 35 is a W address part for designating an address for writing data to the FIFO 34, and 36 is a FIFO address part.
This is an R address portion for specifying an address from which data is read in O34. Reference numeral 37 denotes a flag circuit that compares addresses specified by the W address section 35 and the R address section 36 and outputs a SCSI stop signal or an IDE stop signal.
38 is a W for giving a write clock to the W address section 35;
A clock switching circuit 39 is an R clock switching circuit that supplies a read clock to the R address unit 36. 4
0 is an offset counter for counting the difference between the REQ signal and the ACK signal. 41 is an offset counter 4
This is a comparison circuit that compares the count value of 0 with the offset value set in the SCSI offset unit 25. An end detection circuit 42 determines whether or not the data transfer has been completed.

The SCSI bus is divided into the following eight phases depending on the state of use. Also, different phases do not occur at the same time. Bus Free Phase (BUS FREE PHAS)
E) The phase in which the SCSI bus is not used for any device. Arbitration phase (ARBITRATIO
N PHASE) This is a phase for determining a device that uses the SCSI bus. Selection PHA
SE) This is a phase for selecting a target for starting the input / output operation. Reselection phase (Reselection
PHASE) This is a phase in which a target that has interrupted an input / output operation previously started from the initiator reconnects to the initiator. Command phase (COMMAND PHASE) This is a phase in which the target requests a command from the initiator. Data phase (DATA PHASE) This is a phase in which the target requests the initiator to exchange data. Status phase (STATUS PHASE) This is a phase in which the target requests the initiator to receive status information. Message phase (MESSAGE PHASE) This is a phase in which the target requests the initiator to send and receive a message.

The above-mentioned items (1) to (4) are collectively described as an information transfer phase.
ase). The above-described phase transitions as shown in FIG. The control signals in the SCSI include BSY (BUSY), SEL (SELECT), and C
/ D (CONTROL / DATA), I / O (IN / O
UT), MSG (MESSAGE), REQ (REQU)
EST), ACK (ACKNOWLEDGE), RST
(RESET) and ATN (ATTENTION). FIG. 4 shows a control signal (RS) generated in each phase.
T) and a device (signal source) for outputting a control signal. Further, ID numbers are set for all devices (initiators and targets) connected to the SCSI bus.

On the other hand, the ATA-2 bus does not have a phase partition unlike the SCSI bus. The IDE device 4 performs communication with an external device via a plurality of I / O registers. The types of I / O registers include a data register used for data transfer, a sector count register for storing the number of data to be transferred, a sector number register for storing an address of data to be transferred or an address for storing data to be transferred. Etc. In addition, as a control signal, I / O which selects data on the data line is selected.
Write enable signal (IO
W) and a read enable signal (IO) for outputting the data stored in the selected I / O register to the data line.
R) and the like. Note that SCSI can transfer only 1-byte data at a time, but IDE can transfer 2-byte data.

The bus converter 3 is connected to the CPU 1 when the power is turned on.
1 issues an IDENTIFY DEVICE command to the IDE device 4 connected by the ATA-2 bus. This command is specified by IDE and
It is issued when the parameter information of the DE device 4 is read. At this time, the CPU 11 accesses in the mode 0 with the lowest data transfer speed. Therefore, communication between the bus converter 3 and the IDE device 4 is reliably performed. The parameter information acquired by the bus converter 3 at this time includes a data transfer mode supported by the connected IDE device 4. Therefore, the bus converter 3 sets P
This transfer mode is set in the IO mode setting section 16. Therefore, communication between the bus converter 3 and the IDE device 4 is as follows.
Thereafter, the transfer is performed in this transfer mode. That is, the bus converter 3 and the IDE device 4 perform communication in the upper limit transfer mode. In this embodiment, it is assumed that 0 indicating the asynchronous transfer is set in the transfer mode setting unit 27. When the transfer mode is set to asynchronous transfer, the offset value set in the SCSI offset unit 25 is 1.

Here, the personal computers 1 to I
A process of transferring data to the DE device 4 will be described.
The personal computer 1 has BSY on the SCSI bus.
It is determined whether or not the SCSI bus is in the bus free phase based on whether or not both control signals SEL and SEL are output. Here, if the SCSI bus is not in the bus free phase, the processing is stopped. SCS
If the I bus is in the bus free phase, the process proceeds to the arbitration phase, in which BSY is set to low level and at the same time, its own ID is output on the data line. SCSI
According to the standard, one data line is connected to each device connected to the bus.
Books are assigned one by one. Specifically, the ID number is n (n
Is a number from 0 to 7). For example, the data line D7 is assigned to the device having the ID number 7. The output of the own ID number is performed by outputting a signal to the data line assigned to the user. At this time, if there are multiple devices that output BSY,
The ID numbers are output from the plurality of devices, and these devices compete for the right to use the SCSI bus. In this case, the device with the highest priority (higher ID number) is the SC
The right to use the SI bus is obtained. Other devices are
The processing is stopped by skipping the output signal (BSY, ID number).

Here, the personal computer 1
It is assumed that the right to use the CSI bus has been granted. with this,
The arbitration phase ends, and the process proceeds to the selection phase. When the personal computer 1 proceeds to the selection phase, the personal computer 1 outputs the SEL signal and then outputs the BS signal.
Turn off the Y signal. Then, a signal is output to a data line assigned to the bus converter 3 as a data transfer partner. Note that the ID number of the bus converter 3 is the ID setting unit 1
3 is set. At this time, the personal computer 1 also outputs a signal to the data line assigned to itself. The device connected to the SCSI bus is S
Since the EL signal is output, it is recognized that the present is the selection phase. Bus converter 3
Recognizes that it has been selected as a data transfer partner by outputting a signal to the data line assigned to itself, and outputs a BSY signal from the SCSI control signal input / output unit 29 onto the SCSI bus. Personal computer 1
Knows that the BSY signal has been output, turns off the SEL signal, ends the selection phase, and proceeds to the command phase.

FIG. 5 is a flowchart showing a command receiving process of the bus converter in the command phase. The bus converter 3 includes a SCSI control signal input / output unit 29
Outputs a C / D signal on the SCSI bus (n
1) and then output a REQ signal to the SCSI bus (n
2). When detecting that the bus converter 3 has output the REQ signal, the personal computer 1 outputs a command code to be transferred to the data line and outputs an ACK signal. When the bus converter 3 knows that the ACK signal has been output (n3), it takes in the command code on the data line into the SCSI input / output control unit 28 and turns off the REQ signal (n4, n5). When the personal computer 1 learns that the REQ signal has been released, the personal computer 1 releases the command placed on the data line and outputs the AC signal.
Turn off the K signal. As a result, the personal computer 1 has transferred the one-byte command code to the bus converter 3. Here, in the SCSI standard, a command is composed of a command code of 6 to 12 bytes. Therefore, in the above-described processing, only a part of the command is transferred. When the ACK signal is depressed (n6), the bus converter 3 determines whether or not the command transfer has been completed (n7), and returns to n3 if the command transfer has not been completed. The bus converter 3 can determine the total number of bytes of the command from the information of the first byte transmitted first. As described above, the transfer of the command is repeatedly performed one byte at a time.

When the reception of the command is completed, the bus converter 3 emulates the received command and transfers it to the IDE device 4. FIG. 6 shows that the bus converter
It is a flow chart which shows transfer of a command to DE equipment. The bus converter 3 emulates the command transferred from the personal computer 1 into a command conforming to the ATA-2 bus standard (n11). Then, this emulated command is transferred by 1 byte I
The data is transferred to the DE device 4. As described above, the IDE device 4
Performs communication with an external device via a plurality of I / O registers. The address generator 21 sets an address for specifying the I / O register according to the content of the command to be transferred (n12). Next, a command to transfer to the lower 8 bits of the data line is placed (n13), and the I / O switching unit 18 outputs the pulse signal generated by the pulse generation unit 17 to the ATA-2 bus as an IOW signal (n14). For example,
The number of data (the number of sectors) to be transferred as a part of the emulated command is placed on the data line, and an address for designating a sector count register provided in the IDE device 4 is generated by the address generation unit 21, and the IOW is generated.
Output the signal to the ATA-2 bus. When a head address for storing data to be transferred, which is a part of the emulated command, is placed on the data line, an address for designating a sector number register is generated by the address generation unit 21 and the IOW signal is transmitted to the ATA-2. Output to the bus. Then, the bus converter 3 confirms whether or not the transfer of the emulated command has been completed (n15), and if the transfer of the command has not been completed, returns to n12 and repeats the above processing. When it is confirmed at step n15 that the transfer of the command has been completed, the process ends. Note that the IOW signal is
It is generated periodically at a frequency based on the mode set in the mode setting section 16. So, in practice,
The CPU 11 places a command to be transferred to the data line in accordance with the pulse interval of the IOW signal, and generates an address for designating a corresponding I / O register in the address generator 21.

When the IOW signal is input, the IDE device 4 writes the information on the data line into the I / O register specified by the address setting unit 21.
Then, the information written in the I / O register is fetched and processed. Thus, the bus converter 3
Emulates the command sent from the personal computer 1 and transfers it to the IDE device 4.

When the above processing is completed, the bus converter 3 returns the C / D to the high level. This allows SCSI
The bus completes the command phase and proceeds to the data out phase. When proceeding to the data out phase, the bus converter 3 performs settings for transferring data. In the transfer direction setting unit 19, 0 indicating transfer from the personal computer 1 to the IDE device 4 is set. Further, the number of data to be transferred is set in the transfer data number counter 23. The W address section 35 and the R address section 36 are set to the initial value 0. The W clock switching circuit 38 performs switching using the ACK signal transferred from the personal computer 1 as an output signal. The R clock switching circuit 39 is a pulse generation circuit 1
Switching is performed so that the pulse signal generated in step 7 is output. The address of the address generator 21 is set to the address of the data register. The count value of the offset counter 40 is reset (0). The input data switching unit 32 is SCSI
Outputs the data input from the connector 15 and outputs
Switching to input to O34 is performed. The output data switching unit 33 performs switching to output the data read from the FIFO 34 to the data line of the ATA-2 connector 14.

When the above setting is completed, the bus conversion device 3 independently performs a process of fetching data from the personal computer 1 and a process of outputting data to the IDE device 4 without synchronizing. FIG. 7 is a time chart showing the data transfer processing. The figure shows the transfer of 8-byte data. The capacity of the FIFO 34 is 4 bytes. As described above, the data that can be transferred at a time on the SCSI bus is one byte,
In the A-2 bus, data that can be transferred at one time is 2 bytes. The flag circuit 37 outputs a SCSI stop signal when the FIFO 34 is full of data not transferred to the IDE device 4, and stops the IDE when the data not transferred to the IDE device 4 is 1 byte or less. Output a signal.

Before the start of the direct data transfer, no data has been sent from the personal computer 1 to the bus converter 3. Therefore, the flag circuit 37
A DE stop signal is output. The IDE stop signal is ID
It is input to the E stop circuit 20. IDE stop circuit 20
Stops the operation of the pulse generation circuit 17, and IO
The W signal is not output from the ATA-2 connector 14. Further, no SCSI stop signal is output from the flag circuit 37. In the bus converter 3, the end detection circuit 42 sets the transfer end signal to low, and starts the data transfer processing.
The REQ signal output from the REQ generation circuit 31 is SC
The data is output from the SI connector 15 and received by the personal computer 1.

The personal computer 1 that has received the REQ signal puts 1-byte data on the data line and sends an ACK signal to the bus converter 3 on the control line. In the bus converter 3, the received ACK signal is input to the W address unit 35 via the W clock switching circuit 38. The W address unit 35 increments the set address by one and supplies a write signal to the FIFO 34. When the write signal is input, the FIFO 34 transfers the data transferred from the personal computer 1 input via the input data switching unit 32 to the address (incremented address) specified by the W address unit 35. Write. Also,
The ACK signal transferred from the personal computer 1 is input to the REQ generating circuit 31, and the REQ generating circuit 31 turns off the REQ signal by inputting the ACK signal. On the other hand, when the REQ signal is turned off by the bus converter 3, the personal computer 1 turns off the ACK signal. Thus, the transfer of 1-byte data from the personal computer 1 to the bus converter 3 is completed. Further, the transfer data number counter 23 decrements the count value by one with an ACK signal input from the personal computer 1. The REQ generating unit 31 checks whether or not the count value of the transfer data number counter 23 is 0, and if not, determines that data not transferred from the personal computer 1 remains.
Then, as described above, the REQ generating unit 31 again sets REQ.
A signal is generated, and 1-byte data is taken in from the personal computer 1. This process is repeated, and when the count value of the transfer data number counter 23 becomes 0, it is determined that all the data has been fetched from the personal computer 1, and a stop signal is input to the SCSI stop circuit 30. As a result, the REQ generator 31 stops operating. Even if the count value of the transfer data number counter 23 is not 0, if the address of the R address section 36 matches the address of the W address section 35, the flag circuit 37 outputs
A stop signal is input to the SI stop circuit 30, and the REQ generator 31 stops operating. This is to prevent new data from being written on data that has only been written to the FIFO 34 and has not been transferred to the IDE device 4. When initial values are set in the R address section 36 and the W address section 35 (when data transfer is started)
At this time, the address of the R address section 36 and the address of the W address section 35 match, but at this time, no SCSI stop signal is output.

In the above-described processing, the data transferred from the personal computer 1 is written into the FIFO 34, and when the address of the W address section 35 becomes larger than the address of the R address section 36 by two or more, the flag circuit 37 outputs the IDE stop signal. Stop output of As a result, the pulse generation circuit 17 starts operating, and the PIO mode setting section 16
Outputs a pulse signal according to the mode set in. This pulse signal is input to the R address unit 36 via the R clock switching unit 39. R address section 36
Increments the set address by one, and places the data of this address on the lower eight-bit data line. Further, the R address section 36 increments the address by one and places the data of this address in the upper 8 bits. The output data switching circuit 33 outputs the 16-bit data from the ATA-2 connector 14 to a data line of the IDE bus. Also, the pulse signal generated by the pulse generation unit 17 passes through the I / O switching unit, and is converted into an AT signal as an AT signal.
Output to A-2 bus. The IDE device 4 uses the IOW signal as a trigger to set the data register of the address set by the address setting unit 21 on the data line.
Write 6-bit data. The data written in the data register is finally taken into the IDE device 4 for processing. By the above-described processing, the data sent from the personal computer 1 and written in the FIFO 34 is transferred to the IDE device 4 two bytes at a time. As described above, when the data transmitted from the personal computer 1 is stored in the FIFO 34, the bus converter 3 sequentially transfers the data to the IDE device 4. That is, a process of storing data sent from the personal computer 1 in the FIFO 34 and a process of storing the data stored in the FIFO 34 in the IDE device 4.
Is performed independently without synchronization. In the present specification, performing these two processes independently without synchronizing is referred to as direct transfer.

When all the data transferred from the personal computer 1 has been transferred to the IDE device 4, the data transfer ends. The end of the data transfer is determined by the end detection unit 42.
Is determined. The end detecting unit 42 ends the data transfer when the transfer data number counter 23 is 0, the address of the R address unit 36 matches the address of the W address unit 35, and the count value of the offset counter 40 is 0. It is determined that the data transfer has been completed, and the data transfer end signal is set high.

Upon completion of the data out phase, the personal computer 1 proceeds to the status phase or the message phase, and determines whether or not an error has occurred during data transfer, and what kind of error has occurred if an error has occurred. Check whether it has occurred. Then, the process returns to the bus free phase.

In the above-described embodiment, the data transfer on the SCSI bus is asynchronous transfer. However, in this embodiment, the transfer will be described as synchronous transfer. The process from the bus free phase to the completion of the command phase is the same as that of the above-described embodiment, and the description is omitted here. However, in the message phase, messages are exchanged between the personal computer 1 and the bus converter 3. This message exchange is based on the SDTR
(Synchronous Data Transfer
r Request), which is a process in which data transfer in the synchronous mode is determined in advance. In this process, an offset value and a transfer cycle are set. Synchronous transfer simply means that a target transmits multiple REs without waiting for an ACK from the initiator.
This is a transfer method that can advance Q. In addition, the initiator has the same number of ACKs as the REQ sent from the target.
Is output. However, the number of REQs that can be read is less than or equal to the set offset, and when REQs are output continuously, they must be output at the set transfer cycle. In this transfer method, since the target can output the REQ without waiting for the ACK from the initiator, the delay time due to signal transmission can be reduced. Therefore, there is an advantage that the time required for data transfer can be reduced. For example, in the above-described asynchronous transfer, the time required for 1-byte transfer is the time T1 until the REQ from the bus converter 3 reaches the personal computer 1, and the time A from the personal computer 1
Time T2 until CK arrives at the bus converter 3, time T3 until the bus converter 3 drops the REQ to the personal computer 1, and bus conversion when the personal computer 1 drops ACK. A time T4 for transmitting to the device 3 is required. However, in the case of the synchronous transfer, the transfer of one byte includes the time T1 until the REQ from the bus converter 3 reaches the personal computer 1 and the time T1 until the ACK from the personal computer 1 reaches the bus converter 3. It only takes time T2. In other words, the transfer of one byte of data from the control signal to and from the bus made two round trips becomes one round trip.

FIG. 8 is a time chart in the data out phase at the time of synchronous transfer. In this example, the offset is 2. As in the above embodiment, the number of transfer data is 8 bytes and the capacity of the FIFO is 4 bytes in the figure. Before the direct transfer of data is started, the flag circuit 37 outputs the IDE stop signal, stops the pulse generation circuit 17 and stops the ATA-2 connector 14 from outputting the IOW signal as in the case of the asynchronous transfer. I have to. When the end detecting circuit 42 sets the transfer end signal to low, the REQ generating circuit 31 outputs a REQ signal. The REQ signal output here is a pulse signal of the cycle set in the transfer cycle setting unit 26. The offset counter 40 increments the count value by one when a pulse output from the REQ generation circuit 31 is input, and sends an ACK from the personal computer 1 via the SCSI bus.
When a signal is input, the count value is decremented by one. The comparison circuit 41 compares the count value of the offset counter 40 with the offset value set in the offset setting unit 25, and if they match, the SCSI stop circuit 30
Input a SCSI stop signal. The SCSI halt circuit 30 to which the SCSI halt signal is input becomes the REQ generation circuit 31
Stop the operation of. This is to prevent more REQ signals from being set ahead of the set offset value.

Upon receiving the ACK from the personal computer 1, the bus converter 3 converts the 1-byte data on the data line into the FI, as in the asynchronous transfer described above.
Write to FO34. Note that the REQ generation circuit 31 does not wait for this ACK signal and turns off the REQ signal.
It is generated at the transfer cycle set in the transfer cycle setting unit 26. When the number of REQ signals is equal to the set offset, a SCSI stop signal is input to the SCSI stop circuit 30, and the REQ generation circuit 3
1 is deactivated.

The process of transferring the data written in the FIFO 34 to the IDE device 4 via the ATA-2 bus and the process of detecting the end of the data transfer are the same processes as the above-described asynchronous transfer. . When the data transfer is completed, the end detection circuit 42 sets the transfer end signal to high.

Next, if the data transfer direction is the IDE device 4
A case where the transfer is from the personal computer 1 to the personal computer 1 will be described. Also in this case, the processing from the bus free phase to the command phase is the same as that of the above-described two embodiments, and thus the description is omitted. However, the contents of the commands communicated between the personal computer 1 and the bus converter 3 are different. This embodiment will be described below with the transfer method being asynchronous. Proceeding to the data out phase,
The bus converter 3 makes settings for transferring data. The transfer direction setting unit 19 sets 1 indicating transfer from the IDE device 4 to the personal computer 1. Further, the number of data to be transferred is set in the transfer data number counter 23. The W address section 35 and the R address section 36 are set to the initial value 0. The REQ signal output from the REQ generator 31 is switched as the output of the W clock switching circuit 38. The output of the W clock switching circuit 38 is switched to a pulse signal generated by the pulse generation circuit 17.
The address of the address generator 21 is set to an address that specifies a data register. The count value of the offset counter 40 is reset. The input data switching unit 32 is A
Data input from TA-2 connector 14 is FIFO
Switching to input to 34 is performed. The output data switching unit 33 is F
The data read from the IFO 34 is transferred to the SCSI connector 1
Switching to output to the data line No. 5 is performed.

When the above setting is completed, the bus converter 3 performs the data transfer process to the personal computer 1 and the data fetch process from the IDE device 4 independently without synchronizing. FIG. 9 is a time chart showing the data transfer processing. It should be noted that the figure shows a case where the number of data to be transferred is 8 bytes and F
The capacity of the IFO 34 is 4 bytes. As mentioned above,
On the SCSI bus, data that can be transferred at one time is one byte, while on the ATA-2 bus, data that can be transferred at one time is two bytes. For this reason, the flag circuit 37
When the free space of O34 is 1 byte or less, an IDE stop signal is output, and when there is no data not transferred to the personal computer 1 in the FIFO 34, a SCSI stop signal is output.

Before the direct transfer of data is started, no data has been transferred from the personal computer 1 to the bus converter 3. Therefore, the flag circuit 37
Outputs SI stop signal. This SCSI stop signal is input to the SCSI stop circuit 30. SCSI
The stop circuit 30 stops the REQ generator 31 and sets the SCS
The REQ signal is not output from the I connector 15. The end detection circuit 42 sets the transfer end signal to low, and the following processing is started. The pulse signal generated by the pulse generation circuit 17 is transmitted to the IOR
It is output to the ATA-2 bus as a signal.

Upon receiving the IOR signal, the IDE device 4 outputs the 2-byte data stored in the data register to the data line of the ATA-2 bus. Bus converter 3
Then, the 2-byte data sent from the IDE device 4 is written into the FIFO 34. At this time, the IOR signal is W
It is input to the W address unit 35 via the clock switching circuit 38. The W address unit 35 increments the address by 1 and writes the lower 8 bits of the transmitted 2-byte data to the incremented address of the FIFO 34. Then, the W address unit 35 further increments the address by one and writes the upper 8 bits of the transferred data to this address of the FIFO 34.

Further, the transfer data number counter 23 is decremented by the IOR signal, and if the count value is not 0, the IOR signal is output again to take in 2-byte data from the IDE device 4. Here, unlike the above embodiment, since 2-byte data is transferred, the transfer data number counter 23 decrements the count value by two. The IDE device 4 writes the data of the first address in the data register before the IOR signal is input, and outputs the data in the data register when the IOR signal is input, and then outputs the data in the data register. Is updated to the data at the next address. Therefore, every time the IOR signal is input, data can be transferred by two bytes.

In the bus converter 3, when the SCSI stop signal from the comparison circuit 41 disappears, the REQ generator 31 starts operating. When the REQ generating unit 31 outputs the REQ signal, the REQ signal is input to the R address unit 36 via the R clock switching circuit 39. R address section 36
Increments the address by 1, and puts the 1-byte data stored at this address on the data of the SCSI bus and outputs it. When the personal computer 1 receives the REQ signal from the bus converter 3, the personal computer 1 fetches one byte of data placed on the data line at this time. The personal computer 1 has an AC bus on the SCSI bus.
Outputs K signal. Upon receiving the ACK signal, the bus converter 3 releases the REQ signal and also releases the signal carried on the data line. If data that has not been transferred to the personal computer 1 is stored in the FIFO 34, 1-byte data is transferred to the personal computer 1 together with the REQ signal as described above.
Whether data not transferred to the personal computer 1 is stored in the FIFO 34 is determined by comparing the addresses set in the W address portion 35 and the R address portion 36 as described above. When the end detection circuit 42 determines that the data transfer is completed, it sets the transfer end signal to high.

As described above, data is transferred from the IDE device 4 to the bus converter 3 in units of 2 bytes, and this data is transferred to the personal computer 1 in units of 1 byte.
In addition, a direct transfer method is employed in which the process of transferring data from the IDE device 4 to the bus converter 3 and the process of transferring data from the bus converter 3 to the personal computer 1 are performed independently of each other without synchronization. So
The data transfer speed can be improved.

Next, the processing of the data in phase in the synchronous transfer mode will be described. Processing from the bus free phase to the completion of the command phase is the same as in the above-described embodiment. FIG. 10 shows a time chart in this processing. In this example, the offset value is 2
And The number of data to be transferred is 8 bytes and F
The capacity of the IFO 34 is 4 bytes. Before the direct transfer of data is started, the flag circuit 37 outputs the SCSI stop signal, stops the REQ generating circuit 31 and stops the REQ signal from being output from the SCSI connector 15 as in the case of the asynchronous transfer. I have. Further, the process of capturing the transfer data from the IDE device 4 is the same. The difference is that the data stored in the FIFO 34 is output to the SCSI bus. As described above, in the synchronous transfer, the target does not wait for an ACK from the initiator,
The EQ signal can be preempted. At this time, in the data-in phase, the bus converter 3 outputs the REQ signal, and also outputs the data to be transferred onto the data line. When the personal computer 1 receives the REQ signal, it only takes in one byte of data placed on the data line and returns an ACK. This is for confirming whether or not the same number of ACK signals as the REQ signals generated by the REQ generator 31 have been returned from the personal computer 1. In the case where the same number of ACK signals as the REQ signal are not returned in the synchronous transfer, it is considered that some error has occurred during data transfer.

In the above embodiment, the bus converter 3 and the IDE device 4 are connected via the ATA-2 bus. However, an ATAPI device may be connected instead of the IDE device 4. Since the interface of the ATAPI standard and the interface of the IDE standard are the same in terms of hardware and differ only in the software specifications,
Even if an ATAPI device is connected instead of the device 4, it can be used without any problem. Further, the bus converter 3 and the IDE device 4 may be housed in one case. In this case, the case has an ATA-2 connector and an SCS
If two I connectors are provided, SCSI, ATA-2
Either bus can be connected. Therefore, the connection bus of the peripheral device can be changed and used. Further, by using the bus converter of the present embodiment, the IDE device can be used regardless of whether it is connected to the ATA-2 bus or the SCSI bus. In addition, cheap I
By attaching the bus converter 3 to the DE device 4, the device can be operated as a SCSI device, and an inexpensive SCSI device can be provided. Further, in the above embodiment, the SCSI bus and the ATA-2
Although the description has been given of the bus converter 3 for performing conversion between buses, the present invention is not limited to this, and the present invention can be applied to a bus converter for performing conversion between two buses having different standards. it can.

[0042]

As described above, in the bus converter of the present invention, the data input from one bus is stored in the FIFO, and the data stored in the FIFO is output to the other bus. The input of data to the bus converter and the output of data from the bus converter can be executed independently without synchronization. For this reason,
This has the effect of significantly reducing the time required for data transfer. Further, at the time of startup slowest specified in the bus standard for the device connected to the output side bus
Access speed, the maximum data transfer rate supported by the device can be reliably acquired in a single access.
Can be obtained. And subsequent access to the device
The speed is now set to the upper limit transfer speed I got here
Thus, data transfer can be performed most efficiently. Further
The transfer direction of data input / output via FIFO is switched
The data transfer can be performed in both directions.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a system using a bus converter according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a bus converter according to an embodiment of the present invention.

FIG. 3 is a diagram showing transition of phases of a SCSI bus.

FIG. 4 is a diagram illustrating a control signal and a source of the control signal in each phase.

FIG. 5 is a flowchart showing a command receiving process of the bus conversion device in a command phase.

FIG. 6 is a flowchart showing a command transfer process of the bus conversion device in a command phase.

FIG. 7 is a timing chart when data is transferred from a personal computer to an IDE device in asynchronous transfer.

FIG. 8 is a timing chart at the time of data transfer from a personal computer to an IDE device in synchronous transfer.

FIG. 9 is a timing chart at the time of data transfer from an IDE device to a personal computer in asynchronous transfer.

FIG. 10 is a timing chart at the time of data transfer from an IDE device to a personal computer in synchronous transfer.

FIG. 11 is a block diagram illustrating functions of a bus conversion device according to the present invention.

[Explanation of symbols]

 Reference Signs List 1-Personal computer 3-Bus converter 4-IDE device 34-FIFO 100, 101-Interface 102-First controller 103-Second controller 104-Control signal converter 105-Direct transfer unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 13/36 310 G06F 13/36 320 G06F 13/14 330

Claims (3)

(57) [Claims] 1. Two interfaces respectively connected to two buses having different standards, and a bus as an input side and an output side with respect to the two buses.
And output bus switching means for switching bus, a data writing means for writing the transfer data input from the bus to the output bus switching means has the input side to the FIFO, the transfer data written in the FIFO Above input / output bus
And data output means for scan switching means outputs the bus that the output side, at startup, to devices connected via the bus
Is specified in the standard of the bus to which the device is connected.
Transfer speed acquisition means for accessing at the slowest speed to obtain an upper limit data transfer speed supported by the device
And the upper limit data transfer speed obtained by the above transfer speed obtaining means.
Is the access speed to the device connected to the bus.
A bus conversion device comprising: 2. A method according to claim 1, wherein a command input from one bus is transmitted to another bus.
To convert to a command that conforms to the standard of the other bus
Conversion means, and the command converted by the command conversion means
And a command output means for outputting the command to the
On-board bus converter. 3. The method of claim 1, wherein one of said buses is a SCSI bus.
2. The method of claim 1, wherein the other bus is an ATA-2 bus.
3. The bus converter according to 2.