KR20000067533A - Memory access system and method thereof - Google Patents

Abstract

PURPOSE: A memory access system and its control method is provided to reduce a cache refill time for referencing a cache at a main memory when a cache miss occurs. CONSTITUTION: A memory access system comprises a memory bank unit(62), a memory address unit(60), a row address table unit(64) and a comparator(68). The memory bank unit(62) includes a sub-array(37) for storing data accessed by row and column address, and a sensing amplifier(35) temporarily stored when the data is accessed from the sub-array(37). The memory address unit(60) stores an address information for accessing the data, stored in the sub-array(37), by a control of a central controller. The row address table unit(64), selected by the address information of the memory address unit(60), expresses that a page data stored in the row address is held by the sensing amplifier(35). The comparator(68) compares the row address information, of the row address table unit(64), with the address information of the memory address unit(60).

Description

Memory access system and control method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access system and a control method thereof, and more particularly, to a memory access system for reducing the cache refill time for referencing a cache in a main memory when a cache miss occurs. It is about.

In general, processor and memory design techniques evolve differently around speed and density, with a central controller 10 and a cache 12 as shown in a block diagram illustrating a computer system with off-chip main memory of FIG. Information processing between a processor and a memory in a general computer system in which a memory 100 in which a memory 100 is integrated into a processor 100 and an off chip main memory 18 are connected by a memory bus 16. The performance gap in speed is increasing year by year.

However, with the rapid development of VLSI technology, the amount of transistors that can be integrated on a single chip is increasing significantly. Also, the memory integrated design technology has a single capacity larger than the memory capacity required by computer systems in many applications. It is expected to develop to a level that can be integrated into chips. Therefore, as a solution to overcome the increasing performance gap between the processor and the memory year after year, as shown in the block diagram of a computer system having an on-chip main memory of Figure 2 processor-memory integrated structure having an on-chip dynamic RAM (RAM) main memory Is actively underway.

As shown in FIG. 2, the structure of the on-chip main memory increases the width and clock frequency of the memory bus 26 between the cache 24 and the main memory 28 to increase the memory bandwidth and the low memory delay. latency).

It also has the advantage of low power because it does not drive off-chip memory buses. General DRAMs increase in size by a multiplier of 2 depending on generation, but on-chip DRAMs can be freely sized and shaped depending on the application. And because the number of chips can be reduced, the board size can be reduced.

3 shows a simplified internal structure of a DRAM having multiple banks and a shared sense amplifier.

The DRAM is composed of several banks, but two banks are described in FIG. 3 for explanation. Each bank, consisting of bank 0 and bank 1, has several subarrays 37, and a shared sense amplifier 35 (hereinafter referred to as sense amplifiers) at each end of each subarray 37. Unity), a row decoder 31, and a column decoder 33.

That is, since a plurality of memory data are stored in a grid form in each subarray 37, the memory data in a given subarray can be accessed by a row address and a column address.

In addition, each bank can operate independently. The larger the number of banks, the lower the bank collision rate, which is the probability that the cache refill request by the cache miss will collide with the previous cache request, resulting in higher DRAM performance. . However, if the number of banks is increased based on the same memory capacity, there is a problem in that the chip size increases and power consumption increases.

19th Conf. On Advanced Research in VLSI, 1997, "The hierarchical multi-bank DRAM: A high-performance architecture for memory integrated with processors" by T. Yamauchi, L. Hammond, and K. Olukotun uses additional hardware to operate subarrays within each bank as semi-independent banks, thereby reducing the bank collision rate without increasing the number of banks.

In addition, US Patent No. 5,652,860 (Memory control device, 1997) of the prior art relates to a memory control device for determining a fast page mode (FPM) mode and a normal mode in a virtual memory (virtual memory) system, The memory system compares the previous memory access request with the virtual address for the memory access request of the virtual address without defining the cache memory, and decides to operate in FPM mode using the detection amplifier if it is the same. will be.

4 is a diagram for describing an access sequence of a DRAM.

As shown, the access order of the DRAM is generally divided into three steps. The precharge 42 is a step of charging the lines in the DRAM to a constant voltage, which is a preparation step for accessing the DRAM.

When the precharge 42 is performed, the existing DRAM page data contained in the sensing amplifier 35 is erased. The row access 44 reads one row data from the subarray 37 inside the DRAM to the sense amplifier 35. At this time, the raw data read into the sense amplifier at once is a DRAM page. The column access 46 selects and reads a desired column bit from the DRAM pages read by the sense amplifier 35.

5A is a diagram for describing a main memory access control method in the prior art.

In the illustrated main memory access control method, a method of performing two cache refills when two consecutive cache misses occur is shown. That is, one cache processing block 52 represents precharging, row access, and column access in sequence, assuming that the size of a single row processing block 52 is processed after four column accesses in a general off-chip main memory. In this case, the x-axis represents the address space of the data and the y-axis represents time.

Page mode, which is an access control method of DRAM to refer to the miss block when a cache miss occurs in the existing off-chip DRAM main memory, FPM developed based on this, Extended Data Out (EDO) mode, Synchronous D In RAM, etc., one miss block reference, or cache refill, is performed through precharge, low access, and multiple column accesses. Next, the controller precharges the DRAM in order to prepare for DRAM access, that is, next block reference processing, according to a general scheme.

Thus, in the second cache refill processing block 54 shown in FIG. 5A, the access order and time are the same as the first cache refill processing block 52. At this time, FIG. 5A assumes a situation in which cache misses occur continuously. If a subsequent cache miss does not occur continuously and occurs at an interval longer than the cache refill processing time, the precharge is performed by a general DRAM access controller. By doing so, the cache refill time can be reduced.

5B is a diagram for explaining another main memory access control method in the related art.

That is, FIG. 5B is a main memory access control method different from the related art. In the processor-memory integrated structure having the on-chip main memory, the cache refill process when the width of the memory bus between the cache and the on-chip main memory is configured as the cache block size It is a figure which shows the method.

As shown, one pre-charge, low access, and only one column access can handle one cache refill request. In addition, as shown in FIG. 5A, when a single cache refill request is processed using a general DRAM access controller, FIG. 5B may precharge to process the next cache refill request, thereby erasing data previously stored in the detection amplifier 35. do. Therefore, the second cache refill process is the same as the first cache refill process.

Page mode and FPM, EDO, and Synchronous DRAMs, which are the general DRAM access control methods, are performed by performing continuous column access several times among DRAM page data read by the sense amplifier 35 through raw access. Handles block access requests.

However, in the above schemes, when the size of the memory bus becomes as large as the cache block size, one block access request is processed by only one column access. Thus, the DRAM access control scheme described in FIGS. 5A and 5B is not limited to the sense amplifier. There is a problem that the stored DRAM page data cannot be used again by precharging the DRAM to prepare for the next cache refill after one cache refill process.

Accordingly, an object of the present invention for solving the above problems, as shown in Figure 5c, after processing one block access request according to the cache needs, the block data to the sense amplifier by the control of the central control unit If a second cache request is generated that requires any block data included in the same page data in the state that the page data including the data is retained, the page data held in the sensing amplifier without precharging and low access is generated. The purpose of the present invention is to provide a memory access system and a control method for processing a second cache request by column access.

1 is a block diagram illustrating a computer system having off-chip main memory.

2 is a block diagram illustrating a computer system having an on-chip main memory.

3 shows a simplified internal structure of a DRAM having multiple banks and a shared sense amplifier.

4 is a diagram for describing an access sequence of a DRAM.

5A is a diagram for describing a main memory access control method in the prior art.

5B is a diagram for explaining another main memory access control method in the related art.

5C is a diagram for describing a main memory access control method according to the present invention.

6 is a block diagram illustrating a memory access system according to the present invention.

FIG. 7 is a flowchart illustrating a control method of the memory access system of FIG. 6.

8 is a view illustrating a change in cache refill time according to a change in a bank collision rate and a DRAM page access success rate according to the present invention.

<Explanation of symbols for main parts of drawing>

10, 22. Central control unit 12, 24 .. Cache

16, 26. Memory bus 18, 28. Main memory

31 .. rod decoder 33 .. column decoder

35 .. Sense amplifiers 37 .. Subarrays

42 .. Precharge 44 .. Low Access

46 .. Column Access 60 .. Memory Address

62 .. Memory Bank 64 .. Low Address Table

68 .. Comparators 100, 200 .. Processor

In order to achieve the above object, the memory access system of the present invention includes a subarray in which data accessed by a row and a column address are stored, and a sense amplifier temporarily stored when data is accessed from the subarray. Memory bank unit comprising a; A memory address unit including address information for accessing data stored in a predetermined subarray in the memory bank unit by control of a central controller; A low address table unit selected by address information of the memory address unit and including low address information indicating whether page data stored in any low address of the memory bank unit is retained in the detection amplifier; And comparing the row address information of the row address table unit selected by the memory address unit with the address information included in the memory address unit and accessing the same row address, by the column address only. And a comparator for accessing the page data of the sense amplifier.

In order to achieve the above object, the memory access control method of the present invention is a memory access control method in which a cache request generated from a central controller is processed by precharge, row access, and column access. After processing a block access request of the second cache request, when the second cache requesting any block data included in the same page data is generated while the page data including the block data of the sense amplifier is retained. The second cache needs to be processed in the page data held by the sense amplifier by column access.

In accordance with another aspect of the present invention, there is provided a memory access control method according to an embodiment of the present invention, wherein page data including block data is stored in a sense amplifier by precharge and raw access, and cache refilled by column access from the page data. In the memory access control method that the request is processed,

After processing one block access according to the cache necessity, the page data in the state in which page data including the block data is held in the sense amplifier without precharging the block data held in the sense amplifier. If a second cache request is generated that requires any block data that contains a second cache request, and a second cache request is required to request page data held by the sense amplifier, a block is generated from the page data held by the sense amplifier. Memory access control method, characterized in that the time the data is column access is calculated by the following equation.

Where T _{DRAM_access} is the data output time, t _RP is the precharge time, t _RCD is the low access time, t _CAC is the column access time, t _RAC is the sum of t _RCD and t _CAC , and the local column access time, α _i is the cache. The probability that the request needs to be serviced in the i-th DRAM bank, β _i is the probability that the cache request collides with the previous request being serviced in the i-th DRAM bank, and γ _i is the required data of the i-th DRAM bank. It is the probability that the sense amplifier already holds.

Hereinafter, the configuration and operation of the present invention will be described with reference to FIGS. 6 to 8.

6 is a block diagram illustrating a memory access system according to the present invention.

As shown, the memory access system of the present invention includes a memory bank 62, a memory address 60, a low address table 64, and a comparator 68.

The memory bank unit 62 includes a subarray 37 in which data accessed by a row and a column address are stored, and a sense amplifier 35 temporarily stored when data is accessed from the subarray 37.

The memory address unit 60 includes address information for accessing data stored in a predetermined subarray 37 in the memory bank unit 62 under the control of the central controller.

The low address table unit 64 includes low address information indicating whether any low address data of the memory bank unit 62 indicated by the address information of the memory address unit 60 is held in the sense amplifier 35. .

The comparison unit 68 compares each of the low address information of the low address table unit 64 selected and output by the memory address unit 60 and the address information included in the memory address unit 60, respectively, and compares the same. If it is determined that the address is to be accessed, the page data held in the sense amplifier 35 is accessed only by the column address.

That is, the memory address unit 60 is composed of four fields: bank, subarray, row, and column.

The bank field indicates a specific bank among a plurality of banks, which are multi-bank D-RAMs. In an embodiment, since the bank field has a size of b bits, the number of banks is ^2b . The sub-array field is the number of sub-arrays existing on one of the banks is 2 ^s dog because pointing to a particular sub-array from among a plurality of sub-arrays existing on one of the banks, by way of example gajigi the size of the s bit 2 ^s It is defined as = k.

As shown, the plurality of subarrays 37 provided in each bank includes sensing amplifiers 37 at both ends. In this case, the lowfield included in the memory address unit 60 indicates a specific row among a plurality of DRAM rows existing in an arbitrary subarray 37. In an embodiment, the lowfield is present in the subarray because it has a size of x bits. The number of furnaces is 2 ^x .

In addition, the column field included in the memory address unit 60 indicates arbitrary bit data among a plurality of bit column data existing in one DRAM row. As an embodiment, the column field includes one D RAM. Low contains 2 ^y bits.

On the other hand, the low address table 64 is used to store low addresses of memory requests having a sense amplifier 35 that still holds data among previous memory requests. Is the product of the total number of banks and the number of subarrays 37 per bank, which is defined as 2 ^{b + s} . In addition, as an embodiment, the total size of the low address stored in the low address table 64 is defined as 2 ^{b + s} x bits.

A memory access system according to the present invention configured as described above will be described by a flowchart showing a control method thereof in the memory access system of FIG.

That is, in accessing the data in the cache by the memory processor included in the CPU, a cache miss is generated, and the memory bank unit is configured based on the address information of the bank field of the memory address unit 60 generated by the cache miss. (62) is decoded. (70)

The processor then determines whether a bank conflict has occurred in which a cache miss caused by a cache miss collides with a previous cache miss.

If it is determined in step 71 that no bank collision has occurred, the subarray 37 is decoded by the address information of the subarray field in the memory address unit 60. (72)

However, if the desired bank is already processing the previous cache request, the cache request enters the request queue until the bank is free.

It waits until a cache request is not generated, i.e. until the bank is free (78). When the bank is free, it dequeues the cache request from the request queue. Next, the process returns to step 72 to decode the subarray 37 again.

When the decoding of the subarray 37 is completed as described above, the address table 64 is accessed by using the bank field and the subarray field of the decoded memory address unit 60 as index information. In this case, the table unit 64 is accessed. It compares the log address information that is with the log address information required in the generated cache request.

On the other hand, in this case, when the cache request is received, additional time is required to compare whether the same as the DRAM page data held in the sense amplifier 35. Since this time is similar to the first cache access time, it can be processed in one processor cycle according to the synchronous processing of the digital processor.

It is determined by comparing the page access success (page hit) in the comparison section 68 that the memory request already generated by the comparison is equal to the value of the log address table section 64 (74).

If the memory request compared in step 74 and the value of the log address table unit 64 are not the same, the memory device operates in a general memory access mode. That is, if they are not the same, precharge and low access are performed.

However, if it is determined that the memory request compared with the value of the low address table 64 in step 74 is the same, the operation is performed in a DRAM page access success mode (page hit mode), and accordingly, the precharge and low operations performed in step 75 are performed. Perform only column access without access. (76)

As a result, the data is withdrawn from the subarray 37 selected by the memory access that performs only column access without precharge and low access according to a comparison between the memory request and the value of the low address table 64. The time for fetching data is greatly reduced.

In addition, the present invention may operate in addition to hierarchical multi-bank DRAM. That is, each subarray may operate as a semi-independent bank, and may perform precharge delay to lower a bank collision rate and increase a DRAM page access success rate. 7 illustrates only an operation model of an embodiment based on a general bank structure.

In addition, for high cache miss rates, the number of waiting requests stored in the request queue is examined, and the success rate of DRAM page access is further increased by reordering clustering requests that have the same path. You can. However, in the case of central CPU (CPU) application with high cache success rate, the DRAM access rate is not high and the request reordering does not have much meaning because the number of requests waiting in the request queue is small.

Hereinafter, an embodiment of calculating a cache refill time in a memory access control method according to the present invention will be described. In the present invention, a memory access request or a DRAM access request are assumed to be cache needs since all memory access requests and DRAM access requests are cache systems.

In the present invention, the analytical model follows the model of M / D / 1 queuing, and when the number of requests received from the i-th DRAM bank or waiting in the request queue is N _i , N _i is represented by Equation 1 below. In a computer system architecture having a cache memory, the cache refill time T _{cache_refill} is represented by Equation 2 when the failure cost of the cache miss is defined as one cache block fill time.

At this time, the fundamental element of the data output time (T _{DRAM_access} ), which means the time when data starts to be output to the DRAM bank after the access request is sent to the DRAM bank, is divided into t _RAC and t _RP time. Here, the precharge time is t _RP , the low access time is t _RCD , the column access time is t _CAC , and the local column access time is t _RAC as the sum of t _RCD and t _CAC .

Local column access time (t _RAC ) and precharge time (t _RP ) is a factor that can not be greatly reduced by the physical characteristics of the DRAM. In recent years, new DRAMs that offer high bandwidth do not reduce physically constrained row access time (t _RCD ), column access time (t _CAC ), or precharge time (t _RP ), but rather increase access rates. For example, the continuous data access rate can be increased by using a page mode that utilizes the data of the sense amplifier, such as an FPM DRAM, an EDO DRAM, or an SD RAM, or an advanced mode based on it. Furthermore, the column cache pipeline, prefetch, and multi-bank structure are used to reduce the total cache refill time (T _{cache_refill} ).

In computer systems with on-chip DRAM, however, the page mode is not required to access one cache block. Because memory bus widths can increase to cache block sizes, new on-chip DRAM structures and mechanisms are needed.

On the other hand, the data output time (T _{DRAM_access} ) [cpu cycles], which represents a time at which data begins to be output to the DRAM bank after the access request is sent to the DRAM bank, is expressed by Equation 3 below.

When a DRAM access request arrives, it must wait until all previous requests that are already waiting for service have been serviced. Therefore, the waiting time T _pending , which means the average delay time of cache requesters waiting for service in the request queue, is represented by Equation 4.

In this case, in a general computer system having off-chip DRAM, memory access requirements are not generated by memory bus width and delay constraints, so the bank collision rate beta _i is not large and therefore is not a performance constraint. However, in a computer system having an on-chip DRAM, many memory access requests may be generated to take advantage of the increased internal memory bandwidth, and then the bank collision rate beta _i may be large, which is a performance constraint.

In addition, a high-performance computer system consisting of a non blocking memory system, a multi-issue superscalar processor, a multiprocessor, and an on-chip DRAM may generate multiple memory requirements simultaneously. The bank collision rate beta _i must be large. Therefore, a computer system having an on-chip DRAM structure can adopt a new DRAM structure that reduces the bank collision rate beta _i .

Since the sense amplifier can transmit the data corresponding to the cache block at once, if it is precharged immediately after accessing the data of the sense amplifier once, the sense amplifier of the i-th DRAM bank may already have it. The probability, ie, the DRAM page access success rate γ _i , is zero.

However, before the on-chip DRAM sense amplifier is precharged, if the desired data is included in the sense amplifier in a subsequent request, the DRAM access may be solved by the column access time t _CAC .

In addition, according to the present invention, the DRAM page access success rate γ _i has a positive value, and the data output time T _{DRAM_access} and the waiting time T _pending may be represented by Equations 5 and 6, respectively.

In addition, the overhead time (T _overhead ), which represents the sum of the time for transmitting the data output through the memory bus, the time for arbitrating the memory bus, and the time for inputting and outputting the cache request to the request queue, is expressed by Equation 7. Can be expressed.

Here, the data transfer time (t _transfer ) [cpu cycles] is the time to _transfer the data of one cache block between the DRAM bank and the primary cache through the memory bus, and the bus arbitration time (t _arb ) is the processor's memory bus. The arbitration time, buffering time (t _buf ) is the time required to buffer the data from the processor to the DRAM and the data from the DRAM to the primary cache.

The data transfer time t _transfer [cpu cycles] means a time for transferring data of one cache block through the memory bus between the DRAM bank and the primary cache.

In an embodiment, the memory bus clock frequency (F _BUS ) is assumed to be 200 MHz, such as the central control clock frequency (F _CPU ), and the memory bus width (W) [bytes] is the same as the block size of the cache because the pin restriction is eliminated in the on-chip DRAM. Design with the same size, W = L (where L is the primary cache block size [bytes]). In this design, unlike a computer system having a conventional off-chip DRAM structure, the data transfer time (t _transfer ) in the access delay time (T _{access_latency} ) becomes very small and the share of the data output time (T _{DRAM_access} ) Becomes very large. At this time, in the embodiment, the overhead time t _overhead is assumed to be 3 CPU cycles.

Therefore, the cache refill time when using the conventional DRAM access control method according to the prior art can be obtained by equations (3), (4), and (7). In the present invention, the DRAM page access success occurs for a plurality of block access requests. If so, the cache refill time can be obtained by equations (5), (6) and (7).

8 is a view illustrating a change in cache refill time according to a change in a bank collision rate and a DRAM page access success rate according to the present invention.

Here, it is assumed that the service probability α _i representing the probability that the cache required phrase is serviced in the i-th DRAM bank has the same value for all banks i. That is, as the DRAM bank collision rate increases, the DRAM access time increases exponentially. In this case, increasing the number of D-RAM banks may reduce the bank collision rate, but it requires a trade-off because it has power and area overhead.

Meanwhile, the DRAM page access success rate between a plurality of block access requests is 0 when the on-chip DRAM has an access control scheme of a general DRAM. However, when the access control scheme and the device of the present invention are used, the DRAM page access success rate is increased. Increasing DRAM access time is significantly reduced. In addition, as the DRAM page access success rate increases, the bank collision rate decreases relatively, resulting in overall performance improvement.

According to the present invention, the performance of an on-chip DRAM is improved by using a DRAM access system and a control method thereof to increase the DRAM page access success rate as expressed in the analytical model.

In FIG. 8, as an embodiment, the clock frequency (F _CPU ) of the central controller is defined as 200 MHz, the low access time t _RCD is 30 ns (6 CPU cycles), and the column access time t _CAC is 30 ns (6 CPUs). cycle), the local column access time (t _RAC ) is 60ns (12 CPU cycles), and the precharge time (t _RP ) is 30ns (6 CPU cycles).

The drawings and specification are merely exemplary of the invention, which are used for the purpose of illustrating the invention only and are not intended to limit the scope of the invention as defined in the appended claims or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention, after processing one block access request according to a cache request, any page data included in the same page data including the block data is held in the sense amplifier from the central controller. In the case where the second cache request is required for the block data, the second cache request is processed by the column access in the page data held in the sense amplifier without precharging and low access. The page access time is reduced to improve the performance of the on-chip DRAM.

Claims (4)

A memory bank unit including a subarray in which data accessed by a row and a column address are stored, and a sense amplifier temporarily stored when data is accessed from the subarray; A memory address unit including address information for accessing data stored in a predetermined subarray in the memory bank unit by control of a central controller; A low address table unit selected by address information of the memory address unit and including low address information indicating whether page data stored in any low address of the memory bank unit is retained in the detection amplifier; And If it is determined that the same address is accessed by comparing the address information included in the memory address unit with the low address table selected and output by the memory address unit, the sensing is performed by the column address only. And a comparator for accessing the page data of the amplifier. According to claim 1, Low address information of the low address table unit, And the corresponding row address information of the row address data held in the sense amplifiers of each of the banks, in the memory bank unit including at least one bank. In the memory access control method, the cache request generated from the central controller is processed by precharge, row access and column access. After processing one block access request according to the cache request, a second cache requesting any block data included in the same page data while the page data including the block data of the sense amplifier is retained. And a second cache request from the page data held by the sense amplifier by the column access when the request is generated. A memory access control method in which page data including block data is stored in a sense amplifier by precharge and low access, and cache requests are processed by column access from the page data. After processing one block access according to the cache necessity, the page data in the state in which page data including the block data is held in the sense amplifier without precharging the block data held in the sense amplifier. If a second cache request is generated that requires any block data that contains a second cache request, and a second cache request is required to request page data held by the sense amplifier, a block is generated from the page data held by the sense amplifier. Memory access control method, characterized in that the time the data is column access is calculated by the following equation. Where T _{DRAM_access} is the data output time, t _RP is the precharge time, t _RCD is the low access time, t _CAC is the column access time, t _RAC is the sum of t _RCD and t _CAC , and the local column access time, α _i is the cache. The probability that the request needs to be serviced in the i-th DRAM bank, β _i is the probability that the cache request collides with the previous request being serviced in the i-th DRAM bank, and γ _i is the required data of the i-th DRAM bank. It is the probability that the sense amplifier already holds.