KR20000061787A - Voltage controlled oscillator circuit using multi-range capacitance - Google Patents

Abstract

PURPOSE: A voltage controlling oscillator using a multi range capacitance is provided to make a size of a manufacture small and to reduce the power consumption. CONSTITUTION: A voltage controlling oscillator using a multi range capacitance includes a comparator/clock generator(53) which generates and up-clock if a tuning voltage(VT2) is larger than a reference voltage, and if not, generates a down-clock. An up/down counter(54) up-counts a switching signal when impressed with the up-clock from the comparator/clock generator(53) and down-counts a switching signal when impressed with the down-clock. A switching section(55) has at least one or more switch connect the switch which is turned on/off by a corresponding switching signal of the up/down counter(54). A capacity array(56) has at least one or more capacitor which has one end connected to the ground through each switch of the switching section(55) and the other end an output terminal of a resonance circuit. A tank circuit(51) includes a varactor diode(VD51), a fixed capacitor(C51) and a fixed inductor(L51) having a variable capacitor by the tuning voltage(VT2) of low voltage, and resonates a frequency determined by a capacitance of the varactor diode(VD51), a capacitance of the fixed capacitor(C51), an inductance of the fixed inductor(L51) and a capacitor of the capacity array(56). An oscillator(52) oscillates a resonance frequency of the tank circuit section(51). A phase-locked loop(PLL) controls the tuning voltage(VT2) according to a clock from the comparator/clock generator(53) until an oscillation frequency is phase synchronized with a predetermined frequency.

Description

VOLTAGE CONTROLLED OSCILLATOR CIRCUIT USING MULTI-RANGE CAPACITANCE}

The present invention relates to a voltage controlled oscillator, in particular, in a voltage controlled oscillator, by using the operating power of the system with the tuning voltage to cover the desired frequency band, so as to make the operating power of the system again to a high voltage As the circuit becomes unnecessary, the present invention relates to a voltage controlled oscillator using a multi-range capacitance that can reduce the size of an application and also reduce power consumption.

In general, a phase locked loop (PLL) detects a phase difference between a reference frequency and an oscillation frequency and provides a tuning voltage corresponding to the detected phase difference to phase synchronize the oscillation frequency to a desired frequency. It consists of

Referring to FIG. 1, a general phase synchronization loop includes a reference frequency oscillator 10 for oscillating a reference frequency, a reference frequency divider 20 for dividing a reference frequency of the reference frequency oscillator 10 at a set frequency, and this reference. Phase comparator 30 which compares the phase between the set frequency of the frequency divider 20 and the feedback frequency and outputs a voltage corresponding to the phase difference, and the voltage of the phase comparator 30 is converted into a DC voltage to the tuning voltage VT1. The low pass filter 40 to be provided, the voltage controlled oscillator 50 for oscillating the frequency corresponding to the tuning voltage VT1 of the low pass filter 40, and the oscillation frequency of the voltage controlled oscillator 50 are divided. It consists of a variable divider (60) provided to the phase comparator (30).

In the basic circuit of such a general phase-locked loop, the configuration of the voltage controlled oscillator 50 used in the related art is as shown in FIG. 2, and referring to FIG. 2, the conventional voltage controlled oscillator has a tuning voltage VT1. ) And a tank circuit section 51 for resonating the frequency determined by varying the capacitor, and an oscillation section 52 for oscillating the resonance frequency of the tank circuit section 51.

The tank circuit portion 51 includes a varactor diode C2 having a capacitance inversely proportional to the magnitude of the tuning voltage VT1, a fixed capacitor C2 connected in series with the varactor diode C2, and a fixed capacitor ( It consists of the inductor L1 connected in parallel to the series circuit of C1) and varactor diode C2.

The tuning voltage VT1 of the conventional voltage controlled oscillator 50 made as described above is a voltage obtained by boosting the operating power of the system, and the maximum voltage of the tuning voltage varies depending on the application, but is, for example, 33V, rather than the operating power of the system. High voltage. The varactor diode C2 included in the tank circuit unit 51 in the voltage controlled oscillator is a variable capacitance element having a capacitance-voltage characteristic as shown in FIG. 3, which has a capacitance between 0 and 33V. Since the variable capacitor device is variable, the wideband phase-locked loop (PLL) requires a tuning voltage of at least 0V to a maximum of 33V so that the varactor diode C2 is maximally variable so that the wideband phase-locked loop (PLL) is realized.

However, such a conventional voltage controlled oscillator must boost the system operating power of the applied product to 33V, so a separate booster circuit or power supply such as a DC-DC converter is required, and thus a separate booster circuit or power supply must be provided. Accordingly, there are various problems such as the limitation of the integrated circuit (IC) manufacturing process and the waste of power.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and therefore, an object of the present invention is to enable a voltage controlled oscillator to cover a desired frequency band by using an operating power supply of the system with a tuning voltage. As a separate circuit is not required to turn the operating power back to a high voltage, the present invention provides a voltage controlled oscillator using a multi-range capacitance that can reduce the size of the application and also reduce power consumption.

1 is a block diagram of a general phase locked loop.

2 is a configuration diagram of a conventional voltage controlled oscillator.

3 is a capacitance-voltage characteristic graph of varactor diodes.

4 is a configuration diagram of a voltage controlled oscillator according to the present invention.

FIG. 5 is a characteristic graph of the multi-range capacitance of FIG. 4.

FIG. 6 is a graph showing changes in the tuning voltage of FIG.

FIG. 6B is a graph of change in capacitance according to a change in tuning voltage of FIG. 6A.

Explanation of symbols on the main parts of the drawings

10: reference frequency oscillator 20: reference divider

30: phase comparator 40: low pass filter

50: voltage controlled oscillator 51: tank circuit

52: oscillation unit 53: comparator / clock generator

54: up / down counter 55: switch

56 capacitor array 60 variable divider

As a technical means for achieving the above object of the present invention, the oscillator of the present invention, in a voltage controlled oscillator using a multi-range capacitance, generates an upclock when the tuning voltage is greater than the reference voltage, and the tuning voltage is higher than the reference voltage. A comparator / clock generator that generates a down clock if small; An up / down counter from the comparator / clock generator up counting the switching signal each time an upclock is applied, while an up / down counter down counting the switching signal each time a down clock is applied; A switch unit including at least one switch, the switch being connected to be turned on / off according to a corresponding switching signal of an up / down counter; A capacitor array including at least one capacitor, one end of which is commonly connected to ground after each of the individual switches in the switch unit, and the other end of which is commonly connected to the output terminal of the resonant circuit unit; It is determined by the capacitance of the varactor diode, the capacitance of the fixed capacitor, the inductance of the fixed inductor, and the capacitor of the external capacitor array, including varactor diodes and fixed capacitors and fixed inductors whose capacitors are variable according to the low voltage tuning voltage. Tank circuit unit for resonating frequency; An oscillator for oscillating the resonant frequency of the tank circuit; A PLL for controlling the tuning voltage according to a clock output from the comparator / clock generator until the oscillation frequency is phase synchronized with the set frequency; Characterized by including.

Hereinafter, a voltage controlled oscillator using a multi-range capacitance according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a configuration diagram of a voltage controlled oscillator according to the present invention. Referring to FIG. 4, a voltage controlled oscillator using a multi-range capacitance according to the present invention generates an upclock when the tuning voltage VT2 is greater than a reference voltage. If the tuning voltage VT2 is less than the reference voltage, the comparator / clock generator 53 which generates the down clock and the uplink signal are up counted each time the up clock is applied from the comparator / clock generator 53, while the down clock is applied. An up / down counter 54 for down counting a switching signal each time, and at least one switch, wherein the switch unit 55 is connected to be turned on / off according to a corresponding switching signal of the up / down counter. A capacitor including at least one capacitor having one end connected in common to the ground through each switch in the switch unit 55 and the other end connected in common to the output terminal of the resonant circuit unit. The varistor diode VD51 includes a sheet array array 56 and a varactor diode VD51 and a fixed capacitor C51 and a fixed inductor L51 whose capacitors are variable according to the low-tuning tuning voltage VT2. Resonant frequency of the tank circuit portion 51 and the tank circuit portion 51 for resonating the frequency determined by the capacitance, the capacitance of the fixed capacitor (C51), the inductance of the fixed inductor (L51) and the capacitor of the external capacitor array 56 An oscillation unit 52 for oscillating the oscillation unit 52 and a PLL 57 for controlling the tuning voltage VT2 according to the clock output from the comparator / clock generator 53 until the oscillation frequency is phase synchronized with the set frequency.

With the tuning voltage VT2 provided to the tank circuit section 51, the operating power of the system is directly used as it is without directly boosting the operating power of the applied system through a boosting circuit such as a DC-DC converter. Can vary depending on the system specification of the application, usually low voltage below 10V, for example 4V, 5V.

The comparator / clock generator 53 presets a reference voltage therein. The reference voltage may use one reference voltage, and, as in the embodiment of the present invention, generates an upclock or a downclock. In order to make the tuning operation more quickly and precisely by setting different reference points, the reference voltage may be set to different up and down reference voltages. Is set lower than the maximum value of the tuning voltage, and the down reference voltage is set lower than the up reference voltage.

In addition, the comparator / clock generator 53 compares the tuning voltage with a preset internal reference voltage until the locking signal is input from the PLL 57, and continues to generate a corresponding clock according to the comparison result. When the locking signal is input, it becomes inoperative.

In addition, the up / down counter 54 is configured to output a switching signal composed of the number of bits corresponding to the number of switches included in the switch unit 55 by switching one switch on / off by one bit. For example, when six switches are included in the switch section 55, it is sufficient to use 6 bits as a switching signal in order to switch on / off of each switch, and the up / down counter 54 At the first upclock input from the comparator / clock generator 53, the least significant bit of the 6 bits in the switching signal is set ("1"), and then the set bit is shifted by one bit to the right in the most significant bit direction at each upclock input. On the other hand, the up / down counter 54 sets ("1") the most significant bit of the 6 bits in the switching signal at the first down clock input from the comparator / clock generator 53, and then switches at each down clock input. Constitute a set of heading bits to shift by one bit toward the least significant bit in the left direction.

The switch unit 55 includes a plurality of switches that are turned on / off according to the state of the corresponding switching bit of the switching signal output from the up / down counter 54. The switch in the switch unit 55 includes a capacitor array ( The number of capacitors included in 56 is the same as the number of switch bits of the up / down counter 54. Each switch in the switch section 55 according to the present invention is a switch which is turned on by a reset ("0") bit and turned off by a set ("1") bit. The initial state of each switch is all on.

The capacitor array 56 uses the operating power of the system as the tuning voltage VT2 to compensate for a variable range that cannot be covered by the variable of the tuning voltage, which is a plurality of switches in the switch unit 55. One end of each of which is connected one-to-one, and each other includes a plurality of capacitors connected in common to the output terminal of the resonant circuit section 51, and each of the plurality of capacitors is set to different capacitances, where a plurality of capacitors Is composed of a first capacitor C1 and a plurality of capacitors C2 to CN connected in parallel to the first capacitor C1, respectively. The magnitude | size of the capacitance of these capacitor C1-C6 is set to "C1> C2> C3> C4> C5> C6".

When the up-clock or down-clock is output from the comparator / clock generator 53, the PLL 57 resets the tuning voltage VT2 to a minimum voltage and performs a phase synchronization function.

FIG. 5 is a characteristic graph of the multi-range capacitance of FIG. 4, which shows a change in capacitance according to the tuning voltage VT2 between capacitances of a plurality of capacitors in the capacitor array 56, and FIG. 6A is a graph of the tuning voltage of FIG. 4. 6B is a change graph of capacitance according to the change in the tuning voltage of FIG. 6A.

Operation according to the voltage controlled oscillator of the present invention configured as described above will be described in detail below based on the accompanying drawings.

Conventionally, the system operating power of the applied product should be used as a tuning voltage (VT2) by boosting to a high voltage of 33V using a boost circuit such as a separate DC-DC converter or a separate circuit such as a power supply device. In order to solve various conventional problems such as manufacturing process restrictions and waste of power, the present invention is proposed. In the present invention, the operating power of the system is directly applied without increasing voltage to a high voltage such as 33V. The tuning voltage (VT2) is used to achieve the desired frequency variation.

First, the operating power of the system is used as the tuning voltage in the present invention, the operating power of this system is different to 4V, 5V, etc. according to the specification of the applied product, the present invention assumes the operating power of the system to 5V. .

Referring to FIG. 4, the PLL 57 receives the oscillation frequency from the oscillator 52 and outputs a locking signal to the comparator / clock generator 53 when there is no phase difference compared with the reference frequency, and when there is a phase difference. If the phase difference is large and the voltage corresponding to the phase difference is larger than 5V, the maximum value of the tuning voltage, the PLL 57 supplies 5V, the maximum value of the tuning voltage VT2. On the contrary, when the phase difference is large and the voltage corresponding to the phase difference is less than 0V, the minimum value of the tuning voltage, the PLL 57 provides 0V, the minimum value of the tuning voltage VT2.

In addition, the PLL 57 continuously receives the clock output from the comparator / clock generator 53 and resets the tuning voltage VT2 to 0V when the upclock or the downclock is input. To perform.

The capacitance of the varactor diode VD51 in the tank circuit portion 51 is varied by the tuning voltage VT2 provided in this way.

On the other hand, the comparator / clock generator 53 receives the tuning voltage VT2 provided from the PLL 57 and sets the tuning voltage VT2 to the up reference voltage (5V) set therein. If the voltage is lower than 5V, for example, it is larger than 4.99V, the output is upclocked when it is larger, and the tuning voltage VT2 may be set to the internally set down reference voltage (0V). If the voltage is higher than 0 V, for example, less than 0.01 V), the down clock is output to the up / down counter 54.

The up / down counter 54 provides the switching unit 55 with a switching signal B1, B2, -BN having the same number of bits as the number of capacitors in the capacitor array 56, and the initial state of the switching signal. Is the state in which all the switches in the switch unit 55 are turned on. For example, the initial state of the 6-bit switching signal is "0", and when the 1-bit state is "0" (reset), the corresponding switch is turned on. If the switch section 55 includes a switch, all six switches in the switch section 55 are on, so that all six capacitors in the capacitor array 56 are connected to the tank circuit section 51. do.

At this time, when the upclock is input to the up / down counter 54, the least significant bit in the switching signal is set (" 1 "), and the switching signal is " 100000 " Is shifted to the right side of the most significant bit direction, so the switching signal is " 10000 ". In this way, the set bit is shifted by one bit to the right every time the upclock is input.

On the other hand, if the downclock is inputted to the up / down counter 54 in the state where the switching signal is " 1 ", the switching signal becomes " 10 " since the set bit is shifted to the left in the least significant bit direction. When the downclock is inputted, the set bit is shifted outward by one bit so that the switching signal is "100". Thus, each time the downclock is input, the set bit is shifted by one bit to the left.

By such a switching signal of the up / down counter 54, one of the switches of the plurality of switches in the switch unit 55, which are all on in the initial state, is turned off, and thus the capacitor array connected to the switched off switch. The capacitor in 56 is in a non-connected state with the tank circuit portion 51.

At this time, the oscillation frequency in the present invention is determined by the tank circuit unit 51 and the capacitor array 56, the oscillation frequency (f) is determined by the following equation (1).

Here, CT1 is a combined capacitance of the capacitor C51 and the varactor diode VD51 in the tank circuit portion 51, and is (C51 * CVD) / (C51 + CVD), and CT2 is a plurality of capacitors in the capacitor array 56. It is the combined capacitance of the capacitors connected to the heavy tank circuit portion 51.

Meanwhile, the magnitude of the conventional tuning voltage VT1, the state of the switching signal of the up / down counter 54, the magnitude of the tuning voltage VT2 of the present invention, and the on / off state of each switch in the switch section 55 accordingly. Of the capacitors in the capacitor array 56, the capacitors connected to the tank circuit portion 51 and the corresponding oscillation frequency are shown in Table 1 below.

VT1 Switching signal status VT2 Switch status in the switch Capacitor Array Connection Capacitor CT2 Oscillation frequency S1 S2 S3 S4 S5 S6 5V ↓ 0 5V ↓ ON ON ON ON ON ON C1, C2, C3, C4, C5, C6 CT20 f20 10V ↓ 100000 5V ↓ OF ON ON ON ON ON C2, C3, C4, C5, C6 CT21 f21 15V ↓ 10000 5V ↓ ON OF ON ON ON ON C1, C3, C4, C5, C6 CT22 f22 20V ↓ 1000 5V ↓ ON ON OF ON ON ON C1, C2, C4, C5, C6 CT23 f23 25V ↓ 100 5V ↓ ON ON ON OF ON ON C1, C2, C3, C5, C6 CT24 f24 30V ↓ 10 5V ↓ ON ON ON ON OF ON C1, C2, C3, C4, C6 CT25 f25 35V ↓ One 5V ↓ ON ON ON ON ON OF C1, C2, C3, C4, C5 CT26 f26

In Table 1, "↓" denotes a lower voltage, and the capacitance of the plurality of capacitors in the capacitor array 56 has a relationship of "C1> C2> C3> C4> C5> C6". Since the magnitude of the combined capacitances of the capacitors in the capacitor array 56 connected to the tank circuit part 51 is in the relationship of "CT20> CT21> CT22> CT23> CT24> CT25> CT26", the magnitude of the oscillation frequency according to the present invention is eventually obtained. Becomes "f20 <f21 <f22 <f23 <f24 <f25 <f26".

As shown in Table 1, the switch in the switch unit 55 is turned on / off according to the state of the switching signal output from the up / down counter 54, and the switch in the switch unit 55 is turned on / off. As a result, the capacitor in the capacitor array 56 is connected / disconnected to the tank circuit portion 51.

Referring to Table 1, specifically, first, if the conventional tuning voltage (VT1) is 3V less than 5V, this 3V is a voltage lower than the up reference voltage in the comparator / clock generator 53, the comparator / clock generator Since the clock is not output at 53, the up / down counter 54 outputs the switching signal in the initial state, and thus the switching signal is in the " 0 " state, and the switches S1 to S6 in the switch section 55 are made. Since all of them are in an on state, all of the capacitors C1 to C6 in the capacitor array 56 are connected to the tank circuit part 51, and the oscillation frequency f20 at this time is determined as shown in Equation 1 above. Where CT1 is "(C51 * CVD) / (C51 + CVD)" and CT20 is "C1 + C2 + C3 + C4 + C5 + C6".

If the conventional tuning voltage VT1 is less than 10V and 8V, the 8V is higher than the up reference voltage in the comparator / clock generator 53, so that one upclock is output from the comparator / clock generator 53. In the / down counter 54, since the least significant bit is set ("1") in the switching signal in the initial state, the switching signal at this time is in the "100000" state, and all the switches S2 to S6 in the switch section 55 Since it is in the on state and the switch S1 is in the off state, all of the capacitors C2 to C6 in the capacitor array 56 are connected to the tank circuit portion 51, while the capacitor C1 is in the unconnected state. At this time, the oscillation frequency f21 is determined as shown in Equation 1, where CT1 is "(C51 * CVD) / (C51 + CVD)" and CT21 is "C2 + C3 + C4 + C5 + C6". "to be.

Accordingly, the PLL 57 resets to a tuning voltage of 0V and then performs a phase tuning function so that 5V of 8V corresponding to the phase difference is compensated by a capacitor in the capacitor array 56, thereby outputting a tuning voltage of 3V. .

If the conventional tuning voltage VT1 is 32V which is less than 35V, the 32V is 6 times higher than the up reference voltage in the comparator / clock generator 53, and thus the six clocks are output by the comparator / clock generator 53. Therefore, in the up / down counter 54, since the least significant bit is set ("1") in the switching signal in the initial state and the set bit is shifted to the 5 bit rounding side, the switching signal at this time is in the "1" state, Since all the switches S1 to S5 in the switch section 55 are on and the switch S6 is off, all of the capacitors C1 to C5 in the capacitor array 56 are connected to the tank circuit section 51. On the other hand, the capacitor C6 is disconnected so that the oscillation frequency f26 is determined as shown in Equation 1, where CT1 is " (C51 * CVD) / (C51 + CVD) " And CT26 is "C2 + C3 + C4 + C5 + C6".

Accordingly, the PLL 57 resets to a tuning voltage of 0V and then performs a phase tuning function so that 30V of the 32V corresponding to the phase difference is compensated by a capacitor in the capacitor array 56, thereby outputting a tuning voltage of 2V. .

The above description is for the case where the tuning voltage is greater than the up reference voltage. On the contrary, when the tuning voltage is less than the down reference voltage, the above-described operation is performed in a reverse manner to the above operation process, and a detailed description thereof will be omitted. In brief, the comparator / clock generator 53 outputs the down clock, and accordingly, the up / down counter shifts the bit set in the switching signal to the outside by one bit to turn off the corresponding switch in the switch unit 55. The off switch causes the corresponding capacitor in the capacitor array 56 to be disconnected.

As described above, in the PLL 57 of the present invention, the maximum value of the tuning voltage provided is set to the operating voltage of the system, where the voltage corresponding to the phase difference is actually a range of voltages 0V and 5V that can be output from the PLL 57. In other words, by outputting 5V or 0V, the comparator / clock generator 53 outputs an upclock or a down clock through a comparison process with the up / down reference voltage, so that the up / down counter 54 As the corresponding switch in the capacitor array is connected or disconnected by outputting a switching signal, the capacitor array compensates for the variable capacitance range that cannot be changed to the tuning voltage. Frequency variable effect using high tuning voltage can be obtained.

According to the present invention as described above, in the voltage controlled oscillator, by using the operating power of the system with the tuning voltage to cover the desired frequency band, a separate circuit is provided to make the operating power of the system again high voltage As it becomes unnecessary, there is a special effect that can reduce the size of the application and also reduce the power consumption.

The above description is only a description of one embodiment of the present invention, the present invention is capable of various changes and modifications within the scope of the configuration.

Claims (27)

In a voltage controlled oscillator using a multi-range capacitance, A comparator / clock generator 53 for generating an upclock when the tuning voltage VT2 is greater than the reference voltage and generating a down clock when the tuning voltage VT2 is less than the reference voltage; An up / down counter 54 which up counts the switching signal every time an upclock is applied from the comparator / clock generator 53, while down counting the switching signal every time a down clock is applied; A switch unit 55 including at least one switch, the switch being connected to be turned on / off according to a corresponding switching signal of an up / down counter; A capacitor array 56 including at least one capacitor, one end of which is commonly connected to ground after each of the individual switches in the switch unit 55, and the other end of which is commonly connected to the output terminal of the resonant circuit unit; Capacitance and fixed capacitor (C51) of the varactor diode (VD51), including a varactor diode (VD51), a fixed capacitor (C51) and a fixed inductor (L51), the capacitor is variable according to the tuning voltage (VT2) of the low voltage A tank circuit portion (51) for resonating the capacitance determined by the capacitance of the inductance of the fixed inductor (L51) and the capacitor of the external capacitor array (56); An oscillation unit 52 for oscillating the resonant frequency of the tank circuit unit 51; A PLL 57 for controlling the tuning voltage VT2 according to the clock output from the comparator / clock generator 53 until the oscillation frequency is in phase synchronization with the set frequency; Voltage controlled oscillator using a multi-range capacitance, characterized in that it comprises a. 2. The voltage controlled oscillator using multi-range capacitance according to claim 1, wherein the maximum value of the tuning voltage VT2 provided to the tank circuit section 51 is set as an operating power source of the system. 2. The voltage controlled oscillator using multi-range capacitance according to claim 1, wherein the reference voltage of the comparator / clock generator is set to be equal to or less than a maximum value of the tuning voltage VT2. The voltage control using the multi-range capacitance according to claim 1, wherein the comparator / clock generator 53 is in an operating state until the locking signal is input from the PLL 57, and is in an inoperative state when the locking signal is input. oscillator. The PLL 57 performs a phase synchronization function after resetting the tuning voltage VT2 to a minimum voltage when the upclock is output from the comparator / clock generator 53 and the comparator / clock generator 53. When the down clock is output from the voltage controlled oscillator using a multi-range capacitance characterized in that to perform the phase synchronization function after resetting the tuning voltage (VT2) to the minimum voltage. In a voltage controlled oscillator using a multi-range capacitance, A comparator / clock generator 53 for generating an upclock when the tuning voltage VT2 is greater than the up reference voltage and generating a down clock when the tuning voltage VT2 is less than the down reference voltage; An up / down counter 54 which up counts the switching signal every time an upclock is applied from the comparator / clock generator 53, while down counting the switching signal every time a down clock is applied; A switch unit 55 including at least one switch, the switch being connected to be turned on / off according to a corresponding switching signal of an up / down counter; A capacitor array 56 including at least one capacitor, one end of which is commonly connected to ground after each of the individual switches in the switch unit 55, and the other end of which is commonly connected to the output terminal of the resonant circuit unit; Capacitance and fixed capacitor (C51) of the varactor diode (VD51), including a varactor diode (VD51), a fixed capacitor (C51) and a fixed inductor (L51), the capacitor is variable according to the tuning voltage (VT2) of the low voltage A tank circuit portion (51) for resonating the capacitance determined by the capacitance of the inductance of the fixed inductor (L51) and the capacitor of the external capacitor array (56); An oscillation unit 52 for oscillating the resonant frequency of the tank circuit unit 51; A PLL 57 for controlling the tuning voltage VT2 according to the clock output from the comparator / clock generator 53 until the oscillation frequency is in phase synchronization with the set frequency; Voltage controlled oscillator using a multi-range capacitance, characterized in that it comprises a. 7. The voltage controlled oscillator using multi-range capacitance according to claim 6, wherein the maximum value of the tuning voltage VT2 provided to the tank circuit section 51 is set as an operating power source of the system. 7. The voltage control using the multi-range capacitance according to claim 6, wherein the up reference voltage of the comparator / clock generator 53 is set lower than the maximum value of the tuning voltage and the down up reference voltage is set lower than the up reference voltage. oscillator. 7. The voltage control using the multi-range capacitance according to claim 6, wherein the comparator / clock generator 53 is in an operating state until the locking signal is input from the PLL 57, and is inoperative when the locking signal is input. oscillator. The apparatus of claim 6, wherein the up / down counter 54 switches one switch on and off by one bit so as to output a switching signal having a number of bits corresponding to the number of switches included in the switch unit 55. A voltage controlled oscillator using a multi-range capacitance. 7. The up / down counter 54 sets the least significant bit of the switching signal (" 1 ") at the first upclock input from the comparator / clock generator 53, and thereafter is set at every upclock input. Shifts the bits by one bit to the right in the most significant bit direction, and also shifts the set bits of the switching signal by one bit to the left in the least significant bit direction every time the downclock is input from the comparator / clock generator 53; Voltage controlled oscillator using multi-range capacitance. 7. The voltage controlled oscillator using the multi-range capacitance according to claim 6, wherein the switch unit 55 includes a plurality of switches which are turned on or off according to the state of the corresponding switching bit of the switching signal of the up / down counter 54. . The capacitor array 56 includes a plurality of capacitors, one end of which is connected to each of the plurality of switches in the switch unit 55 one-to-one, and the other end of which is commonly connected to the output terminal of the resonant circuit unit 51. Voltage controlled oscillator using a multi-range capacitance characterized in that it comprises. 15. The voltage controlled oscillator using multi-range capacitance according to claim 13, wherein each of the plurality of capacitors in the capacitor array (56) is set to different capacitances. 14. The capacitor of claim 13, wherein the plurality of capacitors in the capacitor array 56 have a first capacitor C1 set to a capacitance smaller than the maximum capacitance of the varactor diode VD51, and the capacitance of the first capacitor C1. A voltage controlled oscillator using a multi-range capacitance, characterized in that it comprises a plurality of capacitors (C2 to CN) set to a large capacitance step by step as the maximum capacitance of the varactor diode (VD51). The PLL 57 performs a phase synchronization function after resetting the tuning voltage VT2 to a minimum voltage when the upclock is output from the comparator / clock generator 53. When the down clock is output from the voltage controlled oscillator using a multi-range capacitance characterized in that to perform the phase synchronization function after resetting the tuning voltage (VT2) to the minimum voltage. In a voltage controlled oscillator using a multi-range capacitance, A comparator / clock generator 53 for generating an upclock when the tuning voltage VT2 is greater than the reference voltage and generating a down clock when the tuning voltage VT2 is less than the reference voltage; An up / down counter 54 which up counts the switching signal every time an upclock is applied from the comparator / clock generator 53, while down counting the switching signal every time a down clock is applied; A switch unit 55 including a plurality of switches, the switches being connected to be turned on / off according to a corresponding switching signal of an up / down counter; A capacitor array 56 including a plurality of capacitors, one end of which is commonly connected to ground after each of the individual switches in the switch unit 55, and the other end of which is commonly connected to the output terminal of the resonant circuit unit; Capacitance and fixed capacitor (C51) of the varactor diode (VD51), including a varactor diode (VD51), a fixed capacitor (C51) and a fixed inductor (L51), the capacitor is variable according to the tuning voltage (VT2) of the low voltage A tank circuit portion (51) for resonating the capacitance determined by the capacitance of the inductance of the fixed inductor (L51) and the capacitor of the external capacitor array (56); An oscillation unit 52 for oscillating the resonant frequency of the tank circuit unit 51; A PLL 57 for controlling the tuning voltage VT2 according to the clock output from the comparator / clock generator 53 until the oscillation frequency is in phase synchronization with the set frequency; Voltage controlled oscillator using a multi-range capacitance, characterized in that it comprises a. 18. The voltage controlled oscillator using a multi-range capacitance according to claim 17, wherein a maximum value of the tuning voltage VT2 provided to the tank circuit section 51 is set as an operating power source of the system. 18. The voltage controlled oscillator using multi-range capacitance according to claim 17, wherein the reference voltage of the comparator / clock generator is set to different up reference voltages and down reference voltages. 19. The voltage control using the multi-range capacitance according to claim 18, wherein the up reference voltage of the comparator / clock generator 53 is set lower than the maximum value of the tuning voltage and the down up reference voltage is set lower than the up reference voltage. oscillator. 18. The voltage control using the multi-range capacitance according to claim 17, wherein the comparator / clock generator 53 is in an operating state until the locking signal is input from the PLL 57, and is inoperative when the locking signal is input. oscillator. 18. The apparatus of claim 17, wherein the up / down counter 54 outputs a switching signal composed of the number of bits corresponding to the number of switches included in the switch unit 55 by switching one switch on and off by one bit. A voltage controlled oscillator using a multi-range capacitance. 23. The apparatus according to claim 17 or 22, wherein the up / down counter 54 sets ("1") the least significant bit of the switching signal upon initial upclock input from the comparator / clock generator 53, and then the up clock input. Shifts the set bit every hour by one bit to the right in the most significant bit direction, and shifts the set bit of the switching signal by one bit to the left in the least significant bit direction every time the downclock is input from the comparator / clock generator 53. Voltage controlled oscillator using a multi-range capacitance characterized in that. 18. The voltage controlled oscillator using the multi-range capacitance according to claim 17, wherein the switch unit 55 includes a plurality of switches which are turned on or off according to a corresponding switching bit state of the switching signal of the up / down counter 54. . 18. The capacitor array 56 includes a plurality of capacitors, one end of which is connected one-to-one to each of the plurality of switches in the switch unit 55, and the other end of which is connected to the output terminal of the resonant circuit unit 51 in common. Voltage controlled oscillator using a multi-range capacitance characterized in that it comprises. 27. The capacitor of claim 25, wherein the plurality of capacitors in the capacitor array 56 have a first capacitor C1 set to a capacitance smaller than the maximum capacitance of the varactor diode VD51, and the capacitance of the first capacitor C1. A voltage controlled oscillator using a multi-range capacitance, characterized in that it comprises a plurality of capacitors (C2 to CN) set to a large capacitance step by step as the maximum capacitance of the varactor diode (VD51). 18. The PLL (57) according to claim 17, wherein the PLL (57) performs a phase synchronization function after resetting the tuning voltage (VT2) to the minimum voltage when the upclock is output from the comparator / clock generator 53, the comparator / clock generator 53 When the down clock is output from the voltage controlled oscillator using a multi-range capacitance characterized in that to perform the phase synchronization function after resetting the tuning voltage (VT2) to the minimum voltage.