KR20000061690A - Memory module using a failed die stack type components - Google Patents

Abstract

PURPOSE: A memory module is to be constructed to use one good chip if a die stack-typed memory component has a bad chip and a good chip, thereby reducing an economical loss. CONSTITUTION: A memory module comprises a substrate(300) having a pattern for a memory module construction, a number of die stack-typed memory component(302), a tab(308) for an external connection provided on end of the substrate, a chip selection signal line controller(306) capable of altering a chip selection signal line in the pattern of the substrate, and a register chip(310) for adjusting a waveform of a signal transferred between the controller and the tab or for carrying out a function of a buffer to the signal. The die stack-typed memory component is mounted on the substrate with a bad chip being positioned above a good chip. The selection of the upper or lower chip is carried out by controlling a signal applied to a pin. The pin serves as a function of a chip selection by transferring a signal from a particular component to the pin.

Description

Memory module using a failed die stack type components}

The present invention relates to a semiconductor device, and more particularly to a semiconductor memory module (Memory Module).

A semiconductor module is formed by mounting several components or devices having regularity and separation on a printed circuit board (PCB). Refers to a semiconductor device that is considered to be a single component unit that performs a given function. In other words, if the unit of the component of the circuit is a bundle of standardized components instead of one component, the assembly of an electronic device such as a personal computer is further simplified. It also helps a lot in automation. After the modular parts are assembled, the functional parts are finally inspected by performing electrical inspection. When the components mounted on the printed circuit board of the semiconductor module are memory devices such as DRAM and SRAM, this is called a memory module.

As a component for such a memory module, a general memory device in which one chip is mounted in one semiconductor package is used. However, in order to improve the degree of integration in the memory module, one semiconductor package is used. A die stack type memory component in which two chips are mounted inside, and a package stack type memory component in which two semiconductor packages are attached to one semiconductor package are also used. When two chips or semiconductor packages are put together in this way, it is only possible that the memory capacity and pin configuration match exactly each other. The current package stack type memory component is a die stack type memory component which is advantageous in terms of cost and replacement because it is expensive to manufacture when processed in the form of a memory module and it is relatively difficult to replace when one individual memory component is defective. This is the preferred situation.

However, the memory module using the die stack type or the package stack type component according to the related art described above, if any one of two memory components is defective in an electrical test, the other one is a good product. And had to discard it. This is an unavoidable reality for stackable memory components that combine two into one, resulting in economic losses overall.

The technical problem to be achieved by the present invention is to reduce the economic loss by configuring a memory module having a half capacity by using one chip, which is the other good product, even if one chip is defective in the die stack type memory component. The present invention provides a memory module using a defective die stack type memory component.

1 is a schematic diagram illustrating a structure and a pin configuration of a general die stack type memory component.

2 is a cross-sectional view for explaining the structure of a memory module using a die stack type memory component.

3 is a plan view of a memory module using a defective die stack memory component according to the present invention;

4 is a rear view of the memory module using the defective die stack memory component according to the present invention.

Explanation of symbols on the main parts of the drawings

300: printed circuit board for module, 302: defective die stack memory component,

306: chip select signal line controller, 308: tab for external connection,

310: register, 312: pattern of the printed circuit board.

In order to achieve the above technical problem, the present invention provides a printed circuit board having a pattern for configuring a memory module, and a plurality of die stack type memory mounted on the printed circuit board and having one of upper and lower defects. A chip selection signal line controller for changing a chip selection (CS) signal line in a component, a tab for external connection formed in one end of the printed circuit board, and a pattern formed in the printed circuit board. It provides a memory module using a defective die-stack memory component, characterized in that it comprises a.

According to a preferred embodiment of the present invention, the chip selection (CS) signal line controller is configured to selectively use only one chip that is good from two components stacked in the plurality of defective die stack memory components. Suitable.

Preferably, the memory module using the defective die stack type memory component may process a waveform of a signal transmitted between the chip select signal line controller and an external connection tab, or perform a buffer function on the signal. It is appropriate to have a register chip that can register.

According to the present invention, even if a defect occurs in one chip in a die stack type memory component, the chip select signal line controller is adjusted in a memory module configuration printed circuit board (PCB), thereby reusing a defective die stack type memory component. Therefore, by processing into a memory module having a capacity of half, manufacturing cost can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram illustrating a structure and a pin configuration of a general die stack type memory component.

Referring to FIG. 1, a cross-sectional view of a die stack type memory component 100, a package stack type memory component 110, and a semiconductor device 120 in which one chip is mounted on a general package is illustrated. In the drawings, reference numeral 102 denotes a chip, and 104 denotes an external lead in a memory component, respectively. Each of the memory components shown in the figure has a total of 54 external leads, and the function of each pin is shown in the table below.

In the pin configuration shown in the table, AN (N = 1, 2, 3 ..., integer) indicates an address line, and DQN indicates a data in / out line. VCC refers to the power line, VSS refers to the ground line, CASB refers to the column address strobe, RASB refers to the row address strobe, and CSB (0,1) refers to the chip. Point to each selection line. And N. C is an abbreviation for No Connection.

In this case, pins 15 and 19 are pins that perform a function of a chip select line, and send a signal to a plurality of memory components to select a specific memory component. This select signal is enabled by sending a '0' signal to the CSB pin. At this time, the pin 15 CSB (1) is N. C which is not used in a normal device in which one chip is mounted in one package, such as a package stack or a die stack Only memory components are used for chip selection. In other words, by sending a signal here, one of two chips or a package can be selected.

2 is a cross-sectional view illustrating the structure of a memory module using a die stack type memory component.

Referring to FIG. 2, a total of 18 memory components 202 are mounted by soldering on a printed circuit board (PCB) 200 having a memory configuration pattern, each of which is nine on the upper and lower surfaces. Reference numeral 204 is used. Refers to the external lead of the memory component. Each memory component 202 in the figure is a die stack memory component such as 100 of FIG. 1, although not shown therein. In the prior art, if any one of the two chips included in the die stack type memory component 202 is defective, it is completely disposed of. However, in the present invention, by modifying the pattern of the printed circuit board 200 to further configure the selection means (option), a memory module having a capacity of about half can be formed by collecting the die stack type memory component 202 having a defect separately. have.

3 is a plan view of a memory module using a defective die stack memory component according to the present invention.

Referring to FIG. 3, the configuration of a memory module using a defective die stack type memory component according to the present invention includes (a) a printed circuit board 300 having a pattern for configuring the memory module, and (b) the printed circuit. A plurality of die stack type memory components 302 mounted on the substrate 300 and defective in one of the upper and lower portions, and (c) a pattern form formed at one end of the printed circuit board 300. Chip selection signal line control unit 306 and (e) chip selection signal for changing the chip selection (CS) signal line in a pattern configured on the external connection tab 308 of the printed circuit board 300 and (d) A register chip 310 may be used to process a waveform of a signal transferred between the line controller 306 and the external connection tab 308 or to perform a buffer function on the signal.

Here, in the printed circuit board 300 for constructing the memory module, the die stack type memory component may be mounted only with a defect occurring at an upper end and a good lower end. At this time, CS0 and CS2 of the figure is a pin (pin) corresponding to the pins CSB0,1 shown in Figure 2, by adjusting the signal is applied to select any one of the top or bottom chip in the die-stack memory component 302. Decide if

In this case, when '1 (high)' is applied to CS0 and '0 (low)' is applied to CS2, the chip at the bottom of the die stack memory component 302 is selected and the top is not used. Conversely, when applying '0 (low)' to CS0 and '1 (high)' to CS2, the chip at the top of the die stack type memory component 302 is selected and the bottom is not used.

Accordingly, in the die stack memory component 302, the pattern 312 connected to CS0 reaches the chip select line controller 306 to use only the bottom chip. And ?? is connected to the pattern corresponding to the VCC of the external connection tab 308 to maintain a '1 (high) state, and the pattern 312 connected to the CS2 comes to the chip select line controller 306 ?? And through the register 310 is connected to the pattern corresponding to the CS0 'and CS2' of the external connection tap 308 through the register '0 (low)' is applied to the outside from here. At this time, ??, ?? and ??, ?? are connected by using 0Ω resistor.

Therefore, the die stack memory component is used stably only at the lower end, and since the half of the die stack memory component cannot be used, the capacity of the memory module is also reduced by half.

4 is a rear view of the memory module using the defective die stack type memory component according to the present invention.

Referring to FIG. 4, the top side of the memory module illustrated in FIG. 3 has been described so that only the bottom thereof can be used. In FIG. 4, only the top thereof is described. First, a die stack type memory component 302 which can use only an upper end of the printed circuit board 300 is mounted, and the chip select line controller 306 is adjusted. This adjustment is the result of the pattern 312 coming from CS0. And ?? It is connected by using the 0Ω resistor of the portion and is connected to CS0 'and CS2' of the external connection tap 308 through the resistor 310. And pattern 312 emerging from CS2 is shown in FIG. And ?? By connecting to the VCC of the tab 308 for external connection.

The invention can be practiced in other ways without departing from its spirit and essential features. For example, in the above-described preferred embodiment, the memory component will be mainly described as a die stack type memory component, but it can be inferred from FIG. 1 that it can be applied to a package stack type memory component as it is. Therefore, in the above embodiment, the die stack memory component may be the same as the package stack memory component. 3 and 4 exemplarily illustrate that only the bottom of the die stack type memory module can be used on the top side of the memory module, and only the top side on the back side of the memory module. Although it can be used as an example, it can be rearranged in any other way by changing the design of the chip select line controller. Therefore, the content described in the preferred embodiment so far is illustrative and not intended to be limiting.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

Therefore, according to the present invention described above, even if a defect occurs in one chip in the die stack type memory component, the chip select signal line control unit is adjusted in the memory module configuration printed circuit board (PCB) without a defect. Manufacturing costs can be reduced by reusing parts and processing into half-size memory modules.

Claims (3)

A printed circuit board having a pattern for configuring a memory module; A plurality of die stack type memory components mounted on the printed circuit board and having one of upper and lower defects; A tab for external connection in a pattern form formed at one end of the printed circuit board; And a chip select signal line controller for changing a chip select signal line in a pattern formed on the printed circuit board. The method of claim 1, The chip selection (CS) signal line controller may be configured to selectively use only one chip that is good in two components stacked in the plurality of defective die stack memory components. Memory module using parts. The method of claim 1, The memory module using the defective die stack type memory component may process a waveform of a signal transferred between the chip select signal line controller and an external connection tab, or may perform a buffer function on the signal. register) A memory module using a defective die stack memory component, characterized by further comprising a chip.