KR20000061504A - Layout of eeprom cell having single poly and manufacturing method the same - Google Patents

Abstract

PURPOSE: An EEPROM cell layout and method for fabricating an EEPROM cell are to prevent a bottleneck of a poly when a cell size is decreased. CONSTITUTION: A method for manufacturing an EEPROM cell having a select transistor connected to a word line(102b) and a sense transistor connected to a sense line(100b) comprises the steps of: defining an active region(100a) and an inactive region(104) of a semiconductor substrate; forming a first insulating film on the semiconductor substrate; etching the first insulating film on the inactive region; ion implanting to form a first conductive region on the active region; etching the first insulating film by using a tunnel region(101) forming mask; forming an oxide film at the tunnel region with the first insulating film etched therefrom; forming a conductive film on the whole surface of the semiconductor substrate; etching the conductive film by using the word line and the sense line forming mask; forming a high pressure junction region on the active region; and ion implanting to form second and third conductive regions at the high pressure junction region.

Description

LAYOUT OF EEPROM CELL HAVING SINGLE POLY AND MANUFACTURING METHOD THE SAME

The present invention relates to an EEPROM, and more particularly to an EEPROM cell having a single polysilicon.

A single poly electrically erasable programmable read only memory (EEPROM) cell is a nonvolatile memory cell that uses a single layer of poly, unlike a stack gate EEPROM (two stacks).

The table below shows the operating conditions according to the mode of a single poly EEPROM.

bit line word line sense line source bulk program Vpp Vpp GND floating GND elimination GND Vpp Vpp GND GND Reading 1V3V 1V5V 0.5V2V GND GND

1 is a circuit diagram illustrating an EEPROM cell, and FIG. 2 is an EEPROM cell layout of FIG. 1.

2, select transistors having a gate connected to a word line WL 2b in common are connected to a bit line BL and a ground GND, respectively. A sense transistor M12 is connected between the selection transistors M11 and M13, the gate of which is connected to the sense line SL via a capacitor Ca. The poly 2a is disposed on the sense line 1b and some are arranged like 2c in the shape of an outlet on the active area.

Referring again to FIG. 2, the active and inactive regions are defined as 1a and 5. The memory cell is a single poly and has a large single cell size and is formed long in left and right directions. This is because the active region 1a is arranged in a U shape along the line B with respect to A.

A single poly EEPROM cell having the layout as described above is composed of three transistors, and the size of the memory cell is limited in the vertical direction of the memory cell as the active region is arranged in a U shape. Thus, poly EEPROM cells have increased left and right poly length on select lines to achieve high coupling ratios. However, two passes of the poly, i.e., the pass and the write pass of the sense transistor, serve as a bottle neck when the cell size decreases in the vertical direction.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide an EEPROM cell layout for preventing the bottleneck of poly when the cell size is reduced.

1 is a circuit diagram showing a single EEPROM cell according to the prior art;

2 is a single poly EEPROM cell layout according to the prior art;

3 is a single poly EEPROM cell layout in accordance with the present invention;

4 is a circuit diagram showing a single poly EEPROM cell in accordance with the present invention;

5 is an enlarged view of a portion of FIG. 3;

6A-6G are flow charts illustrating the EEPROM cell process sequentially by cutting FIG. 3 along line AA ′;

7A through 7H are flowcharts sequentially illustrating an EEPROM cell process along the line BB ′ of FIG. 3.

* Description of the symbols for the main parts of the drawings *

100a: active area 101: tunnel area

102a, 102b: Poly 104: inactive area

According to a feature of the present invention for achieving the object of the present invention as described above, the single poly EEPROM cell layout is arranged in the first direction on the active region having a straight shape in the first direction, and the active A word line disposed in a second direction perpendicular to the first direction on the region, a sensing line disposed outside the active region and a poly line disposed in a first direction on the sensing line and disposed in a second direction on the active region And a tunnel region formed below the poly region crossing the active region.

(Action)

According to the present invention, as the active region is formed in a straight line, the poly length on the cell size reduction detection line can be increased up and down, and the number of cell transistors can be reduced to two.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 7.

Referring to FIG. 3, the novel single poly EEPROM cell according to the embodiment of the present invention may prevent the poly from being bottleneck even if the cell size is decreased in the vertical direction due to the date deformation of the active region.

3 is a single poly EEPROM cell layout in accordance with the present invention.

Referring to FIG. 3, the active region 100a is changed from a conventional U-shape to a straight line. The word line 102b is disposed in the non-active region 104 in the same direction as the active region 100a and has a region C intersecting with the active region 100a. The poly 102a has an area crossing the sensing line 100b disposed in the same longitudinal direction as the sensing line, and an area crossing the active area is disposed in the horizontal direction. And tunnel region 101 is formed under poly 102a that intersects with active region 100a.

4 is a circuit diagram illustrating a single poly EEPROM cell in accordance with the present invention.

Referring to FIG. 4, the select transistor M1 and the sense transistor M2 are connected in series. The gate of the select transistor M1 is connected to the word line WL, and the gate of the sense transistor M2 is connected to the sense line SL through the capacitor Ca.

5 is an enlarged layout of a portion of FIG. 3.

6A through 6H are flowcharts sequentially illustrating the EEPROM cell process by cutting FIG. 5 in the direction of A-A ', and FIGS. 7A through 7H are flowcharts sequentially illustrating the EEPROM cell process by cutting FIG. 5 in the direction of B-B'.

6A and 7A, an active region and an inactive region 12 of the semiconductor substrate 10 are defined. An insulating film 14 is formed on the active region of the substrate 10. The insulating film 14 is formed as an oxide film or SiO ₂ with a thickness of 300 kPa to 500 kPa.

6B and 7B, a first photoresist film is formed on the entire surface of the substrate 10, and a first photoresist pattern 16 on an inactive region is formed through a photolithography process. N + conductive regions 18 are formed on the substrate through the first ion implantation process. The conductive regions become a tunnel oxide lower portion and a sensing line.

6C and 7C, after the first photoresist pattern 16 is removed, a second photoresist layer 20 is formed on the entire surface of the substrate including the insulating layer 14, and the photolithography process is performed. Through the second photoresist pattern 20 is formed. The insulating film 14 in the tunnel region is selectively etched using the second photoresist pattern 20 as a mask.

6D and 7D, after the second photoresist pattern 20 is removed, an oxide film is formed on the entire surface of the substrate 10 including the insulating layer 14. The oxide film 22 in the tunnel region is formed with a thickness of 50 kPa to 90 kPa as SiO ₂ or SiON.

6E and 7E, the conductive film 24 is formed on the entire surface of the semiconductor substrate 10.

Next, referring to FIGS. 6F and 7F, a third photoresist pattern 26 for forming the selection transistor M1 and the sensing transistor M2 is formed on the conductive film 24. The conductive layer 24 is etched using the third photoresist pattern 26 as a mask. Then a high voltage implant is performed to form a high voltage junction region 28 in the active region of the substrate 10.

6G and 7G, after the third photoresist pattern 26 is removed, a fourth photoresist pattern 30 is formed. The source and the drain 34 are formed in the substrate 10 by the second ion implantation process. The source and drain have a double junction structure of 28 and 32 by two injection processes.

Referring to FIG. 7H, after the fourth photoresist pattern 30 is removed, a word line, a bit line, and a common source line (101 in FIG. 3) are formed.

As mentioned above, a single poly EEPROM cell integrates two passes of poly into one and changes the active area to a straight line so that it is less susceptible to poly D / R at cell size reduction. In addition, since the poly on the sense line can be increased up and down, the memory cell size can be reduced left and right. In addition, since the number of cell transistors is reduced from three to two, the cell size can be further reduced.

According to the present invention as described above, the bottleneck of poly can be prevented by changing the active area of a single poly EEPROM cell to a straight line.

Further, according to the present invention, there is an effect that the cell size can be reduced while reducing the number of cell transistors in the EEPROM.

Claims (3)

A method of manufacturing an EEPROM cell having a select transistor connected to a word line and a sense transistor connected to a sense line, the method comprising: Defining active and inactive regions of the semiconductor substrate; Forming a first insulating film on the semiconductor substrate; Etching the first insulating film on the inactive region; Performing first ion implantation to form a first conductive region in said active region; Etching the first insulating layer using a mask for forming a tunnel region; Forming an oxide film in the tunnel region in which the first insulating film is etched; Forming a conductive film on the entire surface of the semiconductor substrate; Etching the conductive layer using a mask for forming a word line and a sense line; Forming a high voltage junction region in said active region; And And implanting a second ion to form second and third conductive regions in said high voltage junction region. The method of claim 1, And the second and third conductive regions have a double junction structure as source and drain regions. An active region having a straight shape in a first direction; A word line disposed in the first direction on the inactive region and disposed in a second direction perpendicular to the first direction on the active region; A sensing line disposed outside the active area; A poly region disposed on the sense line in a first direction and disposed on the active region in a second direction; And An EEPROM cell layout comprising a tunnel region disposed below a poly region intersecting the active region.