KR20000061322A - Manufacturing method for mos transistor - Google Patents
Manufacturing method for mos transistor Download PDFInfo
- Publication number
- KR20000061322A KR20000061322A KR1019990010279A KR19990010279A KR20000061322A KR 20000061322 A KR20000061322 A KR 20000061322A KR 1019990010279 A KR1019990010279 A KR 1019990010279A KR 19990010279 A KR19990010279 A KR 19990010279A KR 20000061322 A KR20000061322 A KR 20000061322A
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- forming
- film
- reoxidation
- substrate
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000010405 reoxidation reaction Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 5
- 230000002265 prevention Effects 0.000 claims description 5
- 238000002347 injection Methods 0.000 abstract 4
- 239000007924 injection Substances 0.000 abstract 4
- 238000001704 evaporation Methods 0.000 abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 2
- 150000004706 metal oxides Chemical class 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 230000000903 blocking effect Effects 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 모스 트랜지스터 제조방법에 관한 것으로, 특히 재산화막(RE-OXIDE)를 할로이온주입에 의해 손상되는 것을 방지하는데 적당하도록 한 모스 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor fabrication method, and more particularly, to a MOS transistor fabrication method suitable for preventing damage of reoxidation film (RE-OXIDE) by halo ion implantation.
도1a 내지 도1d는 종래 모스 트랜지스터의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)에 필드산화막(2)을 형성하여 소자형성영역을 정의하고, 그 소자형성영역의 상부에 게이트산화막(3)을 증착하고, 그 게이트산화막(3)의 중앙상부에 게이트전극(4)과 그 게이트전극(4)의 상부에 캡산화막(5)을 형성하는 단계(도1a)와; 상기 게이트전극(4)의 측면 및 노출된 게이트산화막(3)의 상부에 재산화막(6)을 형성하고, 경사이온주입을 통해 상기 게이트전극(4)의 측면 기판(1) 하부에 할로방지영역(7)을 형성하는 단계(도1b)와; 상기 캡산화막(5)을 이온주입마스크로 사용하는 불순물 이온주입공정으로 상기 게이트전극(4)의 측면 기판하부에 저농도 소스 및 드레인(8)을 형성하는 단계(도1c)와; 상기 캡산화막(5)과 재산화막(6)의 측면에 측벽(9)을 형성하고, 그 측벽(9)과 캡산화막(5)을 이온주입마스크로 사용하는 이온주입공정으로 불순물 이온을 주입하여 상기 측벽(9)의 측면 기판(1) 하부에 고농도 소스 및 드레인(10)을 형성하는 단계(도1d)로 구성된다.1A to 1D are cross-sectional views of a manufacturing process of a conventional MOS transistor, in which a field oxide film 2 is formed on a substrate 1 to define an element formation region, and a gate oxide layer on the element formation region. (3) depositing a gate electrode 4 on the center of the gate oxide film 3 and forming a cap oxide film 5 on the gate electrode 4 (FIG. 1A); A reoxidation film 6 is formed on the side of the gate electrode 4 and on the exposed gate oxide film 3, and the halo prevention region under the side substrate 1 of the gate electrode 4 through the inclination ion implantation. (7) forming (FIG. 1B); Forming a low concentration source and drain 8 under the side substrate of the gate electrode 4 by an impurity ion implantation process using the cap oxide film 5 as an ion implantation mask (FIG. 1C); Sidewalls 9 are formed on the side surfaces of the cap oxide film 5 and the reoxidation film 6, and impurity ions are implanted by an ion implantation process using the side wall 9 and the cap oxide film 5 as an ion implantation mask. Forming a high concentration source and drain 10 under the side substrate 1 of the side wall 9 (Fig. 1D).
이하, 상기와 같은 종래 모스 트랜지스터 제조방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a conventional method for manufacturing a MOS transistor as described above will be described in detail with reference to the accompanying drawings.
먼저, 도1a에 도시한 바와 같이 기판(1)에 필드산화막(2)을 형성하여, 노출된 기판(1)인 소자형성영역을 정의하고, 그 소자형성영역인 기판(1)의 상부에 게이트산화막(3)을 증착한다.First, as shown in FIG. 1A, a field oxide film 2 is formed on a substrate 1 to define an element formation region that is an exposed substrate 1, and a gate is formed on the substrate 1 that is an element formation region. The oxide film 3 is deposited.
그 다음, 상기 게이트산화막(3)과 필드산화막(2)의 상부전면에 다결정실리콘과 산화막을 순차적으로 증착하고, 사진식각공정을 통해 패터닝하여 상기 게이트산화막(3)의 중앙상부에 위치하며, 상부의 캡산화막(5)에 의해 보호되는 게이트전극(4)을 형성한다.Next, polycrystalline silicon and an oxide film are sequentially deposited on the upper surfaces of the gate oxide film 3 and the field oxide film 2, and patterned by a photolithography process to be positioned on the center of the gate oxide film 3. The gate electrode 4 protected by the cap oxide film 5 is formed.
그 다음, 도1b에 도시한 바와 같이 상기 다결정실리콘인 게이트전극(4)을 산화시켜 재산화막(6)을 형성하여, 상기 게이트전극(4)을 형성하기 위한 식각공정으로 그 게이트전극(4)의 측면부가 손상된 것을 복원하게 된다.Next, as shown in FIG. 1B, the gate electrode 4, which is the polysilicon, is oxidized to form a reoxidation film 6, and the gate electrode 4 is etched to form the gate electrode 4. The side portion of the will restore the damaged.
그 다음, 경사이온주입을 통해 상기 게이트전극(4)의 측면 기판하부 및 그 게이트전극(4)의 하부일부영역의 기판하부에 할로방지영역(7)을 형성한다.Next, a halo prevention region 7 is formed under the side substrate of the gate electrode 4 and under the substrate of the lower portion of the gate electrode 4 by the inclination ion implantation.
이때, 상기 경사이온주입에 의해 상기 형성한 재산화막(6)에도 이온이 주입 또는 충돌하여 그 재산화막(6) 및 게이트전극(4)의 측면부가 손상된다.At this time, ions are also implanted or collided with the formed reoxidation film 6 by the inclined ion implantation, and the side surfaces of the reoxidation film 6 and the gate electrode 4 are damaged.
그 다음, 도1c에 도시한 바와 같이 상기 캡산화막(5)을 이온주입마스크로 사용하는 이온주입공정으로 불순물 이온을 주입하여 상기 게이트전극(4)의 측면 기판(1) 하부에 저농도 소스 및 드레인(8)을 형성한다.Subsequently, as shown in FIG. 1C, impurity ions are implanted in an ion implantation process using the cap oxide film 5 as an ion implantation mask, so that a low concentration source and drain is disposed below the side substrate 1 of the gate electrode 4. (8) is formed.
이어서, 도1d에 도시한 바와 같이 상기 도1c의 구조 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 캡산화막(5)과 재산화막(6)의 측면에 측벽(9)을 형성하고, 불순물 이온을 이온주입하여 상기 측벽(9)의 측면 기판하부에 고농도 소스 및 드레인(10)을 형성한다.Subsequently, as shown in FIG. 1D, an insulating film is deposited on the entire upper surface of the structure of FIG. 1C, and the sidewall 9 is formed on the side surfaces of the cap oxide film 5 and the reoxidation film 6 by dry etching the insulating film. Impurity ions are implanted to form a high concentration source and drain 10 under the side substrate of the side wall 9.
상기한 바와 같이 종래 모스 트랜지스터 제조방법은 식각으로 형성하는 게이트전극의 측면 손상을 복원하기 위해 재산화막을 형성한 후, 할로방지를 위한 경사이온주입공정을 수행하여 그 재산화막 및 게이트전극의 측면에 손상을 주어 모스 트랜지스터의 게이트 특성이 열화되는 문제점이 있었다.As described above, in the conventional method of manufacturing a MOS transistor, a reoxidation film is formed to restore side damage of the gate electrode formed by etching, and then a gradient ion implantation process is performed to prevent halo. There is a problem in that the gate characteristics of the MOS transistor are deteriorated due to damage.
이와 같은 문제점을 감안한 본 발명은 할로이온주입공정으로 부터 게이트전극 및 재산화막을 보호할 수 있는 모스 트랜지스터 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a MOS transistor manufacturing method capable of protecting the gate electrode and the reoxidation film from the halo ion implantation process.
도1a 내지 도1d는 종래 모스 트랜지스터의 제조공정 수순단면도.1A to 1D are cross-sectional views of a manufacturing process of a conventional MOS transistor.
도2a 내지 도2d는 본 발명 모스 트랜지스터의 제조공정 수순단면도.2A to 2D are cross-sectional views of a manufacturing process of the MOS transistor of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2:필드산화막1: Substrate 2: Field Oxide
3:게이트산화막 4:게이트전극3: gate oxide film 4: gate electrode
5:캡산화막 6:재산화막5: cap oxide film 6: reoxidation film
7:할로방지영역 8:저농도 소스 및 드레인7: Halo protection area 8: Low concentration source and drain
9:측벽 10:고농도 소스 및 드레인9: sidewall 10: high concentration source and drain
11:질화막11: Nitride film
상기와 같은 목적은 게이트전극의 측면 손상을 복원하기 위해 재산화막을 증착한 후, 그 재산화막의 상부전면에 질화막을 증착함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설 명하면 다음과 같다.The above object is achieved by depositing a reoxidation film to restore side damage of the gate electrode, and then depositing a nitride film on the upper surface of the reoxidation film, which will be described in detail with reference to the accompanying drawings. Is as follows.
도2a 내지 도2d는 본 발명 모스 트랜지스터 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 필드산화막(2)을 형성하여 소자형성영역을 정의하고, 그 소자형성영역의 상부에 게이트산화막(3)을 형성한 다음, 그 게이트산화막(3)의 중앙부에 캡산화막(5)에 의해 보호되는 게이트전극(4)을 형성하는 단계(도2a)와; 상기 게이트전극(4)의 측면에 재산화막(6)을 형성하고, 그 재산화막(6)과 캡산화막(5)의 상부전면에 질화막(11)을 증착한 후, 경사이온주입을 통해 상기 게이트전극(4)의 측면 기판하부영역에 할로방지영역(7)을 형성하는 단계(도2b)와; 상기 캡산화막(5)을 마스크로 사용하는 이온주입공정으로 상기 게이트전극(4)의 측면 기판(1) 하부에 저농도 소스 및 드레인(8)을 형성하는 단계(도2c)와; 상기 캡산화막(5)과 재산화막(6)의 측면에 증착된 질화막(11)의 측면에 측벽(9)을 형성하고, 불순물 이온주입을 통해 그 측벽(9)의 측면 기판하부에 고농도 소스 및 드레인(10)을 형성하는 단계(도2d)로 구성된다.2A to 2D are cross-sectional views of a MOS transistor fabrication process of the present invention, in which a field oxide film 2 is formed on an upper portion of a substrate 1 to define an element formation region, and an upper portion of the element formation region. Forming a gate oxide film 3, and then forming a gate electrode 4 protected by the cap oxide film 5 in the center of the gate oxide film 3 (FIG. 2A); After forming the reoxidation film 6 on the side of the gate electrode 4, depositing the nitride film 11 on the upper surface of the reoxidization film 6 and the cap oxide film 5, the gate through the gradient ion implantation Forming a halo prevention region 7 in the lower region of the side substrate of the electrode 4 (FIG. 2B); Forming a low concentration source and drain 8 under the side substrate 1 of the gate electrode 4 by an ion implantation process using the cap oxide film 5 as a mask (FIG. 2C); A sidewall 9 is formed on the side of the nitride film 11 deposited on the side of the cap oxide film 5 and the reoxidation film 6, and a high concentration source is formed under the side substrate of the sidewall 9 through impurity ion implantation. Forming a drain 10 (FIG. 2D).
이하, 상기와 같은 본 발명 모스 트랜지스터 제조방법을 좀 더 상세히 설명한다.Hereinafter, the method of manufacturing the MOS transistor of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(1)에 필드산화막(2)을 형성하여, 소자가 형성될 소자형성영역을 정의하고, 그 소자형성영역의 상부에 게이트산화막(3)을 증착한다.First, as shown in FIG. 2A, the field oxide film 2 is formed on the substrate 1 to define an element formation region in which an element is to be formed, and then deposit a gate oxide layer 3 on the element formation region.
그 다음, 상기 게이트산화막(3)과 필드산화막(2)의 상부전면에 다결정실리콘과 산화막을 순차적으로 증착하고, 사진식각공정을 통해 패터닝하여 상기 게이트산화막(3)의 중앙상부에 위치하며, 상부의 캡산화막(5)에 의해 보호되는 게이트전극(4)을 형성한다.Next, polycrystalline silicon and an oxide film are sequentially deposited on the upper surfaces of the gate oxide film 3 and the field oxide film 2, and patterned by a photolithography process to be positioned on the center of the gate oxide film 3. The gate electrode 4 protected by the cap oxide film 5 is formed.
그 다음, 도2b에 도시한 바와 같이 상기 다결정실리콘인 게이트전극(4)을 산화시켜 재산화막(6)을 형성하여, 상기 게이트전극(4)을 형성하기 위한 식각공정으로 그 게이트전극(4)의 측면부가 손상된 것을 복원하고, 그 재산화막(6)과 캡산화막(5)의 상부전면에 질화막(11)을 증착한다.Next, as shown in FIG. 2B, the gate electrode 4, which is the polysilicon, is oxidized to form a reoxidation film 6, and the gate electrode 4 is etched to form the gate electrode 4. The damaged side surface of the film is restored, and the nitride film 11 is deposited on the upper surface of the reoxidized film 6 and the cap oxide film 5.
그 다음, 경사이온주입을 통해 상기 게이트전극(4)의 측면 기판하부 및 그 게이트전극(4)의 하부일부영역의 기판하부에 할로방지영역(7)을 형성한다. 이때, 상기 경사이온주입에 의해 주입되는 이온은 질화막(11)과 재산화막(6)에 의해 게이트전극(4)의 측면부로 주입되지 못하며, 이에 따라 게이트전극(4)과 재산화막(6)이 다시 손상되는 것을 방지하게 된다.Next, a halo prevention region 7 is formed under the side substrate of the gate electrode 4 and under the substrate of the lower portion of the gate electrode 4 by the inclination ion implantation. At this time, the ions implanted by the gradient ion implantation are not implanted into the side portion of the gate electrode 4 by the nitride film 11 and the reoxidation film 6, so that the gate electrode 4 and the reoxidation film 6 are It will prevent damage again.
그 다음, 도2c에 도시한 바와 같이 상기 캡산화막(5)을 이온주입마스크로 사용하는 이온주입공정으로 불순물 이온을 주입하여 상기 게이트전극(4)의 측면 기판(1) 하부에 저농도 소스 및 드레인(8)을 형성한다.Next, as shown in FIG. 2C, impurity ions are implanted in an ion implantation process using the cap oxide film 5 as an ion implantation mask to form a low concentration source and drain under the side substrate 1 of the gate electrode 4. (8) is formed.
이어서, 도2d에 도시한 바와 같이 상기 질화막(11)의 전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 질화막(11)중 기판에 대해 수직방향인 질화막의 특정면 측면에 측벽(9)을 형성하고, 불순물 이온을 이온주입하여 상기 측벽(9)의 측면 기판하부에 고농도 소스 및 드레인(10)을 형성한다.Subsequently, as shown in FIG. 2D, an insulating film is deposited on the entire surface of the nitride film 11, and the insulating film is etched dry so that the sidewall 9 is formed on the side of a specific surface of the nitride film 11 perpendicular to the substrate. And impurity ions are implanted to form a high concentration source and drain 10 under the side substrate of the side wall 9.
상기한 바와 같이 본 발명은 게이트전극의 측면손상을 재산화막의 형성으로 복원하고, 이후의 공정에서 다시 게이트전극 및 재산화막이 손상되는 것을 방지하기 위하여 재산화막의 상부전면에 질화막을 증착하여, 할로이온주입을 위한 경사이온주입에서도 게이트전극이 손상되는 것을 방지하여 모스 트랜지스터의 게이트 특성이 열화되는 것을 방지하는 효과가 있다.As described above, the present invention restores the side surface damage of the gate electrode to the formation of the reoxidation film, and deposits a nitride film on the upper surface of the reoxidation film to prevent the gate electrode and the reoxidation film from being damaged again in a subsequent process, Even in the case of gradient ion implantation for ion implantation, the gate electrode is prevented from being damaged, thereby preventing the gate characteristics of the MOS transistor from being deteriorated.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990010279A KR20000061322A (en) | 1999-03-25 | 1999-03-25 | Manufacturing method for mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990010279A KR20000061322A (en) | 1999-03-25 | 1999-03-25 | Manufacturing method for mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000061322A true KR20000061322A (en) | 2000-10-16 |
Family
ID=19577714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990010279A KR20000061322A (en) | 1999-03-25 | 1999-03-25 | Manufacturing method for mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000061322A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7732280B2 (en) | 2007-02-26 | 2010-06-08 | Samsung Electronics Co., Ltd. | Semiconductor device having offset spacer and method of forming the same |
-
1999
- 1999-03-25 KR KR1019990010279A patent/KR20000061322A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7732280B2 (en) | 2007-02-26 | 2010-06-08 | Samsung Electronics Co., Ltd. | Semiconductor device having offset spacer and method of forming the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5618384A (en) | Method for forming residue free patterned conductor layers upon high step height integrated circuit substrates using reflow of photoresist | |
| US4432132A (en) | Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features | |
| KR100961404B1 (en) | Integrated circuit device and method therefor | |
| KR100875655B1 (en) | Manufacturing method of semiconductor device | |
| JPS6032364A (en) | Manufacture of semiconductor device | |
| US6582998B2 (en) | Method for fabricating nonvolatile semiconductor memory device | |
| US5328867A (en) | Peroxide clean before buried contact polysilicon deposition | |
| US5866482A (en) | Method for masking conducting layers to abate charge damage during plasma etching | |
| KR20000021503A (en) | Method for manufacturing flash memory device | |
| KR100289808B1 (en) | Manufacturing method for mos transistor | |
| KR100299385B1 (en) | Manufacturing method of semiconductor device | |
| US5629235A (en) | Method for forming damage-free buried contact | |
| US20020072156A1 (en) | Method of forming gate electrode in semiconductor devices | |
| KR20000061322A (en) | Manufacturing method for mos transistor | |
| KR0129984B1 (en) | Semiconductor device and its manufacturing method | |
| US7413996B2 (en) | High k gate insulator removal | |
| KR20040007949A (en) | Method of manufacture semiconductor device | |
| KR100244411B1 (en) | Method for manufacturing semiconductor device | |
| US20050164460A1 (en) | Salicide process for metal gate CMOS devices | |
| KR100265849B1 (en) | A method for fabricating MOSFET | |
| KR100215857B1 (en) | Method for fabricating transistor | |
| KR100567047B1 (en) | Menufacturing method for mos transistor | |
| KR0170338B1 (en) | Gate pattern forming method of semiconductor device | |
| KR20000061321A (en) | Manufacturing method for mos transistor | |
| JP3783240B2 (en) | Manufacturing method of flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |