KR20000061061A - Isolation method using silicon spacer - Google Patents
Isolation method using silicon spacer Download PDFInfo
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- KR20000061061A KR20000061061A KR1019990009839A KR19990009839A KR20000061061A KR 20000061061 A KR20000061061 A KR 20000061061A KR 1019990009839 A KR1019990009839 A KR 1019990009839A KR 19990009839 A KR19990009839 A KR 19990009839A KR 20000061061 A KR20000061061 A KR 20000061061A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 실리콘 스페이서를 사용하는 소자분리 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a device isolation method using a silicon spacer.
반도체소자의 집적도가 증가함에 따라 소자분리 영역의 폭 또한 점점 감소하고 있다. 로코스(LOCOS;local oxidation of silicon) 소자분리 방법은 대표적인 소자분리 방법으로 지금까지 널리 사용되어 왔다. 그러나, 로코스 소자분리 방법은 0.5㎛ 이하의 좁은 소자분리 영역을 형성하는 데 적합하지 않은 문제점을 보인다. 이는, 로코스 소자분리 방법이 소자분리 영역의 가장자리에 형성되는 버즈비크의 크기를 감소시키는 데 한계가 있기 때문이다. 따라서, 최근에 버즈비크의 크기를 감소시키기 위하여 트렌치 소자분리 방법 또는 실리콘 스페이서를 사용하는 개량된 로코스 소자분리 방법 등이 제안된 바 있다.As the degree of integration of semiconductor devices increases, the width of device isolation regions also decreases. LOCOS (local oxidation of silicon) device isolation method has been widely used as a representative device isolation method until now. However, the LOCOS device isolation method is not suitable for forming a narrow device isolation region of 0.5 μm or less. This is because the LOCOS device isolation method has a limit in reducing the size of the Buzzbeek formed at the edge of the device isolation region. Therefore, in recent years, in order to reduce the size of Buzzbeek, a trench isolation method or an improved LOCOS isolation method using a silicon spacer has been proposed.
도 1 내지 도 4는 실리콘 스페이서를 사용하는 종래의 로코스 소자분리 방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a conventional LOCOS device isolation method using a silicon spacer.
도 1을 참조하면, 반도체기판(1) 상에 패드산화막 및 패드질화막을 차례로 형성한다. 패드질화막 및 패드산화막을 연속적을 패터닝하여 반도체기판(1)의 소정영역을 노출시키는 패드질화막 패턴(5) 및 패드산화막 패턴(3)을 형성한다. 상기 패드산화막 패턴(3)을 등방성 식각하여 패드질화막 패턴(5)의 가장자리 하부에 언더컷 영역(u)을 형성한다.Referring to FIG. 1, a pad oxide film and a pad nitride film are sequentially formed on the semiconductor substrate 1. The pad nitride film and the pad oxide film are successively patterned to form a pad nitride film pattern 5 and a pad oxide film pattern 3 exposing predetermined regions of the semiconductor substrate 1. The pad oxide film pattern 3 is isotropically etched to form an undercut region u under the edge of the pad nitride film pattern 5.
도 2를 참조하면, 상기 언더컷 영역(u)이 형성된 반도체기판을 열산화시키어 패드산화막 패턴(3)들 사이의 반도체기판(1) 표면에 상기 패드산화막보다 얇은 열산화막(7)을 형성한다. 상기 열산화막(7)이 형성된 반도체기판 전면에 언더컷 영역(u)을 채우는 실리콘막, 예컨대 언도우프트 폴리실리콘막을 형성한다. 상기 실리콘막을 이방성 식각하여 패드질화막 패턴(5)의 측벽에 실리콘 스페이서(9)를 형성한다.Referring to FIG. 2, a thermal oxide film 7 which is thinner than the pad oxide film is formed on the surface of the semiconductor substrate 1 between the pad oxide film patterns 3 by thermally oxidizing the semiconductor substrate on which the undercut region u is formed. A silicon film, such as an undoped polysilicon film, is formed on the entire surface of the semiconductor substrate on which the thermal oxide film 7 is formed, filling the undercut region u. The silicon layer is anisotropically etched to form a silicon spacer 9 on sidewalls of the pad nitride layer pattern 5.
도 3을 참조하면, 상기 실리콘 스페이서(9)가 형성된 반도체기판을 열산화시키어 패드질화막 패턴(5)들 사이의 영역에 실리콘 스페이서(9) 및 반도체기판(1)이 산화된 필드산화막(11)을 형성한다. 이때, 도 3에 도시된 바와 같이 언더컷 영역(u) 내부의 실리콘막은 완전히 산화되기가 어려우므로 필드산화막(11)의 가장자리에 형성되는 버즈비크의 크기를 현저히 감소시킬 수 있다. 그러나, 필드산화막(11)의 버즈비크의 크기를 현저히 감소시킬 수 있는 반면에 언더컷 영역(u) 내에 실리콘 잔여물(R)이 잔존하는 현상을 피할 수 없다.Referring to FIG. 3, a field oxide film 11 in which a silicon spacer 9 and a semiconductor substrate 1 are oxidized in a region between pad nitride layer patterns 5 by thermally oxidizing a semiconductor substrate on which the silicon spacers 9 are formed. To form. In this case, as shown in FIG. 3, since the silicon film inside the undercut region u is difficult to be completely oxidized, the size of the buzz be formed at the edge of the field oxide film 11 may be significantly reduced. However, while the size of the burj beak of the field oxide film 11 can be significantly reduced, the phenomenon that the silicon residue R remains in the undercut region u cannot be avoided.
도 4를 참조하면, 상기 필드산화막(11) 사이의 패드질화막 패턴(5)을 인산용액으로 제거하여 패드산화막 패턴(3)을 노출시킨다. 이어서, 상기 노출된 패드산화막 패턴(3)을 습식 식각공정으로 제거하여 필드산화막(11)들 사이의 반도체기판(1)을 노출시킨다. 이때, 상기 실리콘 잔여물(R)이 습식 식각용액 내에 부유되고, 이들 실리콘 잔여물(R)중 일부는 도 4에 도시된 바와 같이 반도체기판(1)의 표면에 다시 흡착된다.Referring to FIG. 4, the pad nitride layer pattern 5 between the field oxide layers 11 is removed with a phosphate solution to expose the pad oxide layer pattern 3. Subsequently, the exposed pad oxide layer pattern 3 is removed by a wet etching process to expose the semiconductor substrate 1 between the field oxide layers 11. At this time, the silicon residue R is suspended in the wet etching solution, and some of these silicon residues R are again adsorbed onto the surface of the semiconductor substrate 1 as shown in FIG. 4.
이어서 도시하지는 않았지만, 상기 노출된 반도체기판(1) 표면에 희생산화막을 형성한 다음, 상기 희생산화막을 습식 식각용액으로 제거한다. 이때, 상기 실리콘 잔여물(R)은 또 다시 습식 식각용액 내에 부유되거나 반도체기판(1)의 표면에 다시 흡착된다. 이와 같이 반도체기판(1) 표면에 실리콘 잔여물(R)이 존재하면, 후속공정에서 형성되는 게이트 산화막의 두께균일도 및 막질이 저하된다.Subsequently, although not shown, a sacrificial oxide film is formed on the exposed surface of the semiconductor substrate 1, and then the sacrificial oxide film is removed with a wet etching solution. At this time, the silicon residue R is again suspended in the wet etching solution or adsorbed on the surface of the semiconductor substrate 1 again. When the silicon residue R is present on the surface of the semiconductor substrate 1 as described above, the thickness uniformity and film quality of the gate oxide film formed in a subsequent process are reduced.
본 발명의 목적은 게이트 산화막의 두께균일도 및 막질을 개선시킬 수 있는 실리콘 스페이서를 사용하는 소자분리 방법을 제공하는 데 있다.An object of the present invention is to provide a device isolation method using a silicon spacer that can improve the thickness uniformity and film quality of the gate oxide film.
도 1 내지 도 4는 종래의 소자분리 방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a conventional device isolation method.
도 5 내지 도 9는 본 발명에 따른 소자분리 방법을 설명하기 위한 단면도들이다.5 to 9 are cross-sectional views illustrating a device isolation method according to the present invention.
상기 목적을 달성하기 위하여 본 발명은 반도체기판의 소정영역 상에 차례로 적층된 패드산화막 패턴 및 패드질화막 패턴으로 구성되되 상기 패드질화막 패턴의 가장자리 아래에 언더컷 영역을 구비하는 패드 패턴을 형성하는 단계와, 상기 패드 패턴의 측벽에 상기 언더컷 영역을 채우는 실리콘 스페이서를 형성하는 단계와, 상기 실리콘 스페이서 및 상기 반도체기판을 열산화시키어 상기 패드 패턴들 사이에 필드산화막을 형성하는 단계와, 상기 패드질화막 패턴을 제거하여 상기 패드산화막 패턴을 노출시키는 단계와, 상기 언더컷 영역에 잔존하는 실리콘 잔여물을 완전히 열산화시키는 단계와, 상기 노출된 패드산화막 패턴 및 상기 열산화된 실리콘 잔여물을 산화막 식각용액으로 제거하는 단계를 포함한다.In order to achieve the above object, the present invention includes forming a pad pattern comprising a pad oxide film pattern and a pad nitride film pattern sequentially stacked on a predetermined region of a semiconductor substrate, the pad pattern having an undercut area below an edge of the pad nitride film pattern; Forming a silicon spacer on the sidewall of the pad pattern to fill the undercut region, thermally oxidizing the silicon spacer and the semiconductor substrate to form a field oxide layer between the pad patterns, and removing the pad nitride layer pattern Exposing the pad oxide layer pattern, completely thermally oxidizing the silicon residue remaining in the undercut region, and removing the exposed pad oxide layer pattern and the thermally oxidized silicon residue with an oxide etching solution. It includes.
이하, 첨부한 도면들을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 5를 참조하면, 반도체기판(21), 예컨대 실리콘기판 상에 패드산화막 및 패드질화막을 차례로 형성한다. 상기 패드산화막은 150Å 내지 300Å의 열산화막으로 형성하는 것이 바람직하고, 상기 패드질화막은 1000Å 내지 2000Å의 LPCVD 질화막으로 형성하는 것이 바람직하다. 상기 패드질화막 및 패드산화막을 연속적으로 패터닝하여 반도체기판(21)의 소정영역 상에 차례로 적층된 패드산화막 패턴(23) 및 패드질화막 패턴(25)으로 구성되는 패드 패턴을 형성한다. 상기 패드산화막 패턴(23)을 등방성 식각하여 상기 패드질화막 패턴(25)의 가장자리 아래에 언더컷 영역(u)을 형성한다. 상기 패드산화막 패턴(23)을 등방성 식각하는 공정은 불산용액 또는 완충산화막 식각용액(BOE; buffered oxide etchant)을 사용하는 습식 식각공정을 이용하는 것이 바람직하다.Referring to FIG. 5, a pad oxide film and a pad nitride film are sequentially formed on a semiconductor substrate 21, for example, a silicon substrate. The pad oxide film is preferably formed of a thermal oxide film of 150 kV to 300 kV, and the pad nitride film is preferably formed of an LPCVD nitride film of 1000 kV to 2000 kV. The pad nitride film and the pad oxide film are successively patterned to form a pad pattern including a pad oxide film pattern 23 and a pad nitride film pattern 25 sequentially stacked on a predetermined region of the semiconductor substrate 21. The pad oxide layer pattern 23 is isotropically etched to form an undercut region u under an edge of the pad nitride layer pattern 25. The isotropic etching of the pad oxide layer pattern 23 is preferably performed using a wet etching process using a hydrofluoric acid solution or a buffered oxide etchant (BOE).
도 6을 참조하면, 상기 언더컷 영역(u)이 형성된 반도체기판을 열산화시키어 상기 패드질화막 패턴(25)들 사이의 반도체기판(21) 표면에 패드산화막 패턴(23)보다 얇은 열산화막(27)을 형성한다. 이어서, 상기 열산화막(27)이 형성된 반도체기판 전면에 상기 언더컷 영역(u)을 채우는 실리콘막, 예컨대 언도우프트 폴리실리콘막을 형성한다. 상기 실리콘막을 이방성 식각하여 패드패턴 측벽에 실리콘 스페이서(29)를 형성한다. 상기 실리콘막은 단차도포성이 우수한 LPCVD 방법으로 형성하는 것이 바람직하다.Referring to FIG. 6, a thermal oxide layer 27 thinner than a pad oxide layer pattern 23 is formed on a surface of the semiconductor substrate 21 between the pad nitride layer patterns 25 by thermally oxidizing the semiconductor substrate on which the undercut region u is formed. To form. Subsequently, a silicon film, such as an undoped polysilicon film, is formed on the entire surface of the semiconductor substrate on which the thermal oxide film 27 is formed, filling the undercut region u. The silicon layer is anisotropically etched to form silicon spacers 29 on the sidewalls of the pad pattern. The silicon film is preferably formed by the LPCVD method with excellent step coating properties.
도 7을 참조하면, 상기 실리콘 스페이서(29)가 형성된 반도체기판을 열산화시키어 패드질화막 패턴(25)들 사이의 영역에 실리콘 스페이서(29) 및 반도체기판(21)이 열산화된 필드산화막(31)을 형성한다. 이때, 상기 언더컷 영역(u) 내에 존재하는 실리콘막은 완전히 열산되지 않는다. 따라서, 도 3에서 설명한 바와 같이, 필드산화막(31)의 버즈비크 크기는 현저히 감소시킬 수 있으나 언더컷 영역(u) 내에 실리콘 잔여물(R)이 잔존한다.Referring to FIG. 7, a field oxide layer 31 in which a silicon spacer 29 and a semiconductor substrate 21 are thermally oxidized in a region between pad nitride layer patterns 25 by thermally oxidizing a semiconductor substrate on which the silicon spacers 29 are formed. ). At this time, the silicon film present in the undercut region u is not completely thermally dissipated. Therefore, as described with reference to FIG. 3, the size of the burj beak of the field oxide film 31 can be significantly reduced, but the silicon residue R remains in the undercut region u.
도 8을 참조하면, 상기 패드질화막 패턴(25)을 인산용액으로 제거하여 패드산화막 패턴(23)을 노출시킨다. 이때, 상기 패드산화막 패턴(23) 내에 잔존하는 실리콘 잔여물(R)은 여전히 존재한다. 상기 패드산화막 패턴(23)이 노출된 반도체기판을 열산화시키어 실리콘 잔여물(R)을 완전히 산화시킴으로써, 필드산화막(31)들 사이의 반도체기판(21) 표면에 변형된 패드산화막 패턴(23a)을 형성한다. 이에 따라, 실리콘 잔여물(R)이 후속공정인 습식 식각공정에 의해 부유되거나 반도체기판 표면에 다시 흡착되는 현상을 사전에 방지할 수 있다.Referring to FIG. 8, the pad nitride layer pattern 25 is removed with a phosphate solution to expose the pad oxide layer pattern 23. At this time, the silicon residue R remaining in the pad oxide layer pattern 23 is still present. The pad oxide film pattern 23a deformed on the surface of the semiconductor substrate 21 between the field oxide films 31 by thermally oxidizing the semiconductor substrate to which the pad oxide film pattern 23 is exposed, thereby completely oxidizing the silicon residue R. To form. Accordingly, it is possible to prevent the silicon residue R from being suspended or adsorbed again on the surface of the semiconductor substrate by a wet etching process which is a subsequent process.
도 9를 참조하면, 상기 변형된 패드산화막 패턴(23a)을 습식 식각용액, 예컨대 불산용액 또는 완충산화막 식각용액(BOE; buffered oxide etchant)을 사용하여 제거함으로써, 필드산화막(31)들 사이의 반도체기판, 즉 활성영역을 노출시킨다. 이때, 상기 필드산화막(31) 또한 식각되어 표면 프로파일이 완만해진 소자분리막(31a)이 형성된다. 다음에, 상기 노출된 활성영역 표면에 희생산화막(도시하지 않음)을 형성한 후에 상기 희생산화막을 습식 식각용액으로 제거한다. 이어서, 상기 활성영역 표면에 게이트 산화막(33)을 형성한다. 여기서, 상기 변형된 패드산화막 패턴(23a) 및 상기 희생산화막을 습식 식각공정으로 제거하는 이유는 활성영역 표면에 식각 손상이 가해지는 것을 방지하기 위함이다. 이는, 활성영역에 건식 식각공정에 의한 식각 손상이 가해지면, 게이트 산화막의 막질이 저하됨은 물론 게이트 산화막 및 그 아래의 반도체기판 사이의 계면 특성이 저하되기 때문이다. 특히, 게이트 산화막 아래의 반도체기판 표면은 모스 트랜지스터의 전기적 특성에 직접적으로 영향을 미치는 채널 영역에 해당한다. 따라서, 상기 변형된 패드산화막 패턴(23a) 및 희생산화막은 건식 식각공정 보다는 습식 식각공정으로 제거하는 것이 바람직하다.Referring to FIG. 9, the semiconductor pad between the field oxide layers 31 may be removed by removing the modified pad oxide layer pattern 23a using a wet etching solution such as hydrofluoric acid or a buffered oxide etchant (BOE). Expose the substrate, ie the active area. In this case, the field oxide layer 31 is also etched to form a device isolation layer 31a having a smooth surface profile. Next, after the sacrificial oxide film (not shown) is formed on the exposed active region surface, the sacrificial oxide film is removed by a wet etching solution. Subsequently, a gate oxide layer 33 is formed on the surface of the active region. The reason for removing the modified pad oxide layer pattern 23a and the sacrificial oxide layer by a wet etching process is to prevent etching damage from being applied to the surface of the active region. This is because when the etching damage is caused by the dry etching process in the active region, the film quality of the gate oxide film is lowered as well as the interface property between the gate oxide film and the semiconductor substrate beneath it is lowered. In particular, the surface of the semiconductor substrate under the gate oxide film corresponds to a channel region that directly affects the electrical characteristics of the MOS transistor. Therefore, the modified pad oxide layer pattern 23a and the sacrificial oxide layer may be removed by a wet etching process rather than a dry etching process.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적인 사상 내에서 당 분야에서 통상의 지식을 가진자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
상술한 바와 같이 본 발명에 따르면, 패드산화막 패턴을 제거하기 전에 패드산화막 패턴 내에 존재하는 실리콘 잔여물을 완전히 열산화시킴으로써, 후속 습식 식각공정시 실리콘 잔여물이 오염원으로 작용하는 것을 방지할 수 있다. 이에 따라, 후속공정에서 형성되는 게이트 산화막의 막질 및 두께균일도 등을 개선시키어 모스 트랜지스터의 특성을 향상시킬 수 있다.As described above, according to the present invention, the silicon residue present in the pad oxide layer pattern is completely thermally oxidized before the pad oxide layer pattern is removed, thereby preventing the silicon residue from acting as a contaminant during the subsequent wet etching process. Accordingly, the film quality, thickness uniformity, and the like of the gate oxide film formed in a subsequent step can be improved to improve characteristics of the MOS transistor.
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| KR1019990009839A KR20000061061A (en) | 1999-03-23 | 1999-03-23 | Isolation method using silicon spacer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100649872B1 (en) * | 2005-12-29 | 2006-11-27 | 동부일렉트로닉스 주식회사 | Method of fabricating the trench isolation layer in semiconductor device |
| KR100873357B1 (en) * | 2002-10-31 | 2008-12-10 | 매그나칩 반도체 유한회사 | Method for forming the Isolation Layer of Semiconductor Device |
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1999
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100873357B1 (en) * | 2002-10-31 | 2008-12-10 | 매그나칩 반도체 유한회사 | Method for forming the Isolation Layer of Semiconductor Device |
| KR100649872B1 (en) * | 2005-12-29 | 2006-11-27 | 동부일렉트로닉스 주식회사 | Method of fabricating the trench isolation layer in semiconductor device |
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