KR20000060787A - Method of manufacturing silicon on insulator wafer - Google Patents
Method of manufacturing silicon on insulator wafer Download PDFInfo
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- KR20000060787A KR20000060787A KR1019990009401A KR19990009401A KR20000060787A KR 20000060787 A KR20000060787 A KR 20000060787A KR 1019990009401 A KR1019990009401 A KR 1019990009401A KR 19990009401 A KR19990009401 A KR 19990009401A KR 20000060787 A KR20000060787 A KR 20000060787A
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- silicon substrate
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 110
- 239000010703 silicon Substances 0.000 title claims abstract description 110
- 238000004519 manufacturing process Methods 0.000 title abstract description 16
- 239000012212 insulator Substances 0.000 title abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 238000000034 method Methods 0.000 claims abstract description 45
- 230000003647 oxidation Effects 0.000 claims abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 238000005498 polishing Methods 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 9
- 238000007517 polishing process Methods 0.000 claims abstract description 7
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 24
- 235000012431 wafers Nutrition 0.000 description 20
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- -1 oxygen ions Chemical class 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
본 발명은 실리콘 온 인슐레이터(Silicon On Insulator : 이하, SOI) 웨이퍼의 제조방법에 관한 것으로, 보다 상세하게는, 비교적 간단하게 두께 균일도가 향상된 실리콘층을 얻기 위한 SOI 웨이퍼의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a silicon on insulator (hereinafter referred to as SOI) wafer, and more particularly, to a method for manufacturing a SOI wafer for obtaining a silicon layer having improved thickness uniformity relatively simply.
반도체 소자의 고집적화, 고속도화, 및 저전력화가 진행됨에 따라, 벌크 실리콘으로 이루어진 웨이퍼를 대신하여 SOI 웨이퍼를 이용하는 반도체 집적 기술이 주목되고 있다. SOI 웨이퍼에 집적된 반도체 소자는 완전한 소자 분리와, 낮은 접합 용량 및 큰 드레인 전류 특성을 갖도록 할 수 있기 때문에, 고속 동작이 가능하다는 잇점을 갖는다.As the integration of semiconductor devices, high speeds, and low powers have progressed, semiconductor integration technologies using SOI wafers have been attracting attention instead of wafers made of bulk silicon. Semiconductor devices integrated in an SOI wafer have the advantage that high speed operation is possible because of the complete device isolation, low junction capacity and large drain current characteristics.
여기서, SOI 웨이퍼는 전체를 지지하는 지지기판과, 소자가 형성되는 실리콘층 사이에 산화막이 개재되어 있는 구조이며, 통상, 산소 이온주입을 이용하는 SIMOX(seperation by implanted oxygen)법과, 벌크 실리콘으로 이루어진 두 장의 실리콘 기판을 산화막의 개재하에 접합시키는 접합법으로 형성한다.Here, the SOI wafer has a structure in which an oxide film is interposed between the support substrate supporting the whole and the silicon layer on which the device is formed, and typically, a SIMOX (seperation by implanted oxygen) method using oxygen ion implantation, and a bulk silicon A long silicon substrate is formed by a bonding method in which a long silicon substrate is bonded through an oxide film.
SIMOX법은 벌크 실리콘으로 이루어지는 웨이퍼에 산소 이온을 주입한 후, 열처리를 수행하는 것에 의해 산소 이온과 실리콘을 반응시킴으로써, 웨이퍼 내에 상기 웨이퍼를 분리시키는 매몰산화막을 형성시키는 방법이다. 그러나, SIMOX법은 이온주입 및 열처리 공정을 통해 SOI 웨이퍼를 제조하기 때문에, 소자가 형성될 실리콘층의 두께 조절이 어렵고, 특히, 제조 시간이 길다는 단점이 있다.The SIMOX method is a method of forming a buried oxide film in which a wafer is separated in a wafer by injecting oxygen ions into a wafer made of bulk silicon and then reacting the oxygen ions with silicon by performing a heat treatment. However, since the SIMOX method manufactures the SOI wafer through the ion implantation and heat treatment processes, it is difficult to control the thickness of the silicon layer on which the device is to be formed, and in particular, the manufacturing time is long.
접합법은 준비된 두 장의 실리콘 기판들 중에서 전체를 지지하기 위한 제1실리콘 기판 상에 산화막을 형성하고, 상기 산화막 상에 제2실리콘 기판을 접합시킨 후, 그라인딩(Grinding) 및 화학적 기계 연마(Chemical Mechanical Polishing : 이하, CMP) 공정으로 상기 제2실리콘 기판의 후면을 연마해서 원하는 두께의 실리콘층을 얻는 방법이다. 이러한 접합법은 제조 공정이 SIMOX법에 비해 비교적 간단하기 때문에, 주로 이용되고 있다.The bonding method forms an oxide film on the first silicon substrate for supporting the entirety of the two silicon substrates prepared, and after bonding the second silicon substrate on the oxide film, grinding and chemical mechanical polishing (Chemical Mechanical Polishing) : A method of obtaining a silicon layer having a desired thickness by polishing the back surface of the second silicon substrate by a CMP) process. This bonding method is mainly used because the manufacturing process is relatively simple compared to the SIMOX method.
그러나, SOI 웨이퍼를 제조하기 위한 접합법은 그 공정이 SIMOX법에 비해 빠르다는 잇점 때문에 주로 이용되고는 있으나, 실리콘 기판을 그라인딩한 후, 원하는 두께의 실리콘층이 얻어질 때까지 CMP 공정으로 연마하게 되면, 그라인딩에 의해 초래된 실리콘 기판의 표면 단차가 CMP 공정시에 그대로 전사됨으로써, 균일한 두께의 실리콘층을 얻을 수 없게 된다.However, the bonding method for manufacturing SOI wafers is mainly used because of the advantage that the process is faster than the SIMOX method, but after grinding the silicon substrate, polishing is performed by the CMP process until a silicon layer having a desired thickness is obtained. As the surface level difference of the silicon substrate caused by the grinding is transferred as it is during the CMP process, a silicon layer with a uniform thickness cannot be obtained.
그런데, SOI 웨이퍼에 집적된 반도체 소자의 전기적 특성은, 당업자들에게 알려져 있는 바와 같이, 실리콘층의 두께 균일도에 의해 크게 좌우되므로, 접합법으로 SOI 웨이퍼를 제조한 후에는, SOI 소자의 만족할만한 전기적 특성을 얻기 위해서, 즉, 실리콘층의 두께 균일성을 향상시키기 위해서, 별도의 후속 공정을 필요로하기 때문에, 결과적으로는, 제조 공정이 복잡한 문제점이 있다.By the way, since the electrical characteristics of the semiconductor device integrated in the SOI wafer are largely dependent on the thickness uniformity of the silicon layer, as known to those skilled in the art, after fabricating the SOI wafer by the bonding method, satisfactory electrical properties of the SOI device are achieved. In order to obtain, i.e., to improve the thickness uniformity of the silicon layer, a separate subsequent step is required, and as a result, the manufacturing process has a complicated problem.
한편, 종래에는 접합법으로 이용하여 SOI 웨이퍼를 제조하는 경우, 실리콘층의 두께 균일도를 향상시키기 위하여, 실리콘 기판에 대한 CMP 공정 전에, 상기 실리콘 기판에 수소 또는 산소 이온을 이온주입한 후, 열 공정을 수행하여, 보다 용이한 CMP 공정이 수행되도록 함과 동시에, 실리콘층의 두께 균일도가 향상되도록 하고 있으나, 이 경우에는 제조 비용의 증가 및 생산성의 저하를 초래하게 된다.On the other hand, when manufacturing an SOI wafer using a bonding method conventionally, in order to improve the thickness uniformity of the silicon layer, hydrogen or oxygen ions are ion implanted into the silicon substrate before the CMP process for the silicon substrate, and then a thermal process is performed. By performing the CMP process more easily, the thickness uniformity of the silicon layer is improved, but in this case, an increase in manufacturing cost and a decrease in productivity are caused.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 매우 간단하게 실리콘층의 두께 균일도를 향상시킬 수 있는 SOI 웨이퍼의 제조방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing an SOI wafer which can improve the thickness uniformity of a silicon layer very simply.
도 1a 내지 도 1h는 본 발명의 실시예에 따른 실리콘 온 인슐레이터 웨이퍼의 제조방법을 설명하기 위한 공정 단면도.1A to 1H are cross-sectional views illustrating a method of manufacturing a silicon on insulator wafer according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : 제1실리콘 기판 2 : 제1산화막1: first silicon substrate 2: first oxide film
3 : 제2실리콘 기판 3a : 실리콘층3: second silicon substrate 3a: silicon layer
4 : 제2산화막 5 : 제3산화막4: second oxide film 5: third oxide film
6 : 제1열산화막 7 : 제2열산화막6: first thermal oxide film 7: second thermal oxide film
상기와 같은 목적을 달성하기 위한 본 발명의 SOI 웨이퍼의 제조방법은, 전체를 지지하기 위한 제1실리콘 기판과, 소자가 형성될 제2실리콘 기판을 제공하는 단계; 상기 제1실리콘 기판의 일측면 상에 제1산화막을 형성하고, 상기 제2실리콘 기판의 일측면 상에 제2산화막을 형성하는 단계; 상기 제1산화막과 제2산화막이 접촉되도록, 상기 제1실리콘 기판과 제2실리콘 기판들을 본딩시키는 단계; 상기 제2실리콘 기판의 타측면 소정 두께를 그라인딩하는 단계; 상기 그라인딩에 의해 표면 단차가 발생된 상기 제2실리콘 기판의 타측면 상에 제3산화막을 형성하는 단계; 상대적으로 두껍게 잔류된 제2실리콘 기판의 타측면 부분이 노출될 때까지, 상기 제3산화막을 화학적기계연마 공정으로 연마하는 단계; 상기 제2실리콘 기판의 타측면 소정 두께를 열산화시켜, 상기 제2실리콘 기판의 타측면에 잔류된 제3산화막을 포함하는 제1열산화막을 형성하는 단계; 상대적으로 두껍게 잔류된 제2실리콘 기판의 타측면 부분이 노출될 때까지, 상기 제1열산화막을 화학적기계연마 공정으로 연마하는 단계; 상기 제2실리콘 기판의 타측면 소정 두께를 열산화시켜, 상기 제2실리콘 기판의 타측면에 잔류된 제1열산화막을 포함하는 제2열산화막을 형성하는 단계; 및, 실리콘층이 얻어지도록, 화학적기계연마 공정으로 상기 제2열산화막을 제거하는 단계를 포함하여 이루어진다.SOI wafer manufacturing method of the present invention for achieving the above object comprises the steps of providing a first silicon substrate for supporting the whole, and a second silicon substrate on which the device is to be formed; Forming a first oxide film on one side of the first silicon substrate, and forming a second oxide film on one side of the second silicon substrate; Bonding the first silicon substrate and the second silicon substrate to contact the first oxide film and the second oxide film; Grinding a predetermined thickness of the other side of the second silicon substrate; Forming a third oxide film on the other side surface of the second silicon substrate having a surface step generated by the grinding; Polishing the third oxide film by a chemical mechanical polishing process until the other side portion of the second silicon substrate remaining relatively thick is exposed; Thermally oxidizing a predetermined thickness of the other side of the second silicon substrate to form a first thermal oxide layer including a third oxide layer remaining on the other side of the second silicon substrate; Polishing the first thermal oxide film by a chemical mechanical polishing process until the other side portion of the second silicon substrate, which remains relatively thick, is exposed; Thermally oxidizing a predetermined thickness of the other side of the second silicon substrate to form a second thermal oxide layer including the first thermal oxide layer remaining on the other side of the second silicon substrate; And removing the second thermal oxide film by a chemical mechanical polishing process so that a silicon layer is obtained.
본 발명에 따르면, 균일한 두께의 실리콘층을 얻기 위하여, 열산화 공정과 CMP 공정만을 이용하기 때문에, 그 공정이 비교적 간단하다.According to the present invention, since only a thermal oxidation process and a CMP process are used to obtain a silicon layer of uniform thickness, the process is relatively simple.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1h는 본 발명의 실시예에 따른 SOI 웨이퍼의 제조방법을 설명하기 위한 공정 단면도이다.1A to 1H are cross-sectional views illustrating a method of manufacturing an SOI wafer according to an embodiment of the present invention.
우선, 도 1a에 도시된 바와 같이, 벌크 실리콘으로 이루어진 제1실리콘 기판(1)을 마련하고, 상기 제1실리콘 기판(1)의 일측면 상에 열산화막 또는 CVD 산화막으로 이루어진 제1산화막(2)을 형성한다. 마찬가지로, 벌크 실리콘으로 이루어진 제2실리콘 기판(3)을 마련하고, 상기 제2실리콘 기판(3)의 일측면 상에 열산화막 또는 CVD 산화막으로 이루어진 제2산화막(4)을 형성한다. 여기서, 제1 및 제2산화막(2, 4)은 LPCVD, PECVD, APCVD, Photo-CVD, 또는, ECR(Electron Cyclotron Resonance)-CVD 등의 공정으로 형성한다.First, as shown in FIG. 1A, a first silicon substrate 1 made of bulk silicon is provided, and a first oxide film 2 made of a thermal oxide film or a CVD oxide film on one side of the first silicon substrate 1. ). Similarly, a second silicon substrate 3 made of bulk silicon is provided, and a second oxide film 4 made of a thermal oxide film or a CVD oxide film is formed on one side of the second silicon substrate 3. Here, the first and second oxide films 2 and 4 are formed by a process such as LPCVD, PECVD, APCVD, Photo-CVD, or ECR (Electron Cyclotron Resonance) -CVD.
그런 다음, 제1산화막(2)과 제2산화막(4)이 접촉되도록, 상기 제1실리콘 기판(1)과 제2실리콘 기판(3)을 본딩시킨다. 여기서, 제1실리콘 기판(1)은 지지기판으로서의 기능을 수행도록 하기 위한 것이며, 제2실리콘 기판(3)은 소자가 형성될 실리콘층을 얻기 위한 것이다.Then, the first silicon substrate 1 and the second silicon substrate 3 are bonded so that the first oxide film 2 and the second oxide film 4 are in contact with each other. Here, the first silicon substrate 1 is to perform a function as a support substrate, the second silicon substrate 3 is to obtain a silicon layer on which the device is to be formed.
이어서, 도 1b에 도시된 바와 같이, 제2실리콘 기판(3)의 타측면 소정 두께를 그라인딩(Grinding)한다. 이때, 도시된 바와 같이, 그라인딩된 제2실리콘 기판(3)의 타측면에는 단차가 발생되는 것으로 인하여, 매우 불균일하게 된다.Subsequently, as illustrated in FIG. 1B, the predetermined thickness of the other side of the second silicon substrate 3 is ground. At this time, as shown, due to the step is generated on the other side surface of the ground second silicon substrate 3, it becomes very uneven.
다음으로, 도 1c에 도시된 바와 같이, 그라인딩된 제2실리콘 기판(3)의 타측면 상에 BPSG 산화막, PSG 산화막, USG 산화막, 또는, HDP 산화막 중에서 선택되는 하나의 산화막으로된 제3산화막(5)을 1 내지 5㎛ 두께로 형성한다. 여기서, 그라인딩된 제2실리콘 기판(3)의 타측면이 매우 불균일한 것에 기인하여, 도시된 바와 같이, 이러한 제2실리콘 기판(2) 상에 형성된 제3산화막(5)의 표면도 불균일하게 된다.Next, as shown in FIG. 1C, a third oxide film including one oxide film selected from a BPSG oxide film, a PSG oxide film, a USG oxide film, or an HDP oxide film on the other side of the ground second silicon substrate 3 ( 5) is formed to a thickness of 1 to 5 mu m. Here, due to the very uneven side of the ground second silicon substrate 3, as shown, the surface of the third oxide film 5 formed on the second silicon substrate 2 is also uneven. .
그 다음, 도 1d에 도시된 바와 같이, 상대적으로 두꺼운 제2실리콘 기판(3)의 타측면 부분이 노출될 때까지, CMP 공정으로 제3산화막(5)을 연마하고, 이어서, 도 1e에 도시된 바와 같이, 열산화 공정으로 제2실리콘 기판(3)의 타측면 소정 두께를 열산화시킴으로써, 상기 제2실리콘 기판(3)의 타측면에 상기 제3산화막을 포함하는 일정 두께의 제1열산화막(6)을 형성한다. 이때, 산화막으로 매립된 부분 보다 실리콘 기판 부분의 산화 속도가 더 빠른 것에 기인하여, 열산화되지 않고 잔류된 제2실리콘 기판(3)의 표면은 어느 정도의 평탄화가 이루어진다.Then, as shown in FIG. 1D, the third oxide film 5 is polished by the CMP process until the other side portion of the relatively thick second silicon substrate 3 is exposed, and then shown in FIG. 1E. As described above, the first row of a predetermined thickness including the third oxide film on the other side of the second silicon substrate 3 by thermally oxidizing the predetermined thickness of the other side of the second silicon substrate 3 by a thermal oxidation process. The oxide film 6 is formed. At this time, due to the faster oxidation rate of the silicon substrate portion than the portion embedded with the oxide film, the surface of the second silicon substrate 3 remaining without thermal oxidation is subjected to some leveling.
다음으로, 도 1f에 도시된 바와 같이, 제2실리콘 기판(3)이 노출될 때까지, CMP 공정으로 제1열산화막(6)을 연마하고, 이어서, 도 1g에 도시된 바와 같이, 재차 열산화 공정을 공정을 수행하여 일정 두께의 제2열산화막(7)을 형성한다. 이때, 노출된 제2실리콘 기판(3) 부분의 산화 속도가 제1열산화막(6)으로 채워진 부분의 산화 속도 보다 빠른 것에 기인하여, 잔류된 제2실리콘 기판(3)의 두께는, 도시된 바와 같이, 매우 균일하게 된다. 한편, 열산화 공정은 산화되지 않고 잔류되는 제2실리콘 기판(3)의 두께가 원하는 실리콘층의 두께와 유사하거나, 또는, 약간 두껍게 되도록 하는 조건으로 수행함이 바람직하다.Next, as shown in FIG. 1F, the first thermal oxide film 6 is polished by a CMP process until the second silicon substrate 3 is exposed, and then again, as shown in FIG. 1G. The oxidation process is performed to form a second thermal oxide film 7 having a predetermined thickness. At this time, due to the oxidation rate of the exposed portion of the second silicon substrate 3 is faster than the oxidation rate of the portion filled with the first thermal oxide film 6, the thickness of the remaining second silicon substrate 3 is shown in FIG. As it is, it becomes very uniform. On the other hand, the thermal oxidation process is preferably performed under conditions such that the thickness of the second silicon substrate 3 remaining without oxidation is similar to or slightly thicker than the thickness of the desired silicon layer.
그리고 나서, 도 1h에 도시된 바와 같이, 공지된 방법으로 제2열산화막을 제거한 후, 노출된 제2실리콘 기판의 타측면 일부 두께를 CMP 공정으로 연마하여, 소자가 형성될 50 내지 500㎚ 두께의 실리콘층(3a)을 얻는다. 여기서, 도 1g에서와 같이, 제2실리콘 기판(3)은 그 두께가 비교적 균일하기 때문에, 이러한 제2실리콘 기판(3)의 소정 두께를 연마하더라도, 도 1h에서와 같이, 최종적으로 얻게 되는 실리콘층(3a)의 두께는 매우 균일하게 된다.Then, as shown in FIG. 1H, after removing the second thermal oxide film by a known method, a portion of the other side surface of the exposed second silicon substrate is polished by a CMP process to form a device having a thickness of 50 to 500 nm. Silicon layer 3a is obtained. Here, as shown in Fig. 1G, since the thickness of the second silicon substrate 3 is relatively uniform, even if the predetermined thickness of the second silicon substrate 3 is polished, as in Fig. 1H, the silicon finally obtained The thickness of the layer 3a becomes very uniform.
이상에서와 같이, 본 발명의 SOI 웨이퍼 제조방법은 실리콘층의 두께 균일도의 향상을 위해 열산화 공정 및 CMP 공정만을 이용하기 때문에, 그 공정이 비교적 간단하다. 따라서, 실리콘층의 두께 균일도를 향상시킨 것에 기인하여, 이러한 SOI 웨이퍼에 집적시킨 반도체 소자의 전기적 특성을 향상시킬 수 있다.As described above, since the SOI wafer manufacturing method of the present invention uses only the thermal oxidation process and the CMP process to improve the thickness uniformity of the silicon layer, the process is relatively simple. Therefore, due to the improved thickness uniformity of the silicon layer, the electrical characteristics of the semiconductor element integrated in such an SOI wafer can be improved.
한편, 여기에서는 본 발명의 특정 실시예에 대해서 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한, 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (4)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2010105955A1 (en) | 2009-03-17 | 2010-09-23 | S.O.I.Tec Silicon On Insulator Technologies | Finishing method for manufacturing substrates in the field of electronics |
| FR2943459A1 (en) * | 2009-03-17 | 2010-09-24 | Soitec Silicon On Insulator | FINISHING PROCESS FOR THE MANUFACTURE OF SUBSTRATES IN THE FIELD OF ELECTRONICS |
| US20110256730A1 (en) * | 2009-03-17 | 2011-10-20 | S.O.I. Tec Silicon On Insulator Technologies | Finishing method for manufacturing substrates in the field of electronics |
| CN102272901A (en) * | 2009-03-17 | 2011-12-07 | S.O.I.Tec绝缘体上硅技术公司 | Finishing method for manufacturing substrates in the field of electronics |
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