KR20000060067A - Apparatus For Data Transmission/Reception By Using CPU Peripheral Bus In Exchange System - Google Patents

Abstract

PURPOSE: An apparatus for transmitting and receiving data using a CPU peripheral bus for a switch is provided for integrating a plurality of buffers and resistors which form a CPU peripheral bus into one chip. CONSTITUTION: There are provided a CPU(100), a PLD(Programmable Logic Device)(110), a switching unit(120), a controller(130) and a memory unit(140). The CPU supplies data to the controller or supplies the data to the memory unit through the switching units. The PKD(20) generates a control signal in accordance with a corresponding address based on the address transmitted from the CPU through an address bus(IA) for thereby controlling the switching unit(120). The controller receives an address and data transmitted from the CPU through the address bus(MA) and data bus(MD) and the switching unit(120).

Description

Apparatus For Data Transmission / Reception By Using CPU Peripheral Bus In Exchange System}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for transmitting and receiving data using a CPU peripheral bus in an exchange, and more particularly, to a data transmitting / receiving apparatus using an CPU peripheral bus in an exchange to single chip a plurality of buffers and resistors constituting a CPU peripheral bus.

In general, modern communication equipment as well as large-scale systems such as exchangers have a CPU on board to perform additional functions besides the basic transfer function, but not only to generate new information by manipulating the data transmitted from the CPU. In addition, since it controls many controllers, it is operated by multiple bus structures between the CPU and multiple controllers.

As an example of such a data transmission / reception system using a peripheral bus of a CPU in a conventional exchange, as shown in FIG. 1, the CPU 10, the PLD (Programmable Logic Device) 20, and the buffer units 31 to 34 are shown. And a control unit 40 and a memory unit 50.

The buses connecting the devices include IA, which is an address bus of the CPU 10, ID, which is a data bus, PA, which is an address bus of the memory unit 50, PD, which is a data bus, and the controller 40. MA, which is an address bus, and MD, which is a data bus, are constituted.

The CPU 10 supplies data to the controller 40 through the buffer units 31 to 34 through the address bus IA and the data bus ID allocated thereto, or the buffer units 31 and 33. The data is supplied to the memory section 50 via.

The PLD 20 looks at an address transmitted from the CPU 10 through the address bus IA, generates a control signal according to a predetermined address map, and controls the buffer units 31 to 34.

The controller 40 receives an address and data transmitted from the CPU 10 via the buffer units 31 to 34 through an address bus MA and a data bus MD allocated thereto, or the CPU Send to (10).

The memory unit 50 receives the address and data transmitted from the CPU 10 via the buffer units 31 and 33 through the address bus PA and the data bus PD allocated thereto, It transmits to CPU10.

When the buffer units 31 to 34 are enabled by the / OE signals of the buffer units 31 and 33 by the control signal transmitted from the PLD 20 and the data transfer direction of the buffer unit 33 is determined, The address and data transmitted from the CPU 10 are supplied to the memory unit 50, and the / OE signals of all the buffer units 31 to 34 are enabled by the control signal transmitted from the PLD 20. When the data transfer direction of the buffer units 33 and 34 is determined, the address and data transferred from the CPU 10 are supplied to the control unit 40 side.

As described above, an operation of transmitting an address and data through a peripheral bus of a conventional CPU will be described.

First, when the CPU 10 connects the memory unit 50 to transfer the address and data, it transfers the address and data to the buffer units 31 to 34 through the address bus IA and the data bus ID. do.

At this time, the PLD 20 refers to an address transmitted through the address bus IA of the CPU 10 according to a predetermined address map, and the / of the first buffer unit 31 and the third buffer unit 33 are changed. At the same time as the OE (Output Enable) signal is activated, the DIR signal is transmitted to the third buffer unit 33 to determine the data transmission direction. Then, the / OE signals of the second buffer portion 32 and the fourth buffer portion 34 are deactivated.

Here, since the address bus is unidirectional, the buffer units 31 and 33 are connected and disconnected according to the state of the / OE signal. However, since the data bus is bidirectional, the buffer units 32 and 34 are connected according to the state of the / OE signal. At the same time, the DIR signal is transmitted to determine the data transfer direction, and then data is written or read.

Therefore, when the / OE signal of the first buffer unit 31 and the third buffer unit 33 is activated, the address buses IA and PA and the data bus ID between the CPU 10 and the memory unit 50 are activated. , The PD is connected, transfers the address transmitted from the CPU 10 to the memo unit side 50 via the address bus PA, and transmits the data transferred from the CPU 10 to the data bus PD. Through the transmission to the memory unit 50 side.

On the other hand, when the CPU 10 is connected to the control unit 40 to transfer the address and data, the address and data are transferred to the buffer units 31 to 34 through the address bus IA and the data bus ID. .

At this time, the PLD 20 refers to an address transmitted from the CPU 10 through the address bus IA by a predetermined address map to activate the / OE signal of the buffer units 31 to 34, and The DIR signal is transmitted to the third buffer portion 33 and the fourth buffer portion 34 to determine the data transmission direction.

Here, as above, the address bus is unidirectional and connected and disconnected according to the state of the / OE signal. However, since the data bus is bidirectional, the address bus is connected and disconnected according to the state of the / OE signal. The data direction must be determined by transmission.

Accordingly, when the / OE signal of the corresponding buffer units 31 to 34 is activated, and the DIR signal is transmitted to the third buffer unit 33 and the fourth buffer unit 34, the CPU 10 and the controller 40 Address bus (IA, PA, MA) and data bus (ID, PD, MD) are connected, and the address and data transmitted from the CPU 10 are transferred via the address bus MA and data bus MD. Transmission to the control unit 50 side.

In this way, a pull-up resistor is used for a plurality of bus lines by providing a plurality of buffer units to configure a peripheral bus of a conventional CPU, and when the bus width of the device is changed, the PCB design is changed to increase the bus width by only 1 bit. Accordingly, it is necessary to modify the PCB pattern.

In addition, since there are many buffer parts and PCB patterns having the same period, there is a problem of generating a lot of electromagnetic interference (EMI).

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and by transmitting and receiving data through a single switching unit without using a plurality of buffer units in a CPU peripheral bus in an exchange, circuits to which each bus is connected are reduced, thereby causing electromagnetic waves. It aims not only to reduce obstacles, but also to reduce manufacturing costs.

1 is a block diagram showing a data transmission and reception apparatus using a CPU peripheral bus in a conventional exchange.

2 is a block diagram illustrating a data transmission and reception apparatus using a CPU peripheral bus in an exchange according to an exemplary embodiment of the present invention.

3 is a detailed block diagram illustrating the switching unit illustrated in FIG. 2.

4A and 4B are operation programs of the switching unit shown in FIG.

Explanation of symbols on the main parts of the drawings

100: CPU 110: PLD

120: switching unit 121 to 126: input and output unit

127: routing pool 130: control unit

140: memory unit

In order to achieve the above object, the present invention provides a CPU that provides addresses and data through an address bus IA and a data bus ID assigned thereto, and is transmitted from the CPU through an address bus IA. A PLD for generating a control signal according to the address and receiving an address and data transmitted from the CPU through the switching unit through an address bus MA and a data bus MD assigned thereto; And a control unit for transmitting to the CPU, and a memory unit for receiving or transmitting an address and data transmitted from the CPU via the switching unit via the address bus PA and the data bus PD assigned thereto. A data transmission / reception apparatus using an in-flight CPU peripheral bus, wherein the data is transmitted from the CPU according to a control signal transmitted from the PLD. Supplying dress and data toward the memory unit, or characterized in that it further comprises a switch which supplies the side of the controller.

On the other hand, the switching unit and a plurality of input and output unit for mapping and transmitting the applied signal; Connecting and disconnecting according to the state of address control signals inputted from the plurality of input / output units, connecting and disconnecting according to the state of data control signals inputted from the plurality of input / output units, and controlling input data direction signals. It is characterized by having a routing pool.

On the other hand, the routing pool is provided with a selection terminal of a plurality of multiplexers, it characterized in that switching to the selection terminal in accordance with the selection signal applied from the plurality of input and output units.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As an example of a data transmission / reception system using a peripheral bus of a CPU in an exchange according to the present invention, as shown in FIG. 2, a CPU 100, a programmable logic device (PLD) 110, a switching unit 120, The control unit 130 and the memory unit 140 is provided.

Here, since the bus connecting each device is the same as the conventional configuration, a description thereof will be omitted.

The CPU 10 supplies data to the control unit 40 via the switching unit 120 through the address bus IA and the data bus ID allocated thereto, or the switching units 31 and 33. The data is supplied to the memory section 50 via.

The PLD 20 looks at an address transmitted from the CPU 10 through the address bus IA, generates a control signal according to the address, and controls the switching unit 120.

The controller 40 receives an address and data transmitted from the CPU 10 via the switching unit 120 through an address bus MA and a data bus MD allocated thereto, or the CPU 10. To send).

The memory unit 50 receives the address and data transmitted from the CPU 10 via the switching unit 120 through the address bus PA and the data bus PD allocated thereto, or the CPU ( 10).

The switching unit 120 supplies the address and data transmitted from the CPU 10 to the memory unit 50 side or the control unit 40 side according to the control signal transmitted from the PLD 20. As shown in FIG. 3, a plurality of input / output units 121 to 126 and a routing pool 127 are provided.

The plurality of input / output units 121 to 126 map the applied signals to the switching unit 120.

The routing pool 127 is connected and disconnected according to the state of the address control signals input from the plurality of input / output units 121 to 126, and the state of the data control signals input from the plurality of input / output units 121 to 126. In accordance with the connection and disconnection according to the control, the input data direction signal is controlled. In addition, the routing pool 127 includes a selection terminal (not shown) of a plurality of multiplexers, and switches according to selection signals applied from the plurality of input / output units 121 to 126 to the selection terminal.

The operation of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, the CPU 100 transmits the address and data to the control unit 130 or the memory unit 140 via the switching unit 120 through the address bus IA and the data bus ID assigned thereto. The address and data are transferred through the switching unit 120 through the address bus PA and MA and the data bus PD and MD assigned to the controller 130 or the memory 140. The data is read by sending it to 100).

At this time, the PLD 110 may view a valid address transmitted from the CPU 100 through the address bus IA, and may refer to a predetermined address map, between the CPU 100 and the controller 130 or with the CPU 100. Connection and blocking of address control signals (/ IAOE, / MAOE, / PAOE) and data buses (ID, MD, PD) that determine the connection and disconnection of the corresponding address buses (IA, MA, PA) between the memory units 140 Determine the data control signal (/ IDOE, / IDOE, / PDOE) and the data transmission direction signal (/ IDDIR, / MDDIR, / PDDIR) to determine the direction of data transmission to the corresponding switching unit 120 do.

Here, when the switch unit 120 is described in detail, the switch unit 120 unifies a plurality of existing buffer units, and an operation thereof is performed by a program shown in FIG. 4, in which case shown in FIG. 4A. One program configures all I / O pins as pullups, thereby reducing the number of pullup resistors that must be attached to the bus, defining and specifying the address bus and data bus, specifying the bus properties, and specifying the actual pins of the bus. It is a program that maps and maps the signal lines and assigns them to the actual pins.

The program shown in FIG. 4B is a program for controlling the bus and actually manages the switching unit 120, and the address buses may be connected to each other, and connected using the / OE signal generated by the PLD 110. You just need to block it.

In addition, the data bus must specify a data transfer direction in both directions, where Mx (x = 0,1,2,3) means a bus and Sx (x = 0,1) means a selection terminal of the multiplexer. The signal input to Sx has three signals, / IDDIR, / PDDIR, and / MDDIR. The / PDDIR and / MDDIR indicate the same direction, so they can be used interchangeably. Thus, there are two signals that indicate the direction, and the patterns that can be represented by the two signals are 00, 01, 10, and 11, let us define Mx to achieve the desired result.

! IAOE ! MAOE ! PAOE IA => MA 0 0 One IA => PA 0 One 0

! IDOE ! MDOE ! PDOE ! IDDIR ! MDDIR ! PDDIR ID => MD 0 0 One 0 0 x ID => PD 0 One 0 0 x 0 MD => ID 0 0 One One One 0 PD => ID 0 One 0 One 0 One

Table 1 shows an address control signal for controlling the address bus, and Table 2 shows a data control signal and a data transmission direction control signal for controlling the data bus.

Then, when writing data from the first CPU to the controller side with reference to the programs shown in Table 1, Table 2, and FIG. 4, the corresponding switching unit 120 is set by the state of the address control signal transmitted from the PLD 110. When the / IAOE signal of the first input / output unit 121 and the / MAOE signal of the fifth input / output unit 125 are enabled, the IA and the MA, which are address buses, are connected in the routing pool 127 in the corresponding switching unit 120. .

At the same time, the switching unit 120 enables the / IDOE signal of the second input / output unit 122 and the / MDOE signal of the sixth input / output unit 126 by the state of the data control signal transmitted from the PLD 110. In this case, the routing pool 127 in the switching unit 120 connects the ID and the MD which are the data buses. In this case, since the data buses are bidirectional, the data is transmitted by the selected data transmission direction signal transmitted from the corresponding PLD 110. Will determine the direction. That is, since the ID is connected to the MO in the MD with reference to Table 2 and FIG. 4B, the / IDDIR signal and the / MDDIR signal are set to 00 in order to select the MO among four Mx (x = 0, 1, 2, 3). The selection signals SO and S1 are required, and the corresponding / IDDIR and / MDDIR signals are connected as the selection signals SO and S1 are transmitted.

Second, when the CPU transmits an address and data from the CPU to the memory unit, the switching unit 120 transmits the / IAOE signal of the first input / output unit 121 and the third by the state of the address control signal transmitted from the PLD 110. When the / PAOE signal of the input / output unit 125 is enabled, the address bus IA and PA are connected in the routing pool 127 in the switching unit 120.

At the same time, the switching unit 120 switches if the / IDOE signal of the second input / output unit 122 and the / MDOE signal of the fourth input / output unit are enabled by the state of the data control signal transmitted from the PLD 110. In the routing pool 127 in the unit 120, the data bus ID and the PD are connected. In this case, since the data bus is bidirectional, the data transfer direction is determined by the selected data transfer direction signal transmitted from the PLD 110. . That is, since the ID is connected to the MO with reference to Table 2 and FIG. 4B, the / IDDIR and / PDDIR signals are set to 00 in order to select the MO among four Mx (x = 0, 1, 2, 3). The selection signals SO and S1 are required, and the corresponding / IDDIR and / PDDIR signals are connected as the selection signals SO and S1 are transmitted.

Third, when the CPU side receives the address and data from the controller side, the corresponding switching unit 120 is connected to the / IAOE signal of the fifth input / output unit 125 by the state of the address control signal transmitted from the PLD 110. When the / PAOE signal of the first input / output unit 121 is enabled, the IA and the MA, which are address buses, are connected in the routing pool 127 in the switching unit 120.

At the same time, the switching unit 120 enables the / IDOE signal of the sixth input / output unit 126 and the / MDOE signal of the second input / output unit 122 by the state of the data control signal transmitted from the PLD 110. In the routing pool 127 in the switching unit 120, ID and MD, which are data buses, are connected. In this case, since the data bus is bidirectional, the data transmission direction is selected by the selected data transmission direction signal transmitted from the PLD 110. Will be determined. That is, referring to Table 2 and FIG. 4B, since the MD is connected to M1 in the ID, the / IDDIR signal and the / PDDIR signal are set to 01 in order to select M1 among four Mx (x = 0, 1, 2, 3). A selection signal is required because the inverse of the MDDIR signal is input. As the selection signal is transmitted, the corresponding / IDDIR signal and the / PDDIR signal are connected.

At this time, since the / PDDIR signal indicates the same direction as / MDDIR, it can be used interchangeably.

Fourth, when the CPU receives the address and data from the memory unit side, the corresponding switching unit 120 receives the IAOE signal and the first input / output unit of the third input / output unit 123 by the address control signal transmitted from the PLD 110. When the / PAOE signal of 121 is enabled, IA and PA, which are address buses, are connected in the routing pool 127 in the switching unit 120.

At the same time, when the / IDOE signal of the fourth input / output unit 124 and the / PDOE signal of the second input / output unit 122 are enabled by the data control signal transmitted from the PLD 110, the corresponding switching unit 120, In the routing pool 127 in the switching unit 120, the PD and ID, which are data buses, are connected. In this case, since the data bus is bidirectional, the data transfer direction is determined by the selected data transfer direction signal transmitted from the corresponding PLD 110. Will be decided. That is, referring to Table 2 and FIG. 4B, since the PD is connected to M3 in the ID, the / IDDIR signal and the / PDDIR signal are set to 11 in order to select M3 among four Mx (x = 0, 1, 2, 3). The selection signal is required, and the corresponding / IDDIR signal and the / PDDIR signal are connected as the selection signal is transmitted.

As described above, the present invention transmits and receives data through a single switching unit without using a plurality of buffer units in the CPU peripheral bus in the exchange, thereby reducing the circuits to which each bus is connected and thereby reducing electromagnetic interference. The manufacturing cost can be reduced.

Claims (3)

CPU which provides address and data through address bus (IA) and data bus (ID) assigned to it, A PLD for viewing an address transmitted from the CPU via an address bus IA and generating a control signal according to the address; A control unit which receives or transmits an address and data transmitted from the CPU via the switching unit via an address bus MA and a data bus MD assigned thereto, Data using the CPU peripheral bus in the exchange having the memory unit for receiving or transmitting the address and data transmitted from the CPU via the switching unit via the address bus PA and the data bus PD assigned to the CPU. In the transceiver, And a switching unit for supplying an address and data transmitted from the CPU to the memory unit or a controller for supplying the address and data transmitted from the CPU to the control unit according to a control signal transmitted from the PLD. The method of claim 1, The switching unit comprises a plurality of input and output unit for mapping and transmitting the applied signal; Connecting and disconnecting according to the state of address control signals inputted from the plurality of input / output units, connecting and disconnecting according to the state of data control signals inputted from the plurality of input / output units, and controlling input data direction signals. A data transmitting / receiving device using a CPU peripheral bus in an exchange, comprising a routing pool. The method of claim 2, The routing pool includes a selection terminal of a plurality of multiplexers, and the data transmission and reception apparatus using a CPU peripheral bus in the switch, characterized in that for switching according to the selection signal applied from the plurality of input and output units.