KR20000059991A - method for forming heat sink of PBGA package using metal grain injection - Google Patents
method for forming heat sink of PBGA package using metal grain injection Download PDFInfo
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- KR20000059991A KR20000059991A KR1019990007965A KR19990007965A KR20000059991A KR 20000059991 A KR20000059991 A KR 20000059991A KR 1019990007965 A KR1019990007965 A KR 1019990007965A KR 19990007965 A KR19990007965 A KR 19990007965A KR 20000059991 A KR20000059991 A KR 20000059991A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
본 발명은 메탈 그레인 분사 방식을 이용한 피·비·지·에이 패키지의 히트싱크 형성방법에 관한 것으로서, 더욱 상세하게는 피·비·지·에이 패키지의 제조를 위한 패키징 도중에 메탈 그레인(metal grain)을 분사하여 히트싱크를 형성하므로써 패키지 공정 완료 후에 별도로 히트싱크를 부착하지 않아도 되도록 함과 더불어 방열성을 향상시킨 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a heat sink of a PB package using metal grain injection, and more particularly, to a metal grain during packaging for manufacturing PB package. By spraying to form a heat sink, after the package process is completed, it is not necessary to attach a heat sink separately, and heat dissipation is improved.
일반적으로, 비·지·에이 패키지는 히트싱크가 구비되지 않은 피·비·지·에이 패키지(PBGA : Plastic Ball Grid Array package)와 히트싱크가 구비된 에스·비·지·에이 패키지(SBGA : Super Ball Grid Array package)로 나뉜다.In general, a BG package includes a plastic ball grid array package (PBGA) without a heat sink and a SBGA package (SBGA) with a heat sink. Super Ball Grid Array package).
한편, 종래 피·비·지·에이 패키지의 제조 과정은 다음과 같다.On the other hand, the manufacturing process of the conventional B, G, A package is as follows.
먼저, 피·비·지·에이 패키지제조를 위한 회로 기판(1)에 도 1a와 같이 칩(2)을 부착한 후에는, 도 1b에 나타낸 바와 같이 와이어 본딩을 수행하게 된다.First, after the chip 2 is attached to the circuit board 1 for manufacturing a B, G, and A package as shown in FIG. 1A, wire bonding is performed as shown in FIG. 1B.
이어, 칩(2) 및 골드 와이어(3)를 외부로부터 보호하기 위해 도 1c와 같이 엔캡슐레이팅(encapsulating)을 진행하게 된다.Subsequently, in order to protect the chip 2 and the gold wire 3 from the outside, encapsulating is performed as shown in FIG. 1C.
엔캡슐레이팅 완료 후에는 도 1d와 같이 스트립 상의 피·비·지·에이 패키지를 낱개로 분리시키는 싱귤레이션(singulation)을 진행하고, 그 다음 상기 기판(1) 하면의 솔더볼 부착 위치에 솔더볼(6)을 부착하게 되며, 이로써 패키지 단품이 완성된다.After encapsulation is completed, singulation is performed to separate the P, B, G, and A packages on the strip individually, as shown in FIG. 1D. Then, the solder balls 6 are placed at the solder ball attachment position on the bottom surface of the substrate 1. ), Which completes the package unit.
한편, 이와 같이 완성된 피·비·지·에이 패키지는 방열을 위한 히트싱크가 구비되어 있지 않으므로, 방열성을 좋게 하기 위해 별도로 제작된 히트싱크(9a)를 패키지의 톱(top)면에 부착하였다.On the other hand, the P, B, G, and A packages thus completed do not have a heat sink for heat dissipation. Therefore, a heat sink 9a, which is separately manufactured, is attached to the top surface of the package to improve heat dissipation. .
즉, 도 2에 나타낸 바와 같이 피·비·지·에이 패키지 톱면에 양면 테이프(10)를 부착하고, 상기 양면 테이프 위에 히트싱크(9a)를 부착하므로써 방열성능을 증대시켰다.That is, as shown in FIG. 2, the double-sided tape 10 was attached to the top surface of the P, B, G-A package, and the heat sink 9a was attached to the double-sided tape to increase the heat dissipation performance.
그러나, 이와 같은 종래의 피·비·지·에이 패키지는 히트싱크(9a)가 패키지 제조 과정이 아닌 패키지 완성 후 별도의 부착 공정을 통해 부착되어야 하므로 공정이 번거러워지는 단점이 있었다.However, such a conventional B, B, G, and A package has a disadvantage in that the heat sink 9a must be attached through a separate attaching process after the package is completed, rather than a package manufacturing process.
또한, 상기 히트싱크(9a)는 피·비·지·에이 패키지의 톱면에 바로 부착되지 못하고, 양면 테이프(10)를 매개로하여 부착되므로 인해, 상기 히트싱크(9a)로의 열전달이 원할하게 이루어지지 않아 열방출 효과가 떨어지게 되는 문제점이 있었다.In addition, since the heat sink 9a is not directly attached to the top surface of the P, B, G, or A package, and is attached via the double-sided tape 10, heat transfer to the heat sink 9a is smoothly performed. There was a problem that the heat release effect is not reduced.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 피·비·지·에이 패키지의 제조를 위한 패키징 도중에 메탈 그레인을 분사하여 히트싱크를 형성하므로써 패키지 공정 완료 후에 별도로 히트싱크를 부착하지 않아도 되도록 함과 더불어 방열성을 향상시킬 수 있도록 한 피·비·지·에이 패키지의 히트싱크 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above-mentioned problems, by forming a heat sink by spraying the metal grain during the packaging for the manufacture of P, B, G package so that it does not need to attach a heat sink separately after the completion of the package process In addition, the object of the present invention is to provide a heat sink forming method of a P, B, G, A package to improve heat dissipation.
도 1a 내지 도 1f는 종래 피·비·지·에이 패키지의 제조 과정을 나타낸 것으로서,1A to 1F illustrate a process of manufacturing a conventional B, G, and A package,
도 1a는 다이본딩 후의 상태를 나타낸 평면도1A is a plan view showing a state after die bonding
도 1b는 와이어 본딩 후의 상태를 나타낸 평면도1B is a plan view showing a state after wire bonding
도 1c는 엔캡슐레이팅후의 상태를 나타낸 평면도1C is a plan view showing a state after encapsulation
도 1d는 싱귤레이션된 후의 피·비·지·에이 패키지 단품을 나타낸 평면도FIG. 1D is a plan view showing a P, B, A package unit separately after singulation
도 1e는 도 1d의 정면도FIG. 1E is a front view of FIG. 1D
도 1f는 볼 부착 후의 상태를 나타낸 정면도1F is a front view showing a state after ball attachment
도 2는 종래 피·비·지·에이 패키지에 히트싱크가 부착된 상태를 나타낸 정면도2 is a front view showing a state in which a heat sink is attached to a conventional B, B, G, and A package.
도 3a 내지 도 3i는 본 발명의 피·비·지·에이 패키지 제조 과정을 나타낸 것으로서,3A to 3I illustrate a process of manufacturing P, B, A package of the present invention.
도 3a는 다이본딩 후의 상태를 나타낸 평면도3A is a plan view showing a state after die bonding.
도 3b는 와이어 본딩 후의 상태를 나타낸 평면도3B is a plan view showing a state after wire bonding
도 3c는 엔캡슐레이팅후의 상태를 나타낸 평면도3C is a plan view showing a state after encapsulation
도 3d는 도 3c의 정면도3D is a front view of FIG. 3C
도 3e는 메탈 그레인을 분사하고 있는 상태를 나타낸 정면도3E is a front view showing a state in which metal grain is being sprayed
도 3f는 메탈 그레인 분사후의 상태를 정면도3F is a front view of a state after metal grain injection
도 3g는 싱귤레이션된 후의 피·비·지·에이 패키지 단품을 나타낸 평면도3G is a plan view showing a P, B, G, and A package separately after singulation
도 3h는 도 3g의 정면도3H is a front view of FIG. 3G
도 3i는 볼 부착 후의 상태를 나타낸 정면도3i is a front view showing a state after ball attachment
도 3j는 도 3i의 요부 단면도FIG. 3J is a cross-sectional view of main parts of FIG. 3I
도 4는 본 발명의 다른 실시예를 나타낸 정면도Figure 4 is a front view showing another embodiment of the present invention
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:회로 기판 2:칩1: circuit board 2: chip
3:골드 와이어 4:엔캡슐런트3: gold wire 4: encapsulant
5:메탈 인젝터 6:솔더볼5: metal injector 6: solder ball
7:메탈 그레인 8:전도성 페이스트7: Metal grain 8: Conductive paste
9:히트싱크9: Heatsink
상기한 목적을 달성하기 위해, 본 발명은 피·비·지·에이 패키지 제조용 회로 기판에 칩을 본딩하는 단계와, 상기 칩의 본딩패드와 회로 기판의 소정의 본딩영역 사이를 골드와이어를 이용하는 본딩하는 단계와, 상기 칩과 골드와이어를 엔캡슐런트를 이용하여 엔캡슐레이팅하는 단계와, 엔캡슐레이팅 완료 후 회로기판 상에 솔더볼을 부착하는 단계로 이루어진 피·비·지·에이 패키지 제조 방법에 있어서; 엔캡슐레이팅 진행시, 상기 엔캡슐런트가 반(半)쯤 경화된 상태에서 메탈 인젝터로 메탈 그레인을 피·비·지·에이 패키지 톱(top)면에 분사하여 히트싱크를 형성하는 단계가 추가적으로 포함됨을 특징으로 하는 메탈 그레인 분사 방식을 이용한 피·비·지·에이 패키지의 히트싱크 형성방법이 제공된다.In order to achieve the above object, the present invention provides a method for bonding a chip to a circuit board for manufacturing a P, B, A package, and bonding using a gold wire between a bonding pad of the chip and a predetermined bonding area of the circuit board. And encapsulating the chip and the gold wire using an encapsulant, and attaching solder balls onto a circuit board after the encapsulation is completed. In; During encapsulation, the step of forming a heat sink by injecting metal grain onto the top surface of the B, B, G, and A packages with a metal injector while the encapsulant is cured about half way Provided is a method for forming a heatsink of a P, B, G, and A package using a metal grain injection method.
이하, 본 발명의 일실시예를 첨부도면 도 3a 내지 도 3j를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3J.
도 3a 내지 도 3j는 본 발명의 피·비·지·에이 패키지 제조 과정을 나타낸 것으로서, 본 발명의 피·비·지·에이 패키지 제조 과정중 피·비·지·에이 패키지 제조용 회로기판(1) 스트립에 각각 칩(2)을 본딩하고(도 3a), 각 칩(2)의 본딩패드(도시는 생략함)와 회로기판(1)의 소정의 영역간을 와이어(3)로 본딩(도 3b) 하기까지의 과정은 종래의 피·비·지·에이 패키지 제조 과정과 동일하다.3A to 3J illustrate a manufacturing process of a B, G, and A package of the present invention, and a circuit board for manufacturing a B, G, and A package of the B, G, and A package of the present invention (1). Bonding the chips 2 to the strips (FIG. 3A) and bonding the bonding pads (not shown) of each chip 2 to the predetermined regions of the circuit board 1 with the wires 3 (FIG. 3B). The process up to now is the same as the conventional manufacturing process of P, B, G, and A packages.
그러나, 본 발명은 상기 칩(2) 및 와이어(3)를 엔캡슐런트(4)(encapsulant)를 이용하여 엔캡슐레이팅한 후의 과정이 종래의 피·비·지·에이 패키지 제조 과정과 달라지게 된다.However, in the present invention, the process after encapsulating the chip 2 and the wire 3 using an encapsulant is different from the conventional P, B, G package manufacturing process. do.
즉, 엔캡슐런트(4)를 이용하여 상기 칩(2) 및 와이어(3)를 도 3c 및 도 3d와 같이 엔캡슐레이팅하는 공정 진행시, 엔캡슐런트(4)는 시간의 경과에 따라 경화되는데, 이 때 본 발명에서는 엔캡슐런트(4)가 완전히 굳어지기 전에 도 3e에 나타낸 바와 같이 메탈 인젝터(5)를 이용하여 메탈 그레인(7)을 피·비·지·에이 패키지의 톱 면에 분사하게 된다.That is, during the process of encapsulating the chip 2 and the wire 3 using the encapsulant 4 as shown in FIGS. 3C and 3D, the encapsulant 4 hardens over time. In this case, in the present invention, before the encapsulant 4 is completely hardened, as shown in FIG. 3E, the metal grains 7 are applied to the top surface of the P, B, G, and A packages using the metal injector 5. To be sprayed.
그 후, 분사된 메탈 그레인(7)은 경화되어 도 3f에 나타낸 바와 같이 히트싱크를 이루게 된다.Thereafter, the injected metal grain 7 is cured to form a heat sink as shown in FIG. 3F.
한편, 메탈 그레인(7)이 경화된 후에는 도 3g 및 도 3h에 나타낸 바와 같이 스트립 상태의 피·비·지·에이 패키지를 단품으로 분리시키는 싱귤레이션 작업을 행한 후, 도 3i와 같이 회로기판(1) 저면에 볼을 부착하므로써 피·비·지·에이 패키지 단품을 완성하게 된다.On the other hand, after the metal grain 7 has been cured, as shown in FIGS. 3G and 3H, a singulation operation for separating the P, B, G, and A packages in a strip form into pieces is performed. (1) By attaching the ball to the bottom, the B, B, G, and A packages can be completed.
따라서, 본 발명의 피·비·지·에이 패키지는 메탈 그레인(7)과 엔캡슐런트(4)가 도 3j의 요부 단면도에 나타낸 바와 같이 상호간에 직접 접촉되므로 인해, 기존의 양면 테이프(10)를 사용하여 히트싱크(9a)를 부착하던 피·비·지·에이 패키지에 비해 열방출 효과가 현저히 향상된다.Therefore, the B, G, and A packages of the present invention have a conventional double-sided tape 10 because the metal grains 7 and the encapsulant 4 are in direct contact with each other as shown in the main cross-sectional view of FIG. 3J. The heat dissipation effect is remarkably improved compared to the P, B, G, and A packages to which the heat sink 9a is attached by using.
한편, 도 4는 본 발명의 다른 실시예를 나타낸 정면도로서, 메탈 그레인(7) 분사에 의해 형성된 히트싱크 상면에 전도성 페이스트(8)를 도포한 후, 상기 전도성 페이스트(8)상에 별도로 제작된 히트싱크(9)를 부착한 경우를 나타낸 것이다.On the other hand, Figure 4 is a front view showing another embodiment of the present invention, after applying the conductive paste (8) to the upper surface of the heat sink formed by the injection of the metal grain (7), and separately produced on the conductive paste (8) The case where the heat sink 9 is attached is shown.
이 경우 역시, 메탈 그레인(7)과 엔캡슐런트(4)가 직접 접촉되고, 전도성 페이스트(8)(conductive paste)에 의해 또 하나의 히트싱크(9)가 부착되므로 인해, 기존의 양면 테이프를 사용하여 히트싱크를 부착한 경우에 비해 열방출 효과를 향상시킬 수 있게 된다.In this case, too, since the metal grain 7 and the encapsulant 4 are in direct contact with each other and the second heat sink 9 is attached by the conductive paste 8, the existing double-sided tape is removed. The heat dissipation effect can be improved as compared with the case where the heat sink is attached.
이상에서와 같이, 본 발명은 피·비·지·에이 패키지의 제조를 위한 패키징 도중에 메탈 그레인을 분사하여 히트싱크를 형성하므로써 패키지 공정 완료 후에 별도로 히트싱크를 부착하지 않아도 되어 공정을 단순화할 수 있음과 더불어 피·비·지·에이 패키지의 방열성을 향상시킬 수 있게 된다.As described above, the present invention can simplify the process by eliminating the need to attach a heat sink after the completion of the package process by forming a heat sink by spraying metal grains during the packaging for manufacturing the P, B, G and A packages. In addition, the heat dissipation of the P, B, G, and A packages can be improved.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990007965A KR20000059991A (en) | 1999-03-10 | 1999-03-10 | method for forming heat sink of PBGA package using metal grain injection |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990007965A KR20000059991A (en) | 1999-03-10 | 1999-03-10 | method for forming heat sink of PBGA package using metal grain injection |
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| KR20000059991A true KR20000059991A (en) | 2000-10-16 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100790461B1 (en) * | 2006-11-13 | 2008-01-02 | 삼성전기주식회사 | Method for manufacturing electronic package |
| US7388286B2 (en) | 2005-01-05 | 2008-06-17 | Samsung Electronics Co., Ltd. | Semiconductor package having enhanced heat dissipation and method of fabricating the same |
| KR101454078B1 (en) * | 2012-11-16 | 2014-10-27 | 삼성전기주식회사 | Power semiconductor device and method of manufacturing the same |
-
1999
- 1999-03-10 KR KR1019990007965A patent/KR20000059991A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7388286B2 (en) | 2005-01-05 | 2008-06-17 | Samsung Electronics Co., Ltd. | Semiconductor package having enhanced heat dissipation and method of fabricating the same |
| KR100790461B1 (en) * | 2006-11-13 | 2008-01-02 | 삼성전기주식회사 | Method for manufacturing electronic package |
| KR101454078B1 (en) * | 2012-11-16 | 2014-10-27 | 삼성전기주식회사 | Power semiconductor device and method of manufacturing the same |
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