US20190035669A1 - Semiconductor package with individually molded leadframe and die coupled at solder balls - Google Patents

Semiconductor package with individually molded leadframe and die coupled at solder balls Download PDF

Info

Publication number
US20190035669A1
US20190035669A1 US15/663,624 US201715663624A US2019035669A1 US 20190035669 A1 US20190035669 A1 US 20190035669A1 US 201715663624 A US201715663624 A US 201715663624A US 2019035669 A1 US2019035669 A1 US 2019035669A1
Authority
US
United States
Prior art keywords
semiconductor die
solder
molding compound
leadframe
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US15/663,624
Other versions
US10204814B1 (en
Inventor
Jefferson Talledo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMICROELECTRONICS INTERNATIONAL NV
Original Assignee
STMicroelectronics Inc Philippines
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Inc Philippines, STMicroelectronics lnc USA filed Critical STMicroelectronics Inc Philippines
Priority to US15/663,624 priority Critical patent/US10204814B1/en
Assigned to STMICROELECTRONICS, INC. reassignment STMICROELECTRONICS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TALLEDO, JEFFERSON
Priority to CN201810804209.1A priority patent/CN109309010A/en
Publication of US20190035669A1 publication Critical patent/US20190035669A1/en
Application granted granted Critical
Publication of US10204814B1 publication Critical patent/US10204814B1/en
Assigned to STMICROELECTRONICS INTERNATIONAL N.V. reassignment STMICROELECTRONICS INTERNATIONAL N.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STMICROELECTRONICS, INC.
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/16257—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/16258—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • This disclosure is in the field of semiconductor packages, and in particular, is directed towards a semiconductor package in which the leadframe and semiconductor package are each molded separately, then are joined together with solder balls.
  • Semiconductor packages must protect the semiconductor die from the external environment while providing an output at the electrical signals for use by other circuits.
  • the package therefore, must be sufficiently protective and robust to prevent damage to the semiconductor die, while at the same time providing electrical connections so the signals may be received by and sent out from the semiconductor die.
  • a semiconductor die is placed on a leadframe or other substrate, and it is then electrically connected to this leadframe by bonding wires, solder balls, or other electrical coupling.
  • the combination is placed in a mold, and a molding compound injected into the mold to fully encase the die, but leave some of the electrical connections exposed so that it may be connected to the outside environment.
  • a molding compound injected into the mold to fully encase the die, but leave some of the electrical connections exposed so that it may be connected to the outside environment.
  • a leadframe array for a semiconductor die is prepared having locations to receive solder balls. Solder balls are then applied to the leadframe array, after which the leadframe array and solder ball combination is placed in a first mold and encased in a first molding compound. In one embodiment, the solder balls are fully encased in molding compound so as to be completely surrounded by the molding compound.
  • the molding compound is cured, a layer of molding compound is removed to expose the solder balls.
  • a semiconductor die is electrically connected to the exposed solder balls.
  • the combined semiconductor die and leadframe are placed in a second mold, and a second molding compound injected.
  • the second molding compound flows around the semiconductor die and leadframe combination, fully enclosing the electrical connections between the leadframe and the semiconductor die, making the final package a twice-molded configuration. After this, the twice-molded semiconductor package array is cut at the appropriate locations to singulate the packages into individual products.
  • the present method permits the leadframe array to be fully constructed, encapsulated, and provided with electrical connections in a separate manufacturing line, prior to the introduction of the semiconductor die. Only after the leadframe array is encapsulated is the semiconductor die connected to the leadframe, thus providing a more rapid, and lower cost, technique for attaching the die to the leadframe.
  • the leadframe is an array of leadframes, having many hundreds, or many thousands, of positions for a die. Accordingly, the package can be mass-produced with thousands of semiconductor die attached to the array of leadframes, after which the combination is placed in a second mold, encapsulated in a second molding compound and then singulated.
  • FIG. 1 is a cross-sectional view of a completed semiconductor package according to principles disclosed herein.
  • FIG. 2 is a cross-sectional view of an alternative embodiment of a semiconductor package according to principles disclosed herein.
  • FIG. 3 is a cross-sectional view of yet another alternative embodiment according to principles disclosed herein.
  • FIGS. 4-8 are cross-sectional views of the process steps for making a semiconductor package according to principles as taught herein.
  • FIG. 9 is a cross-sectional view of an end package after the final step of FIG. 8 .
  • FIG. 10 is a flow chart of the sequence of making a twice-molded package.
  • FIG. 1 is a cross-sectional view of a twice-molded semiconductor chip package 10 according to principles as taught herein.
  • the package 10 includes a semiconductor die 12 which is encased in a molding compound 16 .
  • Solder bumps 14 extend from pads on the semiconductor die 12 to provide electrical connections to the circuits thereon.
  • a leadframe 18 is separately encased in its own molding compound 24 .
  • the leadframe 18 has solder balls 22 , which are electrically connected to the solder bumps 14 extending from the semiconductor die 12 .
  • a conductive layer 20 extends along an exposed surface of leadframe 18 .
  • the layer 20 is composed of one or more layers of material which are electrically conductive and provide, in most embodiments, a solderable metal in order to solder the twice-molded package 10 to a printed circuit board or other substrate for use in a larger circuit.
  • solder bump 14 extending from the semiconductor die 12 and the solder ball 22 extending from the leadframe 18 are joined as an integral, single solder ball 28 , which provides a contiguous single metal connection between the semiconductor die 22 and the leadframe 18 .
  • the single electrical connection 28 is achieved by reflowing the solder bumps 14 and 22 together at a temperature that approaches their melting point, in order to join them as a single, continuous solder ball connection.
  • the molding compound 16 completely encases and fully surrounds semiconductor die 12 . This isolates semiconductor die 12 from the outside environment, blocking electrical access, moisture ingress, and providing mechanical coupling to the leadframe molding compound 24 .
  • FIG. 2 shows a low-profile package 11 , which is an alternative embodiment of the twice-molded semiconductor package 10 of FIG. 1 .
  • FIG. 2 illustrates a semiconductor die 12 coupled to a leadframe 18 in a similar manner to the package shown in FIG. 1 .
  • the molding compound 16 extends along the sides of the semiconductor die 12 but does not fully surround or encase the semiconductor die 12 . Rather, the molding compound 16 extends completely between the semiconductor die 12 and the leadframe 18 and along the sidewalls of the semiconductor die, but does not cover the back side of the die 12 .
  • the package 11 as shown in FIG. 2 , has the benefit that it can be made substantially thinner than the package of FIG. 1 . It is useful in those embodiments where a low-profile package is desired.
  • the low-profile package 11 can be manufactured by a number of different techniques. It can be made using the process as shown in FIGS. 4-8 as explained herein, with the modification that, when the joint die and leadframe combination is placed in the mold, the shape of the mold ensures that the molding compound 16 only extends along the sidewalls of the die 12 , and is blocked from going across the back of the die 12 .
  • An alternative method for producing the low-profile package 11 of FIG. 2 is to follow the same method steps used as making the package of FIG. 1 and, after the package is fully completed, milling off the top section of the semiconductor die 12 , and along with the molding compound 27 . Namely, when the manufacturing process is in the stage as shown in FIG.
  • the subsequent step is to remove the top section of the package. This can be done by sawing, milling, grinding, polishing, use of CMP, or other acceptable technique to perform a blanket removal of the top portion of the molding compound 27 , and then, after all the top layer of molding compound 16 is removed, and then upon exposure of the semiconductor die 12 , terminate removal of the molding compound 27 .
  • the exposure of the semiconductor die 12 can act as a stopping layer on which the removal of the molding compound 16 takes place.
  • an ultrathin, extremely low-profile package 11 the removal of the package can continue significantly past when the semiconductor die 12 is exposed, to remove substantial portions of the semiconductor die 12 , together with the molding compound 27 .
  • the blanket removal of the top side of the package can continue to remove a significant height of the semiconductor die 12 along with the molding compound 27 to substantially reduce the profile of the overall package.
  • an ultrathin package can be obtained, in which the semiconductor die 12 has approximately half or even one-third of its standard height, and the molding compound 27 is flush with the top of the semiconductor die 12 in the final ultrathin package 11 , as shown in FIG. 2 .
  • FIG. 3 illustrates a further alternative embodiment of a minimally molded package 13 having the semiconductor die 12 coupled to the leadframe 18 .
  • the semiconductor die 12 is coupled to the leadframe 18 and the molding compound 24 by a thin underfill 31 which extends only between the die 12 and the molding compound 24 .
  • the underfill 31 does not extend along the sidewalls or the back of the die 12 , rather it extends only between the die 12 and the molding compound 24 in order to fully enclose and protect the solder bumps 14 .
  • the leadframe portion of FIG. 3 is similar to that as explained in FIG.
  • solder balls 22 namely having a leadframe 18 of a first metal, such as copper, a coating layer 20 of a second metal, such as nickel, or a combination of nickel, palladium, and gold, and solder balls 22 .
  • a molding compound 24 encases the solder balls 22 and the leadframe 18 .
  • the solder bumps 14 extending from the semiconductor 12 has been reflowed with the solder ball 22 to create a single integral solder ball 28 that extends from the semiconductor die 12 to the leadframe 18 .
  • FIGS. 2 and 3 are beneficial in some particular environments in which it is desired to have some portion of the semiconductor die 12 exposed.
  • some packages such as gas composition sensors, temperature sensors, optical readers, fingerprint readers, capacitive sensors, and other designs
  • the embodiments of FIGS. 2 and 3 provide a twice-molded encapsulation package which also permits the semiconductor die 12 to have one or more surfaces exposed to an ambient atmosphere in those embodiments in which it desired because of the design or function of die 12 .
  • They also provide embodiments of an ultrathin package having a low profile which is desired in some end products, such as a wrist watch, wearable clothing, attachment to eyewear, a credit card, or other ultrathin environment in which a low profile packaged semiconductor chip is desired.
  • FIGS. 4-8 illustrate one method of making the twice-molded semiconductor package 10 as shown in FIG. 1 , as well as the alternative embodiments of the packages 11 and 13 as shown in FIGS. 2 and 3 .
  • FIG. 4 shows a leadframe array 18 made of a first metal having a second metal coating 20 at selected locations on an exposed surface thereof.
  • the leadframe 18 can be made of any acceptable first metal such as copper, aluminum, or the like.
  • the leadframe 18 is made of copper and is a single continuous mesh that includes many hundreds or thousands of leadframes for individual semiconductor packages.
  • the second metal layer 20 will act as an etch mask for a later etch step of the leadframe 18 and, thus, is made of a second type of metal which permits selective etching of the leadframe 18 with respect to the metal 20 .
  • the metal 20 can be made of any acceptable metal, such as nickel, a trilayer coating of nickel, palladium, and gold, or other conductive layer of a type well known in the art that is preferably easily wettable by solder.
  • Layer 20 is applied as a blanket layer to the exposed surface of the leadframe 18 and patterned and etched to a desired pattern as shown in FIG. 4 using techniques well known in the art.
  • the leadframe 18 has recesses 21 formed therein at locations where it is desired to provide electrical connections to a semiconductor die.
  • the recesses 21 can be formed using a mask and etching process. Preferably, a wet etch is carried out with a proper mask in place in order to form the recesses 21 .
  • the recesses may be formed by other techniques known in the art. In the embodiment shown in FIG. 4 , the recesses 21 are semicircular because they are formed by a wet etch carried out on the leadframe 18 .
  • the recesses 21 can be rectangular, slots, grooves, or any acceptable shape. In one embodiment, they can be formed by sawing thin grooves or recesses in the leadframe 18 using a mechanical saw or other techniques known in the art for creating recesses in leadframes.
  • FIG. 5 shows the leadframe 18 after conductive solder balls 22 have been affixed thereto and then the entire leadframe array has been placed into a mold and molding compound 24 injected therein. This is carried out by, after the leadframe array is fully prepared, as shown in FIG. 4 , conductive metal, preferably solder balls 22 or other acceptable conductive metal, being placed at the prepared locations 21 in the leadframe 18 . This completes the electrical connections for the leadframe 18 .
  • the combined leadframe 18 and solder balls 22 are placed first in a mold and a first molding compound 24 inserted to encapsulate and fully enclose the upper surface of the leadframe 18 as well as the entire solder balls 22 . Sufficient molding compound is injected to ensure that the solder balls 22 are fully encased. This serves to immobilize the solder balls 22 while isolating them from the outside environment.
  • the leadframe 18 is removed from the first mold and the first molding compound cured to achieve a fully hardened molding compound 24 to obtain the structure of FIG. 5 .
  • FIG. 6 shows the upper layer of the first molding compound 24 having been removed to expose the solder balls 22 .
  • the leadframe 18 as shown in FIG. 5 is subjected to a grinding process in which the upper layer of the molding compound 24 is removed.
  • the grinding continues until the solder balls 22 are exposed and, then, continues for an additional depth in order to expose an area 28 of the solder balls 22 .
  • the grinding of the molding compound 24 continues until a significant surface area 28 of each solder ball 22 is exposed. In the embodiment shown in FIG. 6 , this continues until approximately the top one-quarter of each solder ball 22 has been removed. In some embodiments, the grinding will continue until approximately half of the solder ball 22 has been removed so that the maximum possible surface area 28 is exposed of the full diameter of the solder ball 22 .
  • additional molding compound 24 is particularly beneficial where a low profile, ultrathin package of the type shown in FIG. 2 is desired. It also provides the benefit that additional surface area is provided in the solder ball 22 to enhance the electrical connection and reduce the resistivity between the semiconductor die 12 to be attached. The amount of molding compound 24 that is removed is, therefore, selected according to the desired package design profile and resistance correction.
  • the removal of the molding compound 24 and the top portion of each solder ball 22 can be achieved by any acceptable technique, milling being a preferred technique. It can also be removed using sawing, polishing, etching (either wet etching or dry etching), grinding, or other acceptable technique in order to remove the upper portion of molding compound 24 along with a portion of each solder ball 22 .
  • FIG. 7 shows a semiconductor die 12 having solder bumps 14 .
  • This assembly is coupled to the solder balls 22 of the leadframe 18 .
  • the semiconductor die is manufactured in a different process, using techniques well known in the art.
  • the semiconductor die 12 includes a plurality of die pads, leads, or other electrical connections on a face thereof, as is known in the art.
  • Solder bumps 14 or other electrical connections, are connected to the pads 12 of the semiconductor die 12 in order to provide connections to other circuits.
  • the techniques for connecting a solder bump 14 to a semiconductor die 12 are well known in the art and, therefore, not discussed in greater detail herein. As can be appreciated, any electrical connector can be used for the solder bump 14 .
  • solder bumps 14 For example, pillars, extended contact pads, aluminum layers, or other structures known for providing an extended electrical connection of the type provided by solder bumps 14 to the semiconductor die 12 can be used.
  • the semiconductor die 12 and solder bump 14 assembly is prepared in a previous stage, and then is joined to the assembly as shown in FIG. 6 in order to achieve the assembly as shown in FIG. 7 . This is performed by a pick and place machine or other acceptable mechanical device which places the semiconductor die 12 at the correct locations having the solder bumps 14 in direct contact with the matching solder balls 22 of the leadframe 18 .
  • the solder bumps 14 and/or 18 may be slightly heated to aid in the attachment to each other. Other attachment techniques may also be used.
  • the combined semiconductor die 12 and once molded leadframe 18 are placed in a second mold.
  • a second molding compound 16 is injected into the second mold to fully encase the semiconductor die 12 and also to bond with the first molding compound 24 .
  • the second molding compound 16 is selected which will strongly adhere to and firmly mold to the first molding compound 24 .
  • the second molding compound 16 may become a unitary, contiguous molding compound with the first molding compound 24 at their junction such that the line between them is virtually invisible and indistinguishable.
  • the twice-molded assembly is provided by taking the first-molded leadframe 18 having the first molding compound 24 thereon and placing it into a second mold and then subjecting it to a second molding step, with the semiconductor die 12 attached in order to encapsulate a second time the leadframe 18 and for a first time the semiconductor die 12 .
  • the assembly is removed from the second mold and a post-mold cure is carried out to fully cure the molding compound 16 .
  • the solder bumps 14 , 22 are independent and distinct from each other.
  • the solder bump 14 that was separately formed on the semiconductor die 12 and the solder ball 22 that was previously formed and encapsulated in molding compound 24 as coupled to the frame 18 are not yet fully merged.
  • the two solder balls were brought into contact with each other before the second molding compound 16 was injected into the second mold and cured to fully surround the exposed portions of both solder bumps 14 , 22 .
  • the solder bumps 14 and 22 are in physical and electrical contact.
  • FIG. 9 shows the individual twice-molded package 10 after a subsequent solder reflow step of solder bumps 14 , 22 causes them to merge into a single, integral solder ball 28 .
  • This is performed by reheating the leadframe array having a plurality of leadframes and semiconductor die 12 connected in a large array to a reheating step that brings the solder bumps 14 , 22 to their reflow temperature at which time the solder balls merge together into a single, contiguous solder ball 28 .
  • the solder ball reflow step is preferably carried out after the assembly has been removed from the second mold and has been twice-molded.
  • the reflow temperature for the solder bumps 14 , 22 will be selected to be compatible with each other and the type of solders will be selected to merge into a single, contiguous solder ball having a final metallic alloy of a desired type.
  • the reflow step is carried out when the assembly is in the condition as shown in FIG. 7 , before the second molding compound 16 is injected.
  • a reflow step is carried out to fully and completely merge solder bumps 14 , 22 .
  • the full, high temperature reflow step is carried out, then the combined semiconductor die 12 and leadframe 18 are placed in the second mold and the second molding compound 16 is injected to achieve the final package as shown in FIG. 9 .
  • the reflow occurs in two separate steps.
  • a first step a first, minimal reflow is carried out when solder bump 14 is first brought into contact with solder ball 22 in order to adhere the two solder balls to each other and provide a strong mechanical and electrical connection.
  • a first, minimum temperature reflow occurs by slight heating of the leadframe 18 with the solder ball 22 attached so that upon the solder bumps 14 touching the heated solder balls 22 there is a slight merge between the solder balls bringing them into strong mechanical and electrical connection.
  • this initial connection is carried out just as the semiconductor die 12 is first placed on the leadframe array 18 as shown in FIG. 7 in order to provide strong mechanical coupling.
  • the heating is performed by heating the leadframe 18 and solder balls 22 , which, being made of metal, will easily transfer heat. Subsequently, the assembly is placed in the second mold and the second molding compound 16 injected. After the second molding compound has been injected, then a second, more complete and higher temperature reflow is carried out.
  • the higher temperature reflow will be at a significantly high temperature so that the solders completely merge with each other as a single contiguous piece of metal.
  • the second reflow will be a relatively high temperature compared to the first one, and often sufficiently high that the two solder materials 14 , 22 become substantially liquid.
  • solder bumps 14 , 22 might run and change shape significantly, spreading out well beyond the desired location. They may, in some instance, fail to perform the proper electrical connections or short to other adjacent solder balls. However, once the solder balls have been fully encased as shown in FIG. 8 , the movement of the solder bumps 14 , 22 is strictly limited.
  • the solder balls can be subjected to a significantly high reflow temperature, nearly to their full liquid state temperature, so that a full mixing and reflow is carried out to completely combined the two solder balls to each other into a unitary solder ball 28 as shown in FIG. 9 .
  • the two molding compounds 16 and 24 form an enclosed cavity that keeps the solder in place; even when heated.
  • the leadframe 18 is etched on the back side with an etching fluid that is selective to remove the leadframe material 18 , but not remove the metal layer 20 .
  • the leadframe 18 is made of copper, or in one embodiment aluminum.
  • a wet etch which selectively removes copper, but does not remove nickel or a nickel, palladium, gold layer combination is used. This wet etch will remove the exposed copper portions of leadframe 18 so that some of the molding compound 24 protrudes through the bottom of the package, as can be seen in FIG. 9 .
  • the package is singulated from the array to produce the final completed package 10 , as shown in FIG. 9 .
  • FIG. 10 shows a flow chart for preparing the twice-molded semiconductor package according to the embodiments as described herein.
  • the process starts at step 42 in which a leadframe is prepared and, in a completely separate process and a separate timing, a semiconductor die 12 is also prepared.
  • the leadframe array 18 is prepared to receive the solder. In this case, recesses are formed in the leadframe 18 to receive solder.
  • solder 22 is attached to the leadframe array 18 , usually as solder balls, but could be in another form as well.
  • step 48 the leadframe array 18 is placed into a first mold. Molding compound is injected to completely surround the solder balls 22 , so they are fully encased and also to cover the top surface of the leadframe array 18 .
  • step 52 the top of the completed molded leadframe is removed so as to expose portions of the encapsulated solder ball.
  • the semiconductor die 12 is electrically connected at the appropriate locations to the respective solder balls of the leadframe array 18 , as seen in step 54 .
  • a slight heating of the leadframe array 18 can take place in order to increase the adhesion or, alternatively, some adhesive material may be used that will conductively couple the die 12 to the leadframe array 18 .
  • the combination is placed into a second mold in step 56 .
  • step 58 the combination is encapsulated to affix the package which includes the leadframe array 18 and the semiconductor die 12 in a second molding compound. After this, the twice-molded packages are singulated into individual packages in step 60 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

According to principles as taught herein, a leadframe array for a semiconductor die is prepared having locations to receive solder balls. Solder balls are then applied to the leadframe array, after which the leadframe array and solder ball combination is placed in a first mold and encased in a first molding compound. After the molding compound is cured, a layer of molding compound is removed to expose the solder balls. After this, a semiconductor die is electrically connected to the exposed solder balls. The combined semiconductor die and leadframe are placed in a second mold, and a second molding compound injected. The second molding compound flows around the semiconductor die and leadframe combination, fully enclosing the electrical connections between the leadframe and the semiconductor die, making the final package a twice-molded configuration. After this, the twice-molded semiconductor package array is cut at the appropriate locations to singulate the packages into individual products.

Description

    BACKGROUND Technical Field
  • This disclosure is in the field of semiconductor packages, and in particular, is directed towards a semiconductor package in which the leadframe and semiconductor package are each molded separately, then are joined together with solder balls.
    • Description of the Related Art
  • Semiconductor packages must protect the semiconductor die from the external environment while providing an output at the electrical signals for use by other circuits. The package, therefore, must be sufficiently protective and robust to prevent damage to the semiconductor die, while at the same time providing electrical connections so the signals may be received by and sent out from the semiconductor die.
  • Traditionally, a semiconductor die is placed on a leadframe or other substrate, and it is then electrically connected to this leadframe by bonding wires, solder balls, or other electrical coupling. After this, the combination is placed in a mold, and a molding compound injected into the mold to fully encase the die, but leave some of the electrical connections exposed so that it may be connected to the outside environment. Such an approach, while beneficial in many circumstances, has the goal of securely enclosing the semiconductor die while at the same time ensuring there is exposure to the electrical connections that extend away from the semiconductor die. Improvements in the packaging process, and the end package itself, will provide the benefit of greater reliability in the operation over the longer term use of the die, as well as having fewer failures during the semiconductor packaging process.
    • BRIEF SUMMARY
  • According to principles as taught herein, a leadframe array for a semiconductor die is prepared having locations to receive solder balls. Solder balls are then applied to the leadframe array, after which the leadframe array and solder ball combination is placed in a first mold and encased in a first molding compound. In one embodiment, the solder balls are fully encased in molding compound so as to be completely surrounded by the molding compound.
  • After the molding compound is cured, a layer of molding compound is removed to expose the solder balls. After this, a semiconductor die is electrically connected to the exposed solder balls. The combined semiconductor die and leadframe are placed in a second mold, and a second molding compound injected. The second molding compound flows around the semiconductor die and leadframe combination, fully enclosing the electrical connections between the leadframe and the semiconductor die, making the final package a twice-molded configuration. After this, the twice-molded semiconductor package array is cut at the appropriate locations to singulate the packages into individual products.
  • The present method permits the leadframe array to be fully constructed, encapsulated, and provided with electrical connections in a separate manufacturing line, prior to the introduction of the semiconductor die. Only after the leadframe array is encapsulated is the semiconductor die connected to the leadframe, thus providing a more rapid, and lower cost, technique for attaching the die to the leadframe. The leadframe is an array of leadframes, having many hundreds, or many thousands, of positions for a die. Accordingly, the package can be mass-produced with thousands of semiconductor die attached to the array of leadframes, after which the combination is placed in a second mold, encapsulated in a second molding compound and then singulated.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a completed semiconductor package according to principles disclosed herein.
  • FIG. 2 is a cross-sectional view of an alternative embodiment of a semiconductor package according to principles disclosed herein.
  • FIG. 3 is a cross-sectional view of yet another alternative embodiment according to principles disclosed herein.
  • FIGS. 4-8 are cross-sectional views of the process steps for making a semiconductor package according to principles as taught herein.
  • FIG. 9 is a cross-sectional view of an end package after the final step of FIG. 8.
  • FIG. 10 is a flow chart of the sequence of making a twice-molded package.
    •  DETAILED DESCRIPTION
  • FIG. 1 is a cross-sectional view of a twice-molded semiconductor chip package 10 according to principles as taught herein. The package 10 includes a semiconductor die 12 which is encased in a molding compound 16. Solder bumps 14 extend from pads on the semiconductor die 12 to provide electrical connections to the circuits thereon. A leadframe 18 is separately encased in its own molding compound 24. The leadframe 18 has solder balls 22, which are electrically connected to the solder bumps 14 extending from the semiconductor die 12. A conductive layer 20 extends along an exposed surface of leadframe 18. The layer 20 is composed of one or more layers of material which are electrically conductive and provide, in most embodiments, a solderable metal in order to solder the twice-molded package 10 to a printed circuit board or other substrate for use in a larger circuit.
  • As can be seen in FIG. 1, the solder bump 14 extending from the semiconductor die 12 and the solder ball 22 extending from the leadframe 18 are joined as an integral, single solder ball 28, which provides a contiguous single metal connection between the semiconductor die 22 and the leadframe 18. The single electrical connection 28 is achieved by reflowing the solder bumps 14 and 22 together at a temperature that approaches their melting point, in order to join them as a single, continuous solder ball connection.
  • In the embodiment of FIG. 1, the molding compound 16 completely encases and fully surrounds semiconductor die 12. This isolates semiconductor die 12 from the outside environment, blocking electrical access, moisture ingress, and providing mechanical coupling to the leadframe molding compound 24.
  • FIG. 2 shows a low-profile package 11, which is an alternative embodiment of the twice-molded semiconductor package 10 of FIG. 1. FIG. 2 illustrates a semiconductor die 12 coupled to a leadframe 18 in a similar manner to the package shown in FIG. 1. In the embodiment of FIG. 2, the molding compound 16 extends along the sides of the semiconductor die 12 but does not fully surround or encase the semiconductor die 12. Rather, the molding compound 16 extends completely between the semiconductor die 12 and the leadframe 18 and along the sidewalls of the semiconductor die, but does not cover the back side of the die 12.
  • The package 11, as shown in FIG. 2, has the benefit that it can be made substantially thinner than the package of FIG. 1. It is useful in those embodiments where a low-profile package is desired.
  • The low-profile package 11, as shown in FIG. 2, can be manufactured by a number of different techniques. It can be made using the process as shown in FIGS. 4-8 as explained herein, with the modification that, when the joint die and leadframe combination is placed in the mold, the shape of the mold ensures that the molding compound 16 only extends along the sidewalls of the die 12, and is blocked from going across the back of the die 12. An alternative method for producing the low-profile package 11 of FIG. 2 is to follow the same method steps used as making the package of FIG. 1 and, after the package is fully completed, milling off the top section of the semiconductor die 12, and along with the molding compound 27. Namely, when the manufacturing process is in the stage as shown in FIG. 8, the subsequent step is to remove the top section of the package. This can be done by sawing, milling, grinding, polishing, use of CMP, or other acceptable technique to perform a blanket removal of the top portion of the molding compound 27, and then, after all the top layer of molding compound 16 is removed, and then upon exposure of the semiconductor die 12, terminate removal of the molding compound 27. Thus, the exposure of the semiconductor die 12 can act as a stopping layer on which the removal of the molding compound 16 takes place.
  • Alternatively, if an ultrathin, extremely low-profile package 11 is desired, then the removal of the package can continue significantly past when the semiconductor die 12 is exposed, to remove substantial portions of the semiconductor die 12, together with the molding compound 27. Namely, the blanket removal of the top side of the package can continue to remove a significant height of the semiconductor die 12 along with the molding compound 27 to substantially reduce the profile of the overall package. In this embodiment, an ultrathin package can be obtained, in which the semiconductor die 12 has approximately half or even one-third of its standard height, and the molding compound 27 is flush with the top of the semiconductor die 12 in the final ultrathin package 11, as shown in FIG. 2.
  • FIG. 3 illustrates a further alternative embodiment of a minimally molded package 13 having the semiconductor die 12 coupled to the leadframe 18. In the minimally twice-molded package 13, as shown in FIG. 3, the semiconductor die 12 is coupled to the leadframe 18 and the molding compound 24 by a thin underfill 31 which extends only between the die 12 and the molding compound 24. In the embodiment of the package of FIG. 3, the underfill 31 does not extend along the sidewalls or the back of the die 12, rather it extends only between the die 12 and the molding compound 24 in order to fully enclose and protect the solder bumps 14. The leadframe portion of FIG. 3 is similar to that as explained in FIG. 1, namely having a leadframe 18 of a first metal, such as copper, a coating layer 20 of a second metal, such as nickel, or a combination of nickel, palladium, and gold, and solder balls 22. A molding compound 24 encases the solder balls 22 and the leadframe 18. The solder bumps 14 extending from the semiconductor 12 has been reflowed with the solder ball 22 to create a single integral solder ball 28 that extends from the semiconductor die 12 to the leadframe 18.
  • The embodiment of FIGS. 2 and 3 are beneficial in some particular environments in which it is desired to have some portion of the semiconductor die 12 exposed. In some packages, such as gas composition sensors, temperature sensors, optical readers, fingerprint readers, capacitive sensors, and other designs, it is desirable to have some portion of the circuits on semiconductor die 12 exposed to an outside environment. The embodiments of FIGS. 2 and 3 provide a twice-molded encapsulation package which also permits the semiconductor die 12 to have one or more surfaces exposed to an ambient atmosphere in those embodiments in which it desired because of the design or function of die 12. They also provide embodiments of an ultrathin package having a low profile which is desired in some end products, such as a wrist watch, wearable clothing, attachment to eyewear, a credit card, or other ultrathin environment in which a low profile packaged semiconductor chip is desired.
  • FIGS. 4-8 illustrate one method of making the twice-molded semiconductor package 10 as shown in FIG. 1, as well as the alternative embodiments of the packages 11 and 13 as shown in FIGS. 2 and 3.
  • FIG. 4 shows a leadframe array 18 made of a first metal having a second metal coating 20 at selected locations on an exposed surface thereof. The leadframe 18 can be made of any acceptable first metal such as copper, aluminum, or the like. In a preferred embodiment, the leadframe 18 is made of copper and is a single continuous mesh that includes many hundreds or thousands of leadframes for individual semiconductor packages. The second metal layer 20 will act as an etch mask for a later etch step of the leadframe 18 and, thus, is made of a second type of metal which permits selective etching of the leadframe 18 with respect to the metal 20. The metal 20 can be made of any acceptable metal, such as nickel, a trilayer coating of nickel, palladium, and gold, or other conductive layer of a type well known in the art that is preferably easily wettable by solder.
  • Layer 20 is applied as a blanket layer to the exposed surface of the leadframe 18 and patterned and etched to a desired pattern as shown in FIG. 4 using techniques well known in the art. In addition, the leadframe 18 has recesses 21 formed therein at locations where it is desired to provide electrical connections to a semiconductor die. The recesses 21 can be formed using a mask and etching process. Preferably, a wet etch is carried out with a proper mask in place in order to form the recesses 21. The recesses may be formed by other techniques known in the art. In the embodiment shown in FIG. 4, the recesses 21 are semicircular because they are formed by a wet etch carried out on the leadframe 18. If desired, the recesses 21 can be rectangular, slots, grooves, or any acceptable shape. In one embodiment, they can be formed by sawing thin grooves or recesses in the leadframe 18 using a mechanical saw or other techniques known in the art for creating recesses in leadframes.
  • FIG. 5 shows the leadframe 18 after conductive solder balls 22 have been affixed thereto and then the entire leadframe array has been placed into a mold and molding compound 24 injected therein. This is carried out by, after the leadframe array is fully prepared, as shown in FIG. 4, conductive metal, preferably solder balls 22 or other acceptable conductive metal, being placed at the prepared locations 21 in the leadframe 18. This completes the electrical connections for the leadframe 18. The combined leadframe 18 and solder balls 22 are placed first in a mold and a first molding compound 24 inserted to encapsulate and fully enclose the upper surface of the leadframe 18 as well as the entire solder balls 22. Sufficient molding compound is injected to ensure that the solder balls 22 are fully encased. This serves to immobilize the solder balls 22 while isolating them from the outside environment. The leadframe 18 is removed from the first mold and the first molding compound cured to achieve a fully hardened molding compound 24 to obtain the structure of FIG. 5.
  • FIG. 6 shows the upper layer of the first molding compound 24 having been removed to expose the solder balls 22. The leadframe 18 as shown in FIG. 5 is subjected to a grinding process in which the upper layer of the molding compound 24 is removed. The grinding continues until the solder balls 22 are exposed and, then, continues for an additional depth in order to expose an area 28 of the solder balls 22. Namely, the grinding of the molding compound 24 continues until a significant surface area 28 of each solder ball 22 is exposed. In the embodiment shown in FIG. 6, this continues until approximately the top one-quarter of each solder ball 22 has been removed. In some embodiments, the grinding will continue until approximately half of the solder ball 22 has been removed so that the maximum possible surface area 28 is exposed of the full diameter of the solder ball 22. The extended removal of additional molding compound 24 is particularly beneficial where a low profile, ultrathin package of the type shown in FIG. 2 is desired. It also provides the benefit that additional surface area is provided in the solder ball 22 to enhance the electrical connection and reduce the resistivity between the semiconductor die 12 to be attached. The amount of molding compound 24 that is removed is, therefore, selected according to the desired package design profile and resistance correction.
  • The removal of the molding compound 24 and the top portion of each solder ball 22 can be achieved by any acceptable technique, milling being a preferred technique. It can also be removed using sawing, polishing, etching (either wet etching or dry etching), grinding, or other acceptable technique in order to remove the upper portion of molding compound 24 along with a portion of each solder ball 22.
  • FIG. 7 shows a semiconductor die 12 having solder bumps 14. This assembly is coupled to the solder balls 22 of the leadframe 18. The semiconductor die is manufactured in a different process, using techniques well known in the art. The semiconductor die 12 includes a plurality of die pads, leads, or other electrical connections on a face thereof, as is known in the art. Solder bumps 14, or other electrical connections, are connected to the pads 12 of the semiconductor die 12 in order to provide connections to other circuits. The techniques for connecting a solder bump 14 to a semiconductor die 12 are well known in the art and, therefore, not discussed in greater detail herein. As can be appreciated, any electrical connector can be used for the solder bump 14. For example, pillars, extended contact pads, aluminum layers, or other structures known for providing an extended electrical connection of the type provided by solder bumps 14 to the semiconductor die 12 can be used. The semiconductor die 12 and solder bump 14 assembly is prepared in a previous stage, and then is joined to the assembly as shown in FIG. 6 in order to achieve the assembly as shown in FIG. 7. This is performed by a pick and place machine or other acceptable mechanical device which places the semiconductor die 12 at the correct locations having the solder bumps 14 in direct contact with the matching solder balls 22 of the leadframe 18. The solder bumps 14 and/or 18 may be slightly heated to aid in the attachment to each other. Other attachment techniques may also be used.
  • The combined semiconductor die 12 and once molded leadframe 18 are placed in a second mold. After being placed in the second mold, a second molding compound 16 is injected into the second mold to fully encase the semiconductor die 12 and also to bond with the first molding compound 24. The second molding compound 16 is selected which will strongly adhere to and firmly mold to the first molding compound 24. In some embodiments, the second molding compound 16 may become a unitary, contiguous molding compound with the first molding compound 24 at their junction such that the line between them is virtually invisible and indistinguishable. The twice-molded assembly is provided by taking the first-molded leadframe 18 having the first molding compound 24 thereon and placing it into a second mold and then subjecting it to a second molding step, with the semiconductor die 12 attached in order to encapsulate a second time the leadframe 18 and for a first time the semiconductor die 12.
  • After the second molding step as shown in FIG. 8 is carried out, the assembly is removed from the second mold and a post-mold cure is carried out to fully cure the molding compound 16. At the time that the combined package is removed from the second mold, the solder bumps 14, 22 are independent and distinct from each other. In particular, the solder bump 14 that was separately formed on the semiconductor die 12 and the solder ball 22 that was previously formed and encapsulated in molding compound 24 as coupled to the frame 18 are not yet fully merged. The two solder balls were brought into contact with each other before the second molding compound 16 was injected into the second mold and cured to fully surround the exposed portions of both solder bumps 14, 22. The solder bumps 14 and 22 are in physical and electrical contact.
  • FIG. 9 shows the individual twice-molded package 10 after a subsequent solder reflow step of solder bumps 14, 22 causes them to merge into a single, integral solder ball 28. This is performed by reheating the leadframe array having a plurality of leadframes and semiconductor die 12 connected in a large array to a reheating step that brings the solder bumps 14, 22 to their reflow temperature at which time the solder balls merge together into a single, contiguous solder ball 28. The solder ball reflow step is preferably carried out after the assembly has been removed from the second mold and has been twice-molded. The reflow temperature for the solder bumps 14, 22 will be selected to be compatible with each other and the type of solders will be selected to merge into a single, contiguous solder ball having a final metallic alloy of a desired type.
  • In one alternative embodiment, the reflow step is carried out when the assembly is in the condition as shown in FIG. 7, before the second molding compound 16 is injected. In particular, in the alternative embodiment, after the semiconductor die 12 is attached to the array of leadframes 18, a reflow step is carried out to fully and completely merge solder bumps 14, 22. After the full, high temperature reflow step is carried out, then the combined semiconductor die 12 and leadframe 18 are placed in the second mold and the second molding compound 16 is injected to achieve the final package as shown in FIG. 9.
  • In one preferred embodiment, the reflow occurs in two separate steps. In a first step, a first, minimal reflow is carried out when solder bump 14 is first brought into contact with solder ball 22 in order to adhere the two solder balls to each other and provide a strong mechanical and electrical connection. A first, minimum temperature reflow occurs by slight heating of the leadframe 18 with the solder ball 22 attached so that upon the solder bumps 14 touching the heated solder balls 22 there is a slight merge between the solder balls bringing them into strong mechanical and electrical connection. Preferably, this initial connection is carried out just as the semiconductor die 12 is first placed on the leadframe array 18 as shown in FIG. 7 in order to provide strong mechanical coupling. The heating is performed by heating the leadframe 18 and solder balls 22, which, being made of metal, will easily transfer heat. Subsequently, the assembly is placed in the second mold and the second molding compound 16 injected. After the second molding compound has been injected, then a second, more complete and higher temperature reflow is carried out. The higher temperature reflow will be at a significantly high temperature so that the solders completely merge with each other as a single contiguous piece of metal. The second reflow will be a relatively high temperature compared to the first one, and often sufficiently high that the two solder materials 14, 22 become substantially liquid.
  • If the high temperature reflow were carried out when the assembly is partially completed as shown in FIG. 7, the solder bumps 14, 22 might run and change shape significantly, spreading out well beyond the desired location. They may, in some instance, fail to perform the proper electrical connections or short to other adjacent solder balls. However, once the solder balls have been fully encased as shown in FIG. 8, the movement of the solder bumps 14, 22 is strictly limited.
  • In the stages shown in FIG. 8, the solder balls can be subjected to a significantly high reflow temperature, nearly to their full liquid state temperature, so that a full mixing and reflow is carried out to completely combined the two solder balls to each other into a unitary solder ball 28 as shown in FIG. 9. The two molding compounds 16 and 24 form an enclosed cavity that keeps the solder in place; even when heated.
  • After the second reflow is carried out, the leadframe 18 is etched on the back side with an etching fluid that is selective to remove the leadframe material 18, but not remove the metal layer 20. Preferably, the leadframe 18 is made of copper, or in one embodiment aluminum. A wet etch which selectively removes copper, but does not remove nickel or a nickel, palladium, gold layer combination is used. This wet etch will remove the exposed copper portions of leadframe 18 so that some of the molding compound 24 protrudes through the bottom of the package, as can be seen in FIG. 9. After the back side etching of the copper is carried out, the package is singulated from the array to produce the final completed package 10, as shown in FIG. 9.
  • FIG. 10 shows a flow chart for preparing the twice-molded semiconductor package according to the embodiments as described herein. The process starts at step 42 in which a leadframe is prepared and, in a completely separate process and a separate timing, a semiconductor die 12 is also prepared. In step 44, the leadframe array 18 is prepared to receive the solder. In this case, recesses are formed in the leadframe 18 to receive solder. In step 46, solder 22 is attached to the leadframe array 18, usually as solder balls, but could be in another form as well. In step 48, the leadframe array 18 is placed into a first mold. Molding compound is injected to completely surround the solder balls 22, so they are fully encased and also to cover the top surface of the leadframe array 18. Subsequently, in step 52, the top of the completed molded leadframe is removed so as to expose portions of the encapsulated solder ball. After the top layer is removed, the semiconductor die 12 is electrically connected at the appropriate locations to the respective solder balls of the leadframe array 18, as seen in step 54. At this step, a slight heating of the leadframe array 18 can take place in order to increase the adhesion or, alternatively, some adhesive material may be used that will conductively couple the die 12 to the leadframe array 18. After the appropriate number of semiconductor die are connected to the respective proper locations in the leadframe array 18, the combination is placed into a second mold in step 56. Subsequently, in step 58, the combination is encapsulated to affix the package which includes the leadframe array 18 and the semiconductor die 12 in a second molding compound. After this, the twice-molded packages are singulated into individual packages in step 60.
  • Multiple embodiments have been shown for creating a twice-molded semiconductor package 10. The various embodiments may be combined with each other to achieve a wide variety of different packages according to the various alternative embodiments as taught herein.
  • The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
  • These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims (21)

1. A method for making a semiconductor die package, comprising:
forming recesses in a first surface of a leadframe array;
placing solder in the recesses of the leadframe array to form solder balls;
placing the combined leadframe array and solder balls into a mold;
injecting a molding compound into the mold sufficient to fully encapsulate the solder and the first surface of the leadframe array to create a once-molded leadframe array;
removing an upper portion of the molding compound and the solder balls sufficient to expose an interior surface area of the solder;
attaching a semiconductor die to the exposed solder;
placing the combined semiconductor die and once-molded molded leadframe array into a second mold;
injecting a second molding compound into the second mold to encapsulate the semiconductor die and the upper surface of the exposed first molding compound; and
singulating individual semiconductor die packages from the twice-molded semiconductor package array.
2. The method of claim 1, further including:
attaching a solder ball to the semiconductor die prior to connecting the die to the once-molded leadframe array.
3. The method according to claim 2 wherein the connection of the semiconductor die to the once-molded leadframe array includes the step comprising:
bringing the solder connected to the semiconductor die into physical contact with the solder of the once-molded leadframe array.
4. A method for making a semiconductor die package, comprising:
forming recesses in a first surface of a leadframe array;
placing solder in the recesses of the leadframe array to form solder balls;
placing the combined leadframe array and solder balls into a mold;
injecting a molding compound into the mold sufficient to fully encapsulate the solder and the first surface of the leadframe array to create a once-molded leadframe array;
removing an upper portion of the molding compound and the solder balls sufficient to expose an interior surface area of the solder;
attaching a solder ball to a semiconductor die;
attaching the semiconductor die to the exposed solder after connecting the die to the once-molded leadframe array by bringing the solder connected to the semiconductor die into physical contact with the solder of the once-molded leadframe array;
placing the combined semiconductor die and molded leadframe array into a second mold;
injecting a second molding compound into the second mold to encapsulate the semiconductor die and the upper surface of the exposed first molding compound to create a twice-molded semiconductor die package array;
heating the twice-molded semiconductor die array to a sufficient temperature to reflow the solder to merge the solder ball coupled to the die to the solder ball of the once-molded leadframe array to obtain an integral solder coupling between the semiconductor die and the leadframe; and
singulating individual semiconductor die packages from the twice-molded semiconductor die package array.
5. The method according to claim 4 wherein the heating step is carried out prior to the semiconductor die being placed in the second mold and second molding compound injected therein.
6. The method according to claim 4 wherein the heating step is carried out after the semiconductor die has been removed from second the mold and second molding compound encapsulating it has been cured.
7. The method according to claim 5, further comprising:
subjecting the solder coupled to the semiconductor die to a first temperature in the heating step to mechanically and electrically affix the solder of the die to the solder of the once-molded leadframe array; and
subsequently carrying out the step of placing the semiconductor die and leadframe in the second mold and injecting the second molding compound, after which a second reflow temperature is carried out by subjecting the twice-molded semiconductor package array to a second temperature higher than the first temperature to carry out a second reflow to more completely combine the solder ball of the semiconductor die with the solder ball of the leadframe array.
8. The method according to claim 1 wherein the second molding compound fully encapsulates the semiconductor die and the exposed portions of the once-molded leadframe array.
9. The method according to claim 1 wherein the second molding compound fully encapsulates the electrical connection between semiconductor die and the once-molded leadframe array without encapsulating one full surface of the semiconductor die.
10. The method according to claim 1 wherein the second molding compound fully encapsulates the electrical connection between the semiconductor die and the once-molded leadframe array, but does not encapsulate side walls or an exposed surface of the semiconductor die.
11. A semiconductor package comprising:
a leadframe having a first side and a second side, the lead frame including a lead;
a first solder member connected to the first side of the lead;
a first molding compound extending from the first side of the lead, the first molding compound encapsulating the first solder member and the first side of the lead;
a semiconductor die having an electrical pad on a first surface thereon;
a second solder member connected to the electrical pad of the semiconductor die and to the first solder member that provides an electrical connection from the semiconductor die to the lead of the leadframe; and
a second molding compound that encapsulates the semiconductor die, the second solder member and is in direct physical contact with both the second solder member and the first molding compound.
12. The semiconductor package of claim 11 wherein the first solder member is a solder ball.
13. A semiconductor package comprising
a leadframe having a first side and a second side, the leadframe including a lead;
a first solder member connected to the first side of the lead;
a first molding compound extending from the first side of the lead, the first molding compound encapsulating the first solder member and the first side of the lead;
a semiconductor die having an electrical pad on a first surface thereon;
a second solder member connected to the electrical pad of the semiconductor die and to the first solder member that provides an electrical connection from the semiconductor die to the lead of the leadframe; and
a second molding compound that encapsulates the semiconductor die, the second solder member and is in direct physical contact with the first molding compound
wherein first solder member and the second solder member have been bonded to each other in a heat treatment to form a single, contiguous solder member.
14. The semiconductor package of claim 11 wherein the first molding compound and the second molding compound are comprised of different materials.
15. The semiconductor package of claim 11 wherein the second molding compound encapsulates the sidewalls and the first surface of the semiconductor die but not a second surface of the semiconductor die that is opposite the first surface.
16. The semiconductor package of claim 11 wherein the second molding compound encapsulates the first surface of the semiconductor die but not the sidewall or a second surface of the semiconductor die that is opposite the first surface.
17. A semiconductor package comprising:
a leadframe having a first side and a second side, the lead-frame including a plurality of leads;
a plurality of solder balls, one solder ball of the plurality being connected to the first side of each of the respective leads of the plurality of leads;
a first molding compound connected to the first side of the lead, the first molding compound encapsulating each of the solder balls and the first side of each lead;
a semiconductor die having a plurality of electrical pads thereon;
a plurality of solder members connected to each respective electrical pad of the semiconductor die and also to respective solder balls, the solder members and solder balls forming single, contiguous metal connection between the semiconductor die and the leadframe; and
a second molding compound that encapsulates the semiconductor die, the second solder member and is in direct physical contact with both the solder members and the first molding compound.
18. The semiconductor package of claim 17 wherein the first molding compound and the second molding compound form a unitary, contiguous molding compound.
19. The semiconductor package of claim 17 wherein the solder balls and the solder members are comprised of the same metal alloy.
20. The semiconductor package of claim 17 wherein at least two of the solder balls are connected to the same lead to electrically connect the two solder balls and two of the electrical pads on the semiconductor to each other.
21. The method according to claim 4 wherein the heating step is carried out concurrently with the step of injecting a second molding compound into the second mold to encapsulate the semiconductor die and the upper surface of the exposed first molding compound to create a twice-molded semiconductor die package array.
US15/663,624 2017-07-28 2017-07-28 Semiconductor package with individually molded leadframe and die coupled at solder balls Active US10204814B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/663,624 US10204814B1 (en) 2017-07-28 2017-07-28 Semiconductor package with individually molded leadframe and die coupled at solder balls
CN201810804209.1A CN109309010A (en) 2017-07-28 2018-07-20 Semiconductor packages with the separately molded lead frame and bare die coupled at soldered ball

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/663,624 US10204814B1 (en) 2017-07-28 2017-07-28 Semiconductor package with individually molded leadframe and die coupled at solder balls

Publications (2)

Publication Number Publication Date
US20190035669A1 true US20190035669A1 (en) 2019-01-31
US10204814B1 US10204814B1 (en) 2019-02-12

Family

ID=65038125

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/663,624 Active US10204814B1 (en) 2017-07-28 2017-07-28 Semiconductor package with individually molded leadframe and die coupled at solder balls

Country Status (2)

Country Link
US (1) US10204814B1 (en)
CN (1) CN109309010A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10522505B2 (en) * 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US11152322B2 (en) * 2017-10-05 2021-10-19 Texas Instruments Incorporated Leadframes in semiconductor devices
WO2022212604A1 (en) * 2021-03-30 2022-10-06 Samtec, Inc. Interconnect alignment system and method
EP4016619A3 (en) * 2020-12-18 2023-03-01 INTEL Corporation Microelectronic structures including bridges

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844315A (en) * 1996-03-26 1998-12-01 Motorola Corporation Low-profile microelectronic package
US7372151B1 (en) * 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
MY136179A (en) * 2004-10-23 2008-08-29 Freescale Semiconductor Inc Packaged device and method of forming same
US7768125B2 (en) * 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
TWI343103B (en) * 2007-06-13 2011-06-01 Siliconware Precision Industries Co Ltd Heat dissipation type package structure and fabrication method thereof
US8492883B2 (en) * 2008-03-14 2013-07-23 Advanced Semiconductor Engineering, Inc. Semiconductor package having a cavity structure
US8304277B2 (en) * 2010-09-09 2012-11-06 Stats Chippac, Ltd. Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking
US8361899B2 (en) * 2010-12-16 2013-01-29 Monolithic Power Systems, Inc. Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing
US20130043573A1 (en) * 2011-08-15 2013-02-21 Advanced Analogic Technologies (Hong Kong) Limited Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores
US8928134B2 (en) * 2012-12-28 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package bonding structure and method for forming the same
CN103745967A (en) * 2013-12-05 2014-04-23 南通富士通微电子股份有限公司 Lead frame and packaging structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10522505B2 (en) * 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US10937761B2 (en) 2017-04-06 2021-03-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US11682653B2 (en) 2017-04-06 2023-06-20 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US11152322B2 (en) * 2017-10-05 2021-10-19 Texas Instruments Incorporated Leadframes in semiconductor devices
EP4016619A3 (en) * 2020-12-18 2023-03-01 INTEL Corporation Microelectronic structures including bridges
US12119326B2 (en) 2020-12-18 2024-10-15 Intel Corporation Microelectronic structures including bridges
WO2022212604A1 (en) * 2021-03-30 2022-10-06 Samtec, Inc. Interconnect alignment system and method

Also Published As

Publication number Publication date
CN109309010A (en) 2019-02-05
US10204814B1 (en) 2019-02-12

Similar Documents

Publication Publication Date Title
US6084308A (en) Chip-on-chip integrated circuit package and method for making the same
US10204814B1 (en) Semiconductor package with individually molded leadframe and die coupled at solder balls
US6642610B2 (en) Wire bonding method and semiconductor package manufactured using the same
US8426255B2 (en) Chip package structure and method for manufacturing the same
US8796561B1 (en) Fan out build up substrate stackable package and method
US7138706B2 (en) Semiconductor device and method for manufacturing the same
US20150332991A1 (en) Method of forming a thin substrate chip scale package device and structure
US20080099784A1 (en) Array quad flat no-lead package and method of forming same
US20190067145A1 (en) Semiconductor device
US6064115A (en) Semiconductor device provided with a heat sink
US8389338B2 (en) Embedded die package on package (POP) with pre-molded leadframe
CN112786541A (en) Packaging structure and packaging method of cavity device group
JP2002110718A (en) Manufacturing method of semiconductor device
US20080009096A1 (en) Package-on-package and method of fabricating the same
US20130069223A1 (en) Flash memory card without a substrate and its fabrication method
US8283780B2 (en) Surface mount semiconductor device
US7781259B2 (en) Method of manufacturing a semiconductor using a rigid substrate
US20020187591A1 (en) Packaging process for semiconductor package
US9252114B2 (en) Semiconductor device grid array package
US6710434B1 (en) Window-type semiconductor package and fabrication method thereof
KR100487135B1 (en) Ball Grid Array Package
KR19990051002A (en) Laminated package and its manufacturing method
KR20060024451A (en) Wafer molding type semiconductor package and fabricating this
CN108074824A (en) A kind of production method of semiconductor devices
KR20000059991A (en) method for forming heat sink of PBGA package using metal grain injection

Legal Events

Date Code Title Description
AS Assignment

Owner name: STMICROELECTRONICS, INC., PHILIPPINES

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TALLEDO, JEFFERSON;REEL/FRAME:043300/0254

Effective date: 20170728

STCF Information on status: patent grant

Free format text: PATENTED CASE

CC Certificate of correction
MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

AS Assignment

Owner name: STMICROELECTRONICS INTERNATIONAL N.V., SWITZERLAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS, INC.;REEL/FRAME:068025/0112

Effective date: 20240701