KR20000059833A - Method for doping impurities into poly crystalline silicon - Google Patents
Method for doping impurities into poly crystalline silicon Download PDFInfo
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- KR20000059833A KR20000059833A KR1019990007712A KR19990007712A KR20000059833A KR 20000059833 A KR20000059833 A KR 20000059833A KR 1019990007712 A KR1019990007712 A KR 1019990007712A KR 19990007712 A KR19990007712 A KR 19990007712A KR 20000059833 A KR20000059833 A KR 20000059833A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000012535 impurity Substances 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 28
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims abstract description 16
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 13
- 239000011574 phosphorus Substances 0.000 claims abstract description 13
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000010453 quartz Substances 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229920006268 silicone film Polymers 0.000 abstract 3
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 21
- 239000007788 liquid Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- -1 phosphorus ion Chemical class 0.000 description 2
- 238000000197 pyrolysis Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000010336 energy treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 다층배선이나 상호연결을 위한 도전층으로서 사용되는 다결정 실리콘막에 불순물을 도핑하기 위한 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for doping impurities in a polycrystalline silicon film used as a conductive layer for multilayer wiring or interconnection.
통상적으로, 다결정 실리콘 막은 반도체 디바이스의 다층 배선막으로서 사용되며 저압 화학기상증착법으로 통상 만들어진다. 그러한 다결정 실리콘 막이 배선막으로서의 역할을 원활히 수행하기 위해서는 주로 엔형의 불순물이 상기 실리콘 막에 도우핑된다. 다결정 실리콘의 침적 후 엔형의 불순물을 내부에 주입하기 위한 통상의 이온 주입 방법은 액상 포클액(POCl2)을 800-900℃온도의 노에 공급함으로써 액상 포클액의 성분을 이루는 인(Ph)이온이 상기 다결정 실리콘에 주입되도록 하는 방법이다. 또한, 비교적 덜 알려져 있지만 포스핀 가스를 이용하여 엔형 이온을 주입하는 방법이다. 여기서, 엔 형(N Type) 불순물 주입에 의해 생성되는 캐리어로서의 전자의 농도는 상기 2가지 중 전자의 경우에 포클(POCl2)양, 질소 및 산소가스의 공급량에 따라 결정되고, 후자의 경우에 도우즈,에너지, 열처리 조건등에 따라 결정된다. 결국 이러한 조건에 의해 캐리어인 전자의 농도가 달라지면 전극의 전기전도도가 다르게 되는 것이다.Typically, polycrystalline silicon films are used as multilayer wiring films of semiconductor devices and are usually made by low pressure chemical vapor deposition. In order for such a polycrystalline silicon film to perform a role as a wiring film smoothly, mainly an N-type impurity is doped into the silicon film. The conventional ion implantation method for injecting N-type impurities into the interior after deposition of polycrystalline silicon is a phosphorus (Ph) ion constituting the liquid fockle liquid by supplying the liquid fockle liquid (POCl 2 ) to a furnace at 800-900 ° C. This is a method to be injected into the polycrystalline silicon. In addition, it is a relatively less known method of implanting en-type ions using phosphine gas. Herein, the concentration of electrons as carriers generated by N type impurity injection is determined by the amount of POCl 2 , nitrogen and oxygen gas supply in the case of the former, and in the latter case It depends on the dose, energy and heat treatment conditions. As a result, when the concentration of electrons as carriers is changed under these conditions, the electrical conductivity of the electrode is different.
상기 전자의 이온 주입방법은 웨이퍼 내 혹은 배치내의 웨이퍼의 저항 균일도를 일정하지 않게 할 수 있다. 왜냐하면, 액상 포클액 소스 가스를 이용하는 공정에서 인 원자가 웨이퍼내로 일정하게 확산되기 어렵기 때문이다.The electron ion implantation method can make the resistance uniformity of the wafer in the wafer or in the batch uneven. This is because phosphorus atoms are difficult to uniformly diffuse into the wafer in the process using the liquid fockle liquid source gas.
상기한 바와 같이, 종래에는 포클 공정을 이용하여 불순물 주입시 소오스 가스가 웨이퍼 내에 불균일하게 확산됨으로 인하여 이온 주입농도가 일정하지 못하였다. 따라서, 다결정 실리콘의 시트저항이 불균일하게 되는 문제가 있다.As described above, in the related art, the ion implantation concentration was not constant due to the non-uniform diffusion of the source gas into the wafer during impurity implantation using the fockle process. Therefore, there exists a problem that the sheet resistance of polycrystal silicon becomes nonuniform.
따라서, 배선막 혹은 인터커넥션 막으로 사용되는 다결정 실리콘 막에 도전성을 높이기 위해 엔형의 불순물을 보다 바람직하게 주입하는 도우핑 조건 및 방법이 절실히 요망된다.Accordingly, there is an urgent need for doping conditions and methods for more preferably injecting N-type impurities into the polycrystalline silicon film used as a wiring film or interconnection film to increase conductivity.
따라서, 본 발명의 목적은 상기한 종래의 문제들을 해결할 수 있는 불순물 도핑방법을 제공함에 있다.Accordingly, an object of the present invention is to provide an impurity doping method that can solve the above-mentioned conventional problems.
본 발명의 다른 목적은 배선막 혹은 인터커넥션 막으로 사용되는 다결절 실리콘 막에 엔형의 불순물을 주입하는 방법을 제공함에 있다.Another object of the present invention is to provide a method of injecting an N-type impurity into a multi-nodal silicon film used as a wiring film or an interconnect film.
본 발명의 또 다른 목적은 다결정 실리콘의 시트저항을 최대로 균일하게 보장할 수 있는 이온 주입방법을 제공함에 있다.It is still another object of the present invention to provide an ion implantation method capable of maximally and uniformly ensuring sheet resistance of polycrystalline silicon.
상기한 목적들의 일부를 달성하기 위하여 본 발명에 따라 다결정 실리콘막에 불순물을 도핑하기 위한 방법은, 수직형 노 타입의 챔버내로 포스핀(PH3) 가스를 약 800도씨 정도의 분위기에서 인의 소오스 가스로서 공급하여 배선막으로 사용되어질 다결정 실리콘 막내로 엔형의 불순물이 주입되도록 함을 특징으로 한다.In order to achieve some of the above objects, a method for doping impurities in a polycrystalline silicon film according to the present invention comprises a source of phosphorus in an atmosphere of about 800 degrees Celsius with phosphine (PH 3 ) gas into a vertical furnace type chamber. The Y-type impurity is injected into the polycrystalline silicon film to be supplied as a gas and to be used as the wiring film.
본 발명의 타의 목적 및 이점은 첨부도면과 함께 설명되는 하기 설명에 의해 보다 명확하게 나타날 것이다.Other objects and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.
도 1 내지 도 3은 본 발명에 적용되는 이온 주입장치의 외관을 보인 개략도들1 to 3 are schematic views showing the appearance of the ion implantation apparatus applied to the present invention
도 4a 및 도 4b는 본 발명의 다양한 실시예에 따라 다결정 실리콘막에 불순물을 도핑한 결과를 보여주는 그래프들4A and 4B are graphs showing results of doping impurities into a polycrystalline silicon film according to various embodiments of the present disclosure.
이하에서, 다결정 실리콘막에 불순물을 도핑하기 위한 방법에 대한 본 발명의 바람직한 실시예들이 상세히 설명된다.Hereinafter, preferred embodiments of the present invention for a method for doping impurities in a polycrystalline silicon film are described in detail.
본 발명에서는 다결정 실리콘에 불순물을 주입하는 인의 소오스 가스로서 포스핀 가스를 사용한다는 것이 중요한 사항이다. 이에 따라 인 가스의 확산균일도는 액상 포클 가스의 경우에 비해 개선이 된다는 것이 설명될 것이다. 또한, 일정한 온도 이상에서는 다결정 실리콘 내의 도핑 레벨도 일정해져 시트 저항이 균일해지는 효과가 얻어진다.In the present invention, it is important to use phosphine gas as a source gas of phosphorus for injecting impurities into polycrystalline silicon. Accordingly, it will be explained that the diffusion uniformity of the phosphorous gas is improved compared to that of the liquid fockle gas. Moreover, above a certain temperature, the doping level in polycrystalline silicon also becomes constant, and the effect that a sheet resistance becomes uniform is acquired.
먼저, 도 1은 포스핀(PH3)가스를 이용하여 다결정 실리콘에 엔형 불순물을 이온 주입하기 위한 이온주입 장치를 보인 것이다. 일정한 농도 예컨대 0.1-10퍼센트농도의 포스핀 가스를 수직형의 노내에 온도가 700-1000℃이고 압력이 100 mTorr-3000 mTorr로 형성된 챔버에 10-1000 SCCM의 유속으로 공급하면, 열분해 방식에 의해 포스핀 가스중의 인 가스가 로딩된 웨이퍼에 침적된 다결정 실리콘내로 주입된다. 여기서, 노내부에 형성되는 챔버의 튜브 타입은 2중석영관이다. 도 1에서, 참조부호 10은 메인 히터이고, 참조부호 20은 2중석영관중의 외부 튜브이며, 참조부호 30은 2중석영관중의 내부튜브이다. 참조부호 40은 웨이퍼를 탑재하기 위한 보우트이고, 50은 상기 보우트를 지지하기 위한 지지부이다. 여기서, 상기 포스핀 가스는 인입구 IN를 통해 입력되어 화살부호 AR1의 방향으로 흘러 배출구 OUT로 배출된다. 도 2는 상기 도 1의 경우와 동일하나, 노의 구조상 포스핀 가스의 흐름을 화살부호 AR2와 같은 방향으로 변형한 것만이 다르다. 도 3은 2중 석영관을 사용치 아니하고 단일 석영관을 사용한 경우이다. 이 경우에 챔버내의 포스핀 가스의 흐름은 화살부호 AR3와 같은 방향으로 된다.First, FIG. 1 shows an ion implantation apparatus for ion implanting Y-type impurities into polycrystalline silicon using phosphine (PH 3 ) gas. When a constant concentration, such as 0.1-10 percent of phosphine gas, is supplied to a chamber formed with a temperature of 700-1000 ° C. and a pressure of 100 mTorr-3000 mTorr in a vertical furnace at a flow rate of 10-1000 SCCM, Phosphorous gas in phosphine gas is injected into the polycrystalline silicon deposited on the loaded wafer. Here, the tube type of the chamber formed inside the furnace is a double quartz tube. In Fig. 1, reference numeral 10 denotes a main heater, reference numeral 20 denotes an outer tube in a double quartz tube, and reference numeral 30 denotes an inner tube in a double quartz tube. Reference numeral 40 is a boat for mounting a wafer, and 50 is a support for supporting the boat. Here, the phosphine gas is input through the inlet IN and flows in the direction of arrow AR1 and is discharged to the outlet OUT. FIG. 2 is the same as the case of FIG. 1, except that the phosphine gas flow is modified in the same direction as arrow AR2 due to the structure of the furnace. 3 is a case where a single quartz tube is used without using a double quartz tube. In this case, the flow of phosphine gas in the chamber is in the same direction as arrow AR3.
상기 도 1,2,3의 경우 모두 챔버내에 포스핀 가스의 농도를 균일하게 형성하기 위해 감압을 하여 일정한 압력을 유지시킨다.In the case of FIGS. 1,2 and 3, the pressure is reduced to maintain a constant pressure in order to uniformly form the concentration of phosphine gas in the chamber.
도 4a,4b 는 포스핀 가스를 챔버에 공급한 경우에 다결정 실리콘에 주입된 인 농도를 공정조건별로 측정한 SIMS데이터를 그래프로 나타낸 것을 보여준다. 측정을 행하기 위해, 웨이퍼를 이루는 단결정 실리콘과 침적되어질 다결정 실리콘의 격리막으로서 열산화막을 약 1000Å 정도 성장시킨 후 다결정 실리콘을 저압화학기상증착 타입의 설비에서 1000Å성장 시킨 웨이퍼를 측정대상용 시료로 준비한다. 이를 상기 도 1,2,3의 챔버에 로딩하고 열처리 시간과 온도를 달리하여 주입된 인 농도를 평가한 것이다.Figures 4a, 4b shows the graph showing the SIMS data measured by the process conditions of the phosphorus concentration injected into the polycrystalline silicon when the phosphine gas is supplied to the chamber. In order to perform the measurement, as a separator for the single crystal silicon to be deposited and the polycrystalline silicon to be deposited, a thermal oxide film was grown to about 1000 GPa, and then a wafer having a 1000 GPa growth of polycrystalline silicon in a low pressure chemical vapor deposition type facility was prepared as a sample for measurement. do. This was loaded into the chambers of FIGS. 1,2 and 3 to evaluate the injected phosphorus concentration by varying the heat treatment time and temperature.
도 4a에서, 가로축은 다결정 실리콘내로 주입된 인이온의 주입 깊이를 나타내고 세로축은 인이온의 주입농도를 나타낸다. 도면에서 그래프 A1,A2,A3는 각기 챔버의 온도를 750℃로 세팅하고 열처리시간을 각기 30분, 60분, 120분으로 한 경우를 보인 것이다. 이를 통해, 포스핀 가스의 열분해 시간이 증가할 수록 도우핑 농도가 증가하는 것을 알 수 있으며, 다결정 실리콘 내의 깊이별 농도분포는 표면에서 벌크쪽으로 갈 수록 농도가 감소함을 알 수 있다. 또한, 열분해 시간이 짧을 수록 농도의 불균일성이 심화되는 현상이 보여진다. 이는 750℃공정온도에서 포스핀 가스를 공급하기 때문에 인 원자가 다결정 실리콘 내로 충분히 확산되지 아니함에 따라 나타나는 농도 불균일 현상으로 관찰된다.In FIG. 4A, the horizontal axis represents the implantation depth of the phosphorus ion implanted into the polycrystalline silicon and the vertical axis represents the implantation concentration of the phosphorus ion. In the drawings, graphs A1, A2, and A3 show a case where the temperature of the chamber is set to 750 ° C. and the heat treatment time is set to 30 minutes, 60 minutes, and 120 minutes, respectively. Through this, it can be seen that the doping concentration increases as the pyrolysis time of the phosphine gas increases, and the concentration distribution for each depth in the polycrystalline silicon decreases as the bulk goes from the surface to the bulk. In addition, the shorter the pyrolysis time, the more uneven the concentration is observed. This is observed as a concentration non-uniformity phenomenon, which occurs as phosphorus atoms do not sufficiently diffuse into the polycrystalline silicon because the phosphine gas is supplied at a process temperature of 750 ° C.
도 4b에서, 공정 온도별로 다결정 실리콘에 주입된 인 농도를 측정한 것으로서 그래프 B1,B2,B3는 60분동안 각기 700℃,750℃,800℃에서 열처리를 한 경우를 나타낸다. 마찬가지로, 가로축은 주입깊이를, 세로축은 농도를 나타낸다. 여기서, 온도가 증가할 수록 도우핑 농도가 증가하는 현상을 보이며 특히 800℃온도의 60분조건에서는 인 농도가 4.0E20 atoms/cc 정도인 도우핑 농도 수준을 얻을 수 있으며 다결정 실리콘 내에도 인의 농도 분포가 균일하게 됨을 확인할 수 있다. 따라서, 웨이퍼의 전 부분에서 시트 저항이 일정하게 되는 것이다. 여기서, 포스핀 가스를 사용하여 인을 확산시키는 효과를 증대시키기 위해서는 다결정 실리콘에 형성되는 자연산화막을 제거하여 확산 배리어 막을 최소화하는 것이 바람직하다. 이를 위해 불산을 이용한 크리닝 공정 즉 세정공정이 적용된다. 세정공정이 완료되면 공정타임 딜레이도 고려를 하여 최대로 줄이는 것이 바람직하다.In Figure 4b, as measured the phosphorus concentration injected into the polycrystalline silicon for each process temperature, graphs B1, B2, B3 shows a case where the heat treatment at 700 ℃, 750 ℃, 800 ℃ for 60 minutes respectively. Similarly, the horizontal axis represents the injection depth and the vertical axis represents the concentration. Here, the doping concentration increases with increasing temperature. Especially, the doping concentration level with phosphorus concentration of 4.0E20 atoms / cc can be obtained in 60 minutes at 800 ℃, and the concentration distribution of phosphorus in polycrystalline silicon It can be seen that is uniform. Thus, sheet resistance is constant over the entire portion of the wafer. Here, in order to increase the effect of diffusing phosphorus using phosphine gas, it is preferable to minimize the diffusion barrier film by removing the native oxide film formed on the polycrystalline silicon. To this end, a cleaning process using hydrofluoric acid, that is, a cleaning process is applied. Once the cleaning process is complete, it is desirable to consider the process time delay to the maximum.
전술한 바와 같이, 본 발명의 실시예들은 도면을 참조하여 예를들어 설명되었지만, 사안이 허용하는 범위에서 다양한 변화와 변경이 가능함은 물론이다.As described above, the embodiments of the present invention have been described by way of example with reference to the drawings, but of course, various changes and modifications can be made within the scope allowed by the matter.
상기한 본 발명의 방법에 따르면, 다결정 실리콘막에 불순물을 도핑시 시트 저항을 균일하게 하여 배선의 도전성을 안정 및 우수하게 보장하는 효과가 있다.According to the method of the present invention described above, when doping an impurity into a polycrystalline silicon film, the sheet resistance is uniform, thereby ensuring the stability and excellent conductivity of the wiring.
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