KR20000057851A - Combined system, method and apparatus for wire bonding and testing - Google Patents
Combined system, method and apparatus for wire bonding and testing Download PDFInfo
- Publication number
- KR20000057851A KR20000057851A KR1020000004832A KR20000004832A KR20000057851A KR 20000057851 A KR20000057851 A KR 20000057851A KR 1020000004832 A KR1020000004832 A KR 1020000004832A KR 20000004832 A KR20000004832 A KR 20000004832A KR 20000057851 A KR20000057851 A KR 20000057851A
- Authority
- KR
- South Korea
- Prior art keywords
- bonding
- wire
- testing
- computer
- bond
- Prior art date
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 148
- 238000000034 method Methods 0.000 title claims abstract description 30
- 230000004044 response Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 18
- 238000005520 cutting process Methods 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000006664 bond formation reaction Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 claims 2
- 238000000528 statistical test Methods 0.000 claims 1
- 230000002950 deficient Effects 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 description 23
- 239000002184 metal Substances 0.000 description 23
- 239000004065 semiconductor Substances 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000013500 data storage Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000012937 correction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- -1 gold-aluminum Chemical compound 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000012372 quality testing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000009662 stress testing Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 241000587161 Gomphocarpus Species 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 241000124033 Salix Species 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000001464 adherent effect Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000011575 calcium Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000010267 cellular communication Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05664—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10271—Silicon-germanium [SiGe]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 일반적으로 전자 시스템 및 반도체 디바이스 분야에 관한 것으로, 특히, 반도체 칩에 와이어 본딩을 하고 품질 테스팅을 하기 위한 자동화된 결합 시스템, 방법 및 장치에 관한 것이다.FIELD OF THE INVENTION The present invention generally relates to the field of electronic systems and semiconductor devices, and more particularly, to automated bonding systems, methods and apparatus for wire bonding and quality testing of semiconductor chips.
종래에는, 집적 회로 칩의 입/출력 패드는 소정 길이(span)를 형성하는 금속 와이어에 의해 외부에 접속되었다. 입/출력 패드의 금속은 통상적으로 알루미늄 또는 구리로 구성되며, 통상 금 또는 구리 와이어 재료로서 사용된다. 대부분의 반도체 디바이스에서는, 접속 와이어(예를 들어, 금)의 한 단부를 패드 금속에 평탄화된 볼 모양으로 부착시키는데 모세관(capillary)이 사용된다. 고 품질의 용접을 위해 고온, 초음파 에너지, 기계적 압력 및 본딩 시간을 주의하여 제어할 필요가 있으며, 예를 들어 알루미늄 금속 상의 금 볼의 경우에, 용접은 5개의 일련의 금속간 금-알루미늄으로 구성되며, 단시간의 본딩 시간(5 내지 20 ms)내에 신속하게 개시될 필요가 있다.Conventionally, input / output pads of integrated circuit chips have been connected to the outside by metal wires that form a predetermined span. The metal of the input / output pad is typically composed of aluminum or copper and is commonly used as gold or copper wire material. In most semiconductor devices, capillary is used to attach one end of the connecting wire (eg gold) to the pad metal in a flattened ball shape. Careful control of high temperature, ultrasonic energy, mechanical pressure and bonding time is required for high quality welding, for example in the case of gold balls on aluminum metal, the welding consists of five series of intermetallic gold-aluminum And need to be started quickly within a short bonding time (5 to 20 ms).
접속 와이어의 다른 단부는 모세관에 의해 금속 표면에 스티치 본드 형태로(in form of a stitch bond) 부착된다. 다양한 반도체 디바이스에서, 금속 표면은 구리기 리드프레임 상에 증착된 은 플래시(silver flash)로 구성되며, 고온 및 기계적 압력(약 5 내지 20 ms 의 범위)에서 와이어 스티치가 형성되어, 금속간 확산이 발생된다. 웨지 본드를 형성하는데 모세관 대신에 웨지형의 툴을 사용하는 경우, 유사한 금속간 확산이 발생된다.The other end of the connecting wire is attached in form of a stitch bond to the metal surface by a capillary tube. In various semiconductor devices, the metal surface is composed of silver flash deposited on a copper base leadframe, and wire stitches are formed at high temperature and mechanical pressure (range of about 5 to 20 ms) so that intermetallic diffusion is achieved. Is generated. When using wedge-shaped tools instead of capillaries to form wedge bonds, similar intermetallic diffusion occurs.
와이어 본딩 동작은, 비젼 시스템(vision system)과 통상 결합된 자동화된 컴퓨터로 제어되는 본더(automated, computer-controlled bonder)에 의해 수행된다. 이것은 본딩 툴의 기하학적 위치 설정, 충격 속도 및 접촉력 및 본드 형성시의 휴지 시간(dwell time) 및 초음파 에너지와 같은 본딩 파라미터의 설정 및 제어를 가능케한다. 이러한 제어에도 불구하고, 본드의 품질은 최저 한계치거나 매우 불량하다. 대부분의 경우에, 근본 원인은 본드될 금속의 미지의 변수(예를 들어, 결정성 또는 경도) 또는 불충분하게 세정된 금속 표면(예를 들어, 검출되지 않은 산화, 유기 잔류물 또는 미립자 오염) 때문이다. 그러므로, 지난 십년 동안, 불량한 본드 품질 또는 제어불가능한 프로세스(run-away processes)를 가능한 한 일찍 식별하는 것을 목표로 하는 품질 테스트가 개발되어 왔다.Wire bonding operations are performed by an automated, computer-controlled bonder, typically coupled with a vision system. This allows the setting and control of bonding parameters such as the geometric positioning of the bonding tool, impact velocity and contact force, and dwell time and ultrasonic energy during bond formation. Despite this control, the quality of the bond is at its lowest limit or very poor. In most cases, the root cause is due to unknown variables (eg crystalline or hardness) of the metal to be bonded or insufficiently cleaned metal surfaces (eg undetected oxidation, organic residue or particulate contamination). to be. Therefore, over the last decade, quality tests have been developed that aim to identify poor bond quality or run-away processes as early as possible.
가장 중요하며 정기적으로 수행되는 테스트는 와이어 길이를 와이어 브레이크 지점(wire break point)까지 끌어 당기며, 와이어 부착, 특히 볼 본드를 절단 지점까지 절단하는 것이다. 이들 양 테스트 모두에서, 필요한 힘이 측정되며, 테스트는 파괴적이며 오프-라인으로 수행되어야 하지만, 비교적 빨리 수행된다. 다른 테스트는 매우 귀찮으며 시간을 소모하며, 이들 테스트는 금속 표면 또는 야금술의 횡단면의 화학적 에칭, 표면 오제 분석(surface Auger analysis) 또는 놉 금속 경도 분석(Knoop metal hardness analysis)을 포함한다. 물론, 이들 모든 테스트는 파괴적이고 오프-라인적이다.The most important and regularly performed test is pulling the wire length to the wire break point and cutting the wire attachment, especially the ball bond, to the cutting point. In both of these tests, the required force is measured and the test is destructive and must be performed off-line, but is performed relatively quickly. Other tests are very cumbersome and time consuming, and these tests include chemical etching, surface Auger analysis, or Knoop metal hardness analysis of metal surfaces or cross sections of metallurgy. Of course, all of these tests are disruptive and off-line.
<발명의 요약>Summary of the Invention
반도체 집적 회로(IC) 어셈블리에 대한 본 발명에 따르면, 와이어 본딩 및 와이어 품질 테스팅의 2가지 동작은 하나의 컴퓨터로 제어되는 시스템으로 결합되며, 하나의 툴 헤드는 먼저 본딩 동작을 수행한 후 테스팅 동작을 온-라인으로 실행하며, 마지막으로 본딩 처리를 지속하기 전에, 테스팅 결과에 기초하여 본딩 파라미터로 실시간 피드백으로 소정의 보정을 수행한다. 본 발명에 따르면, 결함이 있는 본드의 수가 거의 0으로 감소되며, 오프-라인 테스팅으로 인한 본딩 생성 비가동 시간(bonding production downtime)이 실질적으로 제거된다.According to the present invention for a semiconductor integrated circuit (IC) assembly, the two operations of wire bonding and wire quality testing are combined into one computer controlled system, one tool head performing the bonding operation first and then the testing operation. Is performed on-line, and finally, before continuing the bonding process, a predetermined correction is performed with real-time feedback with the bonding parameters based on the testing result. According to the present invention, the number of defective bonds is reduced to almost zero, and the bonding production downtime due to off-line testing is substantially eliminated.
본 발명은, 특히 다수의 입/출력 또는 본딩 패드를 갖는 고밀도 IC, 절연 기판 상에 장착된 칩, 금속 리드프레임을 사용하는 디바이스 및 소형 패키지 아웃라인 및 낮은 측면을 필요로 하는 디바이스에 관한 것이다. 이들 IC는 프로세서, 디지탈 및 아날로그 디바이스, 스텐다드 리니어 및 로직 프로덕트, 메모리, 고주파 및 고파워 디바이스 및 대형 및 소형 영역의 칩 카테고리와 같은 많은 반도체 디바이스 부류에서 발견될 수 있다. 본 발명은 셀룰러 통신 장치, 페이저, 하드 디스크 드라이브, 랩탑 컴퓨터 및 의료 기기 등과 같은 응용에서 빌트-인(built-in) 품질 및 신뢰성을 보장하는데 도움을 준다.The present invention relates in particular to high density ICs with multiple input / output or bonding pads, chips mounted on insulating substrates, devices using metal leadframes and devices requiring small package outlines and low side. These ICs can be found in many semiconductor device classes such as processors, digital and analog devices, standard linear and logic products, memory, high frequency and high power devices, and chip categories in large and small areas. The present invention helps to ensure built-in quality and reliability in applications such as cellular communication devices, pagers, hard disk drives, laptop computers and medical devices.
본 발명은 볼 본딩 및 웨지 본딩 변형의 경우 와이어 본딩 기술에서 통상 사용된 재료 및 기본 처리를 사용한다. 그러나, 본딩 처리는 통계적으로 의미 있는 개수의 약간의 본딩만을 완성한 후 테스트 데이타가 얻어질 수 있도록 본딩 처리가 변경된다. 테스트 데이타는 실시간으로 평가되고 본딩 파라미터의 포텐셜 보정으로 자동 변환되어, 본더로 피드백된다. 이러한 방식에서, 모든 후속 본드의 특징이 자동으로 개선된다.The present invention uses the materials and basic processing commonly used in wire bonding techniques in the case of ball bonding and wedge bonding variations. However, the bonding process changes only the bonding process so that test data can be obtained after completing only a statistically significant number of bondings. The test data is evaluated in real time and automatically converted into potential corrections of the bonding parameters and fed back to the bonder. In this way, the features of all subsequent bonds are automatically improved.
본 발명의 한 특징은 완전히 자동이며 본더 머신을 위한 부가적 장비 공간이 필요없는, 반도체 어셈블리에서 와이어 본딩과 와이어 테스팅 동작을 결합하는 기술을 제공하는 것이다. 이러한 특징은 와이어를 끌어당기고 본드를 밀치는 품질 테스트를 수행하고 필요한 힘을 기록하도록 설계된 본드 헤드에 근접하게 컴퓨터로 제어되는 툴을 부가하여 달성된다.One feature of the present invention is to provide a technique that combines wire bonding and wire testing operations in a semiconductor assembly that is fully automatic and requires no additional equipment space for the bonder machine. This feature is achieved by the addition of a computer controlled tool in close proximity to the bond head designed to perform quality tests that pull the wire, push the bond and record the force required.
본 발명의 다른 특징은 장비 변형 비용을 최소로 유지하고 새로운 기본 자본이 필요없도록 설치되어 있는 제조 장비 베이스를 사용하면서 이러한 목적들을 달성하는 것이다.Another feature of the present invention is to achieve these goals while using a manufacturing equipment base that is installed to keep equipment modification costs to a minimum and eliminate the need for a new base capital.
본 발명의 다른 특징은 상당한 본더 휴지 시간없이도 본드 품질을 개선하도록 본딩 파라미터가 보정될 수 있도록 테스팅 결과의 실시간 피드백을 제공하는 것이다. 이러한 특징은 본더로의 직접 피드백을 이용하여 테스트 데이타를 본딩 파라미터로 자동으로 변환함으로써 달성된다.Another feature of the present invention is to provide real-time feedback of the testing results so that the bonding parameters can be corrected to improve the bond quality without significant bond downtime. This feature is achieved by automatically converting test data into bonding parameters using direct feedback to the bonder.
본 발명의 다른 특징은 가변 결정성, 산화물 형성 및 적어도 어느 정도 우연한 불순물과 같은 칩 금속화에서의 변형을 수용하도록 본딩 처리에 융통성을 제공하는 것이다.Another feature of the present invention is to provide flexibility in the bonding process to accommodate variations in chip metallization, such as variable crystallinity, oxide formation and at least somewhat accidental impurities.
본 발명의 다른 특징은 웨지 본딩 기술 및 여러 부류의 반도체 IC 프로덕트에 뿐만 아니라 볼 본딩에 적용될 수 있도록 가요성을 가지며 몇몇 차세대 프로덕트에 적용될 수 있도록 보다 일반적인 어셈블리 개념을 도입하는 것이다.Another feature of the present invention is the introduction of a more general assembly concept that is flexible to be applied to ball bonding as well as to wedge bonding technology and various classes of semiconductor IC products.
이들 특징은 다용량 생성용으로 적합한 시스템 및 장치의 설계 개념 및 방법에 관련된 본 발명의 기술에 의해 달성된다.These features are achieved by the techniques of the present invention that relate to the design concepts and methods of systems and devices suitable for high capacity production.
와이어 테스팅 툴은 와이어를 끌어당기고 본딩을 밀치기에 적합한 제1 단부에 소정 특징을 갖는 연장형 암으로서 설계된다. 와이어 테스팅용의 이러한 툴은 와이어 본딩 처리 중에 후퇴될 수 있다.The wire testing tool is designed as an elongate arm with certain features at a first end suitable for pulling wire and pushing bonding. Such a tool for wire testing may be retracted during the wire bonding process.
본 발명의 한 실시예에서, 이러한 후퇴는 제2 단부를 통해 한 축 주위로 암을 회전시킴으로써 달성된다. 축은 본딩 툴을 동작시키는 툴 헤드에 부착된 지지 구조에 고정된다.In one embodiment of the invention, this retraction is achieved by rotating the arm about one axis through the second end. The axis is fixed to the support structure attached to the tool head for operating the bonding tool.
본 발명의 한 특징에 있어서, 지지 구조와 함께 암을 회전시킴으로써 후퇴가 달성되며, 이 경우 툴 헤드 근방에 회전축을 갖는다.In one aspect of the invention, retraction is achieved by rotating the arm together with the support structure, in which case it has an axis of rotation near the tool head.
이러한 특징들 이외에 본 발명에 나타난 기술적 이점은, 첨부된 도면 및 첨부된 청구범위를 고려하면 본 발명의 양호한 실시예에 대한 다음의 설명으로부터 분명해질 것이다.In addition to these features, the technical advantages shown in the present invention will become apparent from the following description of the preferred embodiments of the present invention in view of the accompanying drawings and the appended claims.
도 1은 와이어 본딩과 와이어 테스팅을 결합하고 본딩 파라미터들을 자동으로 보정하는 컴퓨터 시스템의 블럭도.1 is a block diagram of a computer system that combines wire bonding and wire testing and automatically corrects bonding parameters.
도 2는 리드프레임 상에 장착된 집적 회로 칩의 일부의 개략도.2 is a schematic diagram of a portion of an integrated circuit chip mounted on a leadframe.
도 3은 와이어 본딩 동작 중에 모세관의 첨단 및 그것의 이동을 개략적, 간략화한 횡단면도.3 is a schematic, simplified cross-sectional view of the tip of a capillary and its movement during wire bonding operation;
도 4a 및 4b는 본드 절단 품질 테스트의 소정 상태 동안 볼 본드의 개략적, 간략화한 횡단면도.4A and 4B are schematic, simplified cross-sectional views of ball bonds during a given state of bond cut quality test.
도 5는 본 발명의 툴 헤드의 제1 실시예의 개략적, 간략화한 사시도.5 is a schematic, simplified perspective view of a first embodiment of a tool head of the present invention.
도 6은 본 발명의 와이어 테스팅 툴의 개략적인 사시도.6 is a schematic perspective view of a wire testing tool of the present invention.
도 7a 및 7b는 본 발명의 툴 헤드의 제2 실시예의 개략적, 간략화한 사시도.7A and 7B are schematic, simplified perspective views of a second embodiment of a tool head of the present invention.
도 8a, 8b 및 8c는 본 발명에 따른 교정 처리의 소정 상태 중에 툴 헤드 및 비젼 서브시스템의 개략적, 간략화한 사시도.8A, 8B and 8C are schematic, simplified perspective views of a tool head and a vision subsystem during a given state of the calibration process according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
100 : 결합 시스템100: coupling system
101 : 장착된 칩101: chip installed
102 : 재료 처리 시스템102: Material Handling System
103 : 컴퓨터103: computer
105 : 본딩 툴105: bonding tool
106 : 툴 헤드106: tool head
107 : Z 구동기107 Z driver
108 : 테스트 툴108: test tool
109 : 비젼 서브시스템109: vision subsystem
110 : 테스트 데이타 저장 장치110: test data storage device
111 : 데이타 변환기111: data converter
112 : 본딩 파라미터 저장 장치112: bonding parameter storage device
본 발명의 양호한 실시예로서, 도 1은 집적 회로(IC) 칩 및 기판에 부착된 와이어 커넥션을 자동으로 본딩하고 테스팅하기 위한 결합 시스템(100)의 블록도를 도시한다. 칩은 통상적으로 지지대(기판의 일부일 수도 있음) 상에 장착되며, 도 1에서 장착된 칩은 참조 부호(101)로 나타나 있다. 장착된 칩은 시스템의 컴퓨터(103)에 결합된 재료 처리 서브 시스템(102)에 의해 시스템(100) 내외로 이동된다. 시스템 내에서, 장착형 칩(101)의 이동은 컴퓨터(103)에 또한 결합된 X-Y 테이블(104)에 의해 또한 조정될 수도 있다.As a preferred embodiment of the present invention, FIG. 1 shows a block diagram of a coupling system 100 for automatically bonding and testing wire connections attached to integrated circuit (IC) chips and substrates. The chip is typically mounted on a support (which may be part of a substrate), and the chip mounted in FIG. 1 is indicated by reference numeral 101. The mounted chip is moved into and out of the system 100 by a material processing subsystem 102 coupled to the system's computer 103. Within the system, the movement of the mounted chip 101 may also be adjusted by the X-Y table 104 also coupled to the computer 103.
좀더 상세히 설명하자면, 도 2는 기판에 대한 장착 칩 및 와이어 본드를 개략적으로 도시하고 있다. IC는 실리콘, 실리콘 게르마늄, 갈륨 비소 또는 전자 디바이스 제조시에 사용되는 임의의 다른 반도체 재료로 제조된 반도체 칩(201)의 액티브 표면으로 제조된다. 실리콘의 경우, 칩의 두께는 통상 225 내지 475 ㎛이다. 칩(201)은, 복수의 본딩 패드(203)를 갖는 액티브 회로측이 지지대로부터 일정 거리 이격되어 면해 있도록 지지대(202)(기판의 일부일 수도 있음) 상에 장착된다. 이러한 장착은 통상 부착 에폭시 또는 폴리이미드(도 3에서 (209)로 표시됨) 박막으로 수행된다,More specifically, FIG. 2 schematically illustrates mounting chips and wire bonds to a substrate. The IC is made of an active surface of a semiconductor chip 201 made of silicon, silicon germanium, gallium arsenide, or any other semiconductor material used in the manufacture of electronic devices. In the case of silicon, the thickness of the chip is usually 225 to 475 mu m. The chip 201 is mounted on the support 202 (which may be part of the substrate) such that the active circuit side having the plurality of bonding pads 203 faces away from the support at a predetermined distance. Such mounting is usually carried out with a thin film of adherent epoxy or polyimide (indicated by 209 in FIG. 3),
본딩 패드(203)는 측면 길이가 약 40 내지 150 ㎛, 양호하게는, 90 내지 100 ㎛인 구형, 사각형 또는 원형으로 형성된다. 입/출력 단자가 많은 IC의 경우, 인접한 본딩 패드들간의 피치는 통상 50 내지 200 ㎛ 범위, 양호하게는, 50 내지 75 ㎛이다. 도 2는 복수의 외부 접촉 패드(204)를 도시한다. 기판이 금속 리드프레임인 경우, 지지대(202)는 칩 장착 패드이며, 접촉 패드(204)는 외부 리드이다. 기판이 절연 매체 내에 장착된 도전성 패턴인 경우, 지지대(202)는 기판의 일부일 수도 있고, 접촉 패드(204)는 기판과 일체화된 금속 패드이다.The bonding pads 203 are formed into a spherical, square or circular shape having a side length of about 40 to 150 mu m, preferably 90 to 100 mu m. For ICs with many input / output terminals, the pitch between adjacent bonding pads is typically in the range of 50 to 200 μm, preferably 50 to 75 μm. 2 illustrates a plurality of external contact pads 204. When the substrate is a metal leadframe, the support 202 is a chip mounting pad and the contact pad 204 is an external lead. When the substrate is a conductive pattern mounted in an insulating medium, the support 202 may be part of the substrate, and the contact pad 204 is a metal pad integrated with the substrate.
본딩 패드(203)는 주로 0.5 내지 2 % 구리 및/또는 0.5 내지 1 % 실리콘으로 합금된 알루미늄으로 종종 이루어진다. 금속층의 두께는 약 0.4 내지 1.5 ㎛이다. 알루미늄은 주로 예를 들어 티타늄, 티타늄 질화물, 티타늄 텅스텐, 탄탈, 탄탈 질화물 또는 텅스텐 질화물의 박층(4 내지 20 ㎚)이다. 대안적으로, 본딩 패드(203)는 팔라듐, 금 또는 니켈 등의 접합가능한 금속 박막으로 피복된 구리(약 0.2 내지 1.0 ㎛ 두께)를 포함할 수도 있다.The bonding pads 203 are often made of aluminum alloyed primarily with 0.5-2% copper and / or 0.5-1% silicon. The thickness of the metal layer is about 0.4 to 1.5 mu m. Aluminum is mainly a thin layer (4-20 nm), for example of titanium, titanium nitride, titanium tungsten, tantalum, tantalum nitride or tungsten nitride. Alternatively, the bonding pads 203 may include copper (about 0.2-1.0 μm thick) coated with a bondable metal thin film such as palladium, gold or nickel.
와이어 커넥션(205)은 본딩 패드(203)와 접촉 패드(204) 사이에 상호 접속을 제공한다. 와이어 커넥션은 볼 본드(206)에 의해 본딩 패드(203)에 부착되며, 스티치 본드(207)에 의해 접촉 패드(204)에 부착된다. 대안적으로, 부착은 본딩 패드와 접촉 패드 상의 웨지 본드일 수도 있다. 2개의 부착 사이에 와이어 길이(208)가 연장된다.Wire connection 205 provides an interconnection between bonding pads 203 and contact pads 204. The wire connection is attached to the bonding pad 203 by ball bond 206 and to the contact pad 204 by stitch bond 207. Alternatively, the attachment may be a wedge bond on the bonding pad and the contact pad. The wire length 208 extends between the two attachments.
본 발명의 양호한 실시예에서, 직경이 약 18 내지 33 ㎛, 양호하게는 20 내지 25 ㎛인 표준 라운드형 와이어가 사용된다. 알루미늄 패드와의 본딩의 경우, 와이어는 베릴륨, 구리, 팔라듐, 철, 은, 칼슘 또는 마그네슘의 선택적으로 매우 작은 콘텐츠(때때로 볼 형성시 열-영향을 제어하도록 사용되며, 벤딩 또는 다른 변형 응력에 대해 기계적으로 약한)를 갖는 금으로 구성된다. 구리 패드와의 본딩의 경우, 와이어는 동일한 직경의 구리 또는 금으로 구성된다.In a preferred embodiment of the present invention, standard round wires of about 18 to 33 μm in diameter, preferably 20 to 25 μm are used. In the case of bonding with aluminum pads, the wire is optionally used to control the thermally-affecting (sometimes ball formation) of beryllium, copper, palladium, iron, silver, calcium or magnesium, Mechanically weak). In the case of bonding with a copper pad, the wire consists of copper or gold of the same diameter.
도 3에서, 와이어 본딩 처리는, 가열 받침대(heated pedesral) 상의 부착층(209)에 의해 지지대(202) 상에 장착된 칩(201)을 위치 설정함으로써 시작되어 150 내지 300 ℃ 온도로 상승된다. 와이어(205)는 첨단(301)을 갖는 모세관을 통해 고정된다. 와이어의 첨단에는, 프레임 또는 스파크 기술을 이용하여 프리 에어 볼(free air ball)이 생성된다. 이러한 볼은 통상적으로 와이어 직경이 약 1.2 내지 1.6이다. 모세관은 칩 본딩 패드쪽으로 이동되며, 볼은 패드의 금속화에 대해 압축되어, 네일 헤드 구성(302)이 생성된다. 알루미늄 패드의 경우, 압축력 및 초음파 에너지 조합은 금속간 금-알루미늄을 형성하여 강한 금속 접합을 발생시킨다. 압축력(Z- 또는 매시력(mash force)라 불림)은 통상적으로 약 17 내지 75 g이며, 초음파 시간은 약 10 내지 20 ms이며, 초음파력은 약 20 내지 50 mW 이다. 본딩시에, 온도는 일반적으로 150 내지 270 ℃이다. 구리 패드 상의 구리 와이어의 경우, 강한 결합을 발생시키기 위해 금속간 확산이 발생된다.In FIG. 3, the wire bonding process is started by positioning the chip 201 mounted on the support 202 by an adhesion layer 209 on a heated pedesral and raised to a temperature of 150 to 300 ° C. Wire 205 is secured through a capillary with tip 301. At the tip of the wire, free air balls are created using frame or spark technology. Such balls typically have a wire diameter of about 1.2 to 1.6. The capillary is moved towards the chip bonding pad, and the ball is compressed against metallization of the pad, resulting in a nail head configuration 302. In the case of aluminum pads, the compressive force and ultrasonic energy combinations form intermetallic gold-aluminum, resulting in strong metal bonding. The compressive force (called Z- or mash force) is typically about 17 to 75 g, the ultrasonic time is about 10 to 20 ms, and the ultrasonic force is about 20 to 50 mW. In bonding, the temperature is generally 150 to 270 ° C. In the case of copper wires on copper pads, intermetallic diffusion occurs to produce strong bonds.
소정의 컴퓨터 제어 방식으로 모세관을 에어를 통해 이동시키면, 정확히 정의된 형태의 와이어 루핑이 생성된다. 예를 들어, 모세관의 첨단은 도 3에 개략적으로 도시된 바와 같이 경로(303)를 따라가며 자연스러운 루프(304)를 형성한다. 최근 기술의 발달로 인해, 원형, 사다리꼴, 선형 및 주문형 루프 경로가 형성될 수 있다. 결국, 모세관은 소망의 목적지(305)에 도달된다. 모세관은 패드(204)에 접촉되도록 낮아지며, 모세관의 임프린트(imprint)에 따라, 금속 스티치 본드가 형성되며, 와이어가 절단되어 모세관이 이완된다. 스티치 접촉은 신뢰성이 적으며, 스티치 임프린트의 외부 치수는 와이어 직경의 약 1.5 내지 3 배이다(그것의 실제 형태는, 모세관 벽 두께 및 모세관 풋프린트와 같은, 사용된 모세관의 형태에 의존한다).Moving the capillary through the air in some computer-controlled fashion creates a wire looping of exactly defined form. For example, the tip of the capillary follows the path 303 as schematically shown in FIG. 3 to form a natural loop 304. Due to recent advances in technology, circular, trapezoidal, linear and custom loop paths can be formed. Eventually, the capillary reaches the desired destination 305. The capillary is lowered to contact pad 204, and upon imprint of the capillary, a metal stitch bond is formed, and the wire is cut to relax the capillary. Stitch contact is less reliable, and the outer dimension of the stitch imprint is about 1.5 to 3 times the wire diameter (its actual form depends on the type of capillary used, such as capillary wall thickness and capillary footprint).
대안적으로, 와이어 단부(302 및 305) 모두는 웨지 본드될 수 있다.Alternatively, both wire ends 302 and 305 may be wedge bonded.
와이어 본딩의 최근의 기술 진보로 인해, 소형의 신뢰성있는 볼 및 스티치 접촉 형성 및 와이어 루프(304)의 단단히 제어된 형태가 가능하다. 그러한 진보는, 예를 들어 미국 윌로우 그루브 쿠릭크 및 소파에 의해 컴퓨터화 본더 8020 또는 미국 텍사스주 달라스에 있는 텍사스 인스트루먼츠에 의한 ABACUS SA에서 찾아볼 수 있다.Recent technological advances in wire bonding allow for compact, reliable ball and stitch contact formation and tightly controlled form of wire loop 304. Such advances can be found, for example, in Computerized Bond 8020 by Willow Groove Corick and Couch, USA, or ABACUS SA by Texas Instruments, Dallas, Texas.
도 1을 참조하면, 모세관은 Z 구동기(107)에 결합되며 툴 헤드(106) 상의 벤딩 툴(105)의 일부이다. Z 구동기(107) 및 X-Y 테이블(104)은 컴퓨터(103)로부터 위치 설정 명령을 수신한다.Referring to FIG. 1, the capillary is coupled to the Z driver 107 and is part of the bending tool 105 on the tool head 106. Z driver 107 and X-Y table 104 receive positioning commands from computer 103.
도 1은 또한 Z 구동기 및 컴퓨터(103)에 결합된 테스팅 툴(108)을 또한 도시한다. 이러한 테스팅 툴은 본 발명의 중추부이며, 이것은 예를 들어 도 3에 도시된 바와 같이 와이어 길이(304), 볼 본드(302) 및 스티치 본드(305)에 의해 완성된 와이어 커넥션에 대해 후속 품질 테스트를 실행하도록 구성된다.1 also shows a testing tool 108 coupled to a Z driver and a computer 103. This testing tool is the backbone of the present invention, which, for example, performs subsequent quality tests on wire connections completed by wire length 304, ball bond 302 and stitch bond 305 as shown in FIG. Configured to execute.
와이어 끌어당기기(Wire Pull)Wire Pull
와이어를 끌어당기는(Wire Pulling) 테스트는 와이어 길이의 강도, 스티치 본드의 품질 및 본딩 장치의 성능을 측정한다. 양호하게는 훅크 모양으로 형성된 테스팅 툴은 와이어 길이를 잡고(툴의 정확한 위치 설정을 위한 규격화된 룰이 존재한다) 와이어 길이가 파손될 때까지 와이어 길이를 힘이 증가되는 쪽으로 들어올리는데 사용된다. 파손에 필요한 힘이 측정되어 테스트 데이타 저장 장치(도 1에 참조 부호(110)로 표시됨)에 기록된다. 그러나, 볼 본드의 강도에 관한 정보의 경우, 와이어를 끌어당기는 테스트는 본드 전단 응력 테스트(bond shear test)에 덜 민감한 진폭의 순서이다.The wire pulling test measures the strength of the wire length, the quality of the stitch bond and the performance of the bonding device. A testing tool, preferably formed in the shape of a hook, is used to hold the wire length (there are standardized rules for accurate positioning of the tool) and to lift the wire length towards the increasing force until the wire length is broken. The force required for breakage is measured and recorded in a test data storage device (indicated by reference numeral 110 in FIG. 1). However, for information regarding the strength of the ball bond, the test for pulling the wire is an order of magnitude less sensitive to the bond shear stress test.
결함있는 와이어 길이 파손은 와이어 길이를 따라 너무 낮은 인력 또는 오류 위치에서 나타나며, 그것은 와이어 길이의 오류 루핑, 가열 또는 벤딩으로 인해 약화된 와이어 존 또는 불완전한 본더 성능을 나타낸다.Defective wire length breakdown appears at too low attraction or error locations along the wire length, which indicates a weakened wire zone or incomplete bond performance due to error looping, heating or bending of the wire length.
본드 전단 응력(Bond Shear)Bond Shear
"본드 전단 응력(bond shearing)" 테스트는 볼 본드(또는 웨지 본드의 강도), 볼 금속과 본딩 패드 금속 사이에 형성된 금속간 품질(따라서, 본드 전단 응력은 웨이퍼 페브 처리(wafer fab process) 성능의 품질의 간접 측정이다) 및 본딩 파라미터의 효과를 측정한다. 양호하게는 평탄한 접촉면을 갖는 램 모양으로 형성된 테스팅 툴은 와이어 볼에 대해 외부측으로 밀고(툴의 정확한 위치 설정을 위한 규격화된 룰이 존재한다) 볼 전단 응력이 없어질 때까지 볼에 대한 외부력을 증가시키는데 사용된다. 전단 응력 제거에 필요한 힘은 측정되어 테스트 데이타 저장 장치(도 1에 참조 부호(110)으로 표시됨)에 기록된다. 그러나, 볼 전단 응력 테스트에서는 와이어 또는 스티치 본드 품질을 측정하지 않는다.The "bond shearing" test is a test of ball bond (or wedge bond strength), intermetallic quality formed between the ball metal and the bonding pad metal (thus, bond shear stress is a function of wafer fab process performance). Is an indirect measure of quality) and the effect of bonding parameters. The testing tool, preferably formed in the shape of a ram with a flat contact surface, pushes outward with respect to the wire ball (there are standardized rules for accurate positioning of the tool) and exerts external forces on the ball until there is no ball shear stress. Used to increase. The force required for shear stress relief is measured and recorded in a test data storage device (indicated by reference numeral 110 in FIG. 1). However, the ball shear stress test does not measure wire or stitch bond quality.
너무 낮은 전단 응력 또는 부적절한 위치에서의 결함있는 전단 응력은 불충분한 금속간 형성, 패드 금속의 리프팅, 패드 금속화 중에 반도체 부분의 리프팅, 와이어 전단 응력 또는 부적절한 위치에서의 볼 전단 응력을 나타낸다.Too low shear stress or defective shear stress at improper locations indicates insufficient intermetallic formation, lifting of pad metal, lifting of semiconductor portions during pad metallization, wire shear stress or ball shear stress at improper locations.
도 4a 및 4b에서, IC 칩(40)은 본드 패드 금속(41)을 갖는다. 도 4a에는, 패드 금속(41)과의 용접부에서 금속간(개별적으로 도시되지 않음)을 포함하는 볼 본드(42)가 형성된다. 전단 응력 램(43)은 평탄 표면(43a)을 갖는 터칭 볼(42)이다. 도 4b에서, 볼 본드(42)는 외측으로 이동하는 전단 응력 램(43)에 의해 볼 본드 용접 영역(44)에서 전단 응력이 제거되며, 전단 응력은 금속간 존을 통해 진행하므로, 본드의 품질을 테스트한다. 볼(42)의 주요부(46)는 여전히 와이어(45)에 부착되어 있다.In FIGS. 4A and 4B, the IC chip 40 has a bond pad metal 41. In FIG. 4A, a ball bond 42 including intermetallic (not separately shown) is formed at the weld with the pad metal 41. Shear stress ram 43 is a touching ball 42 having a flat surface 43a. In FIG. 4B, the shear bond is removed at the ball bond weld zone 44 by the shear stress ram 43 moving outward, and the shear stress proceeds through the intermetallic zone, thus the quality of the bond. Test The main portion 46 of the ball 42 is still attached to the wire 45.
도 1을 참조하면, 와이어를 끌어당기는 테스트 및 볼 전단 응력 테스트에 의해 얻어진 힘 데이타(force data)는 테스트 데이타 저장 장치(110)에 저장된다. 데이타 변환기(111)는 테스트 데이타를 본딩 툴(105)에 의해 생성되는 후속 와이어 길이 및 본드 부착용의 본딩 파라미터의 컴퓨터 제어(103)를 조정하는 지시로 변환한다. 보정된 본딩 파라미터는 컴퓨터(103)에 결합된 본딩 파라미터 저장 장치(112)에 저장된다. 이러한 보정된 본딩 파라미터를 사용하여, 결함 있는 본드의 수가 거의 0으로 감소되며, 오프-라인 테스팅 및 파라미터 보정으로 인한 본딩 생성 비가동 시간이 실질적으로 제거된다.Referring to FIG. 1, force data obtained by a wire pulling test and a ball shear stress test is stored in the test data storage device 110. The data converter 111 converts the test data into instructions for adjusting the computer control 103 of the subsequent wire lengths generated by the bonding tool 105 and the bonding parameters for bond attachment. The corrected bonding parameters are stored in a bonding parameter storage device 112 coupled to the computer 103. Using this corrected bonding parameter, the number of defective bonds is reduced to nearly zero, and the bond generation downtime due to off-line testing and parameter correction is substantially eliminated.
컴퓨터(103)에 결합된 비전 서브시스템(109)은 본드될 디바이스 및 툴 헤드의 본딩 및 테스팅 수단의 상대 위치를 정렬하는 기능을 한다. 또한, (도 8a, 8b 및 8c와 결부하여 논의되는) 교정 절차가 필요하다.Vision subsystem 109 coupled to computer 103 serves to align the relative positions of the bonding and testing means of the device and tool head to be bonded. There is also a need for a calibration procedure (discussed in conjunction with FIGS. 8A, 8B and 8C).
도 5는 본 발명의 툴 헤드의 양호한 실시예를 도시한다. 전체적으로 참조 부호(500)로 표시한 툴 헤드는 Z 축(Z 구동기)(502) 주위를 회전가능한 캐리어(501)를 갖는다. 캐리어(501)에는 본딩 수단(510) 및 테스팅 수단(520)이 부착되어 있다. 툴 헤드(500)는 리드 프레임 리드(504)에 와이어 본드되어 본드 품질이 테스트되는 IC 칩(503)에 근접하여 도시되어 있다. 본딩 수단(510)은 캐리어(501)에 고정된 암(511) 및 적절한 지지 구조에 모세관을 포함하는 본딩 툴(512)을 포함한다.5 shows a preferred embodiment of the tool head of the present invention. The tool head, indicated generally at 500, has a carrier 501 that is rotatable about the Z axis (Z driver) 502. The carrier 501 is attached with bonding means 510 and testing means 520. Tool head 500 is shown in close proximity to IC chip 503 that is wire bonded to lead frame lead 504 to test bond quality. The bonding means 510 comprises an arm 511 fixed to the carrier 501 and a bonding tool 512 comprising a capillary in an appropriate support structure.
테스팅 수단(520)은 캐리어(501)에 고정된 암(521) 및 축 주위로 회전가능하도록 암(521)에 부착된 테스팅 툴(522)을 포함한다. 테스팅 툴(522)을 이 축 주위로 회전시켜, 이러한 테스팅 툴은 와이어 본딩 동작 중에 본딩 툴(512)이 자유롭게 동작할 수 있도록 후퇴될 수 있다.The testing means 520 comprises an arm 521 fixed to the carrier 501 and a testing tool 522 attached to the arm 521 so as to be rotatable about an axis. By rotating the testing tool 522 about this axis, this testing tool can be retracted to allow the bonding tool 512 to operate freely during the wire bonding operation.
도 6은 테스팅 툴(522)을 보다 상세히 도시하고 있다. 전체적으로 참조 부호(600)로 나타낸 테스팅 툴은 종축(61)을 갖는 연장된 암(63) 모양으로 형성된다. 암(63)의 길이(63a)는 5 내지 6 ㎜이다. 양호한 실시예에서, 테스팅 툴은 스테인레스 스틸 또는 구리 등의 금속으로 이루어지며, 낮은 마모에 대해 강해야 하며, 와이어를 끌어당기고 밀치는 테스팅 조건 하에서의 최소 변형에 대해 충분히 튼튼해야 한다.6 illustrates testing tool 522 in more detail. The testing tool, shown generally at 600, is formed in the shape of an extended arm 63 with a longitudinal axis 61. The length 63a of the arm 63 is 5-6 mm. In a preferred embodiment, the testing tool is made of metal such as stainless steel or copper, must be resistant to low wear, and must be sufficiently robust against minimal deformation under testing conditions that pull and push the wire.
한 단부(64)에서, 테스팅 툴은 축(62) 주위로 회전할 수 있도록 (도 5에 도시된 바와 같이) 중추적 접합에 적합하다. 다른 단부(65)에서, 테스팅 툴은 암(63)에서 횡방향으로 연장되는 돌기부(66)를 갖는다. 양호한 실시예에서, 돌기부(66)는 돌기부의 길이(67a)에 대해 종축(61)으로부터 일반적으로 수직으로 연장된다. 일반적으로, 돌기부의 길이(67a)는 테스트될 와이어의 직경 및 길이의 주변에 따라 좌우된다. 예를 들어, 직경이 25 ㎛이고 피치가 150 ㎛인 와이어의 경우, 돌기부의 길이(67a)는 약 200 내지 250 ㎛일 수도 있다. 그 길이는 본더의 X-Y 위치 설정 정밀도 내에서 와이어를 붙잡을 수 있을 정도로 충분히 커야 하지만, 밀접하게 이격된 와이어 길이에 응용시 빈틈 없을 정도로 충분히 작다. 표면(67)은 와이어를 끌어당기는 테스트시에 와이어 길이를 붙잡도록 하는 외형을 나타내며, 통상적으로 표면은 후크 모양과 유사하다. 표면은, 잘못된 오류의 경우 테스트될 와이어에 흠이 발생되는 것을 방지하도록 곡선형 에지를 갖는다.At one end 64, the testing tool is suitable for pivotal bonding (as shown in FIG. 5) to be able to rotate about axis 62. At the other end 65, the testing tool has protrusions 66 extending transversely from the arm 63. In a preferred embodiment, the projection 66 extends generally perpendicular from the longitudinal axis 61 with respect to the length 67a of the projection. In general, the length 67a of the projection depends on the diameter of the wire to be tested and the perimeter of the length. For example, in the case of a wire having a diameter of 25 μm and a pitch of 150 μm, the length 67a of the protrusion may be about 200 to 250 μm. Its length should be large enough to hold the wire within the bonder's X-Y positioning precision, but small enough for application to closely spaced wire lengths. Surface 67 exhibits an appearance that allows the wire to be grasped during the test of pulling the wire, and typically the surface resembles a hook shape. The surface has curved edges to prevent flaws in the wire to be tested in case of false errors.
단부(65)는 본드 전단 응력 테스트시에 와이어 본드, 특히 볼 본드에 대해 밀치기에 적합한 적어도 하나의 표면(68)을 갖는다. 그 때문에, 툴(600)은 전단 응력 테스트를 수행하도록 수직 및 측면으로 이동하도록 동작가능하다. 양호한 실시예에서, 표면(68)은 와이어 본드에 대해 양호하게 정의된 접촉 표면을 제공하도록 평탄하다. 다른 실시예에서, 표면(68)은 곡선형일 수도 있다. 폭(68a)은 볼 본드 직경과 관련되며, 볼을 통해 절단될 정도로 작아서는 안되지만, 인접한 볼과 접촉될 정도로 커서도 안된다. 통상적인 폭은 75 내지 125 ㎛이다.End 65 has at least one surface 68 suitable for pushing against wire bonds, particularly ball bonds, in bond shear stress testing. As such, the tool 600 is operable to move vertically and laterally to perform a shear stress test. In a preferred embodiment, the surface 68 is flat to provide a well defined contact surface for the wire bonds. In other embodiments, the surface 68 may be curved. Width 68a is related to the ball bond diameter and should not be small enough to cut through the ball, but should be large enough to be in contact with adjacent balls. Typical widths are 75 to 125 μm.
전단 응력 접촉 표면(68)에는 툴(600)의 하부 표면(68b)이 관련된다. (본 기술 분야의 숙련자는, 본 발명의 장치 및 어셈블 리가 다양한 상태 및 방식으로 사용될 수 있으므로, "하부" 및 "단" 등의 용어가 설명의 목적으로만 사용되었다는 것을 알 수 있을 것이다). 표면의 형태는 과도한 툴 마모 없이 포지티브 접지(positive touchdown) 검출 및 와이어들간의 돌기부(67) 구동시의 용이성을 제공한다. 하부면(68b)의 평탄성은, 그 내부로 파지 않고도 표면과의 접촉을 용이하게 하며, 그 경사는 파손하지 않고도 와이어를 밀치는 것을 가능케 한다.Shear stress contact surface 68 is associated with bottom surface 68b of tool 600. (A person of ordinary skill in the art will recognize that the terms "lower" and "end", etc., are used for illustrative purposes only, as the devices and assemblies of the present invention may be used in a variety of states and ways.) The shape of the surface provides positive touchdown detection and ease in driving the projections 67 between the wires without excessive tool wear. The flatness of the bottom surface 68b facilitates contact with the surface without digging into it, and the inclination allows the wire to be pushed without breaking.
도 7a 및 7b는 일반적으로 참조 부호(700)로 표시된 툴 헤드의 구성에 있어서의 본 발명의 다른 실시예를 도시한다. 툴 헤드는 Z 축(Z 구동기;702) 주위를 회전할 수 있는 캐리어(701)를 갖는다. 캐리어(701)에는 본딩 수단(710) 및 테스팅 수단(720)이 부착되어 있다. 도 7a에서, 툴 헤드(700)는 리드 프레임 리드(704)에 와이어 본드되며 본드 품질이 테스트될 IC 칩(703)에 근접하여 도시되어 있다. 본딩 수단(710)은 캐리어(701)에 고정된 암(711) 및 적절한 지지 구조 내에 모세관을 포함하는 본딩 툴(712)을 포함한다.7A and 7B show another embodiment of the present invention in the construction of a tool head, generally indicated at 700. The tool head has a carrier 701 that can rotate about the Z axis (Z driver) 702. Bonding means 710 and testing means 720 are attached to the carrier 701. In FIG. 7A, tool head 700 is shown in close proximity to IC chip 703 that is wire bonded to lead frame lead 704 and bond quality is to be tested. The bonding means 710 comprises an arm 711 fixed to the carrier 701 and a bonding tool 712 comprising a capillary in a suitable support structure.
테스팅 수단(720)은 와이어 본딩 동작시에 본딩 툴(712)이 자유롭게 동작할 수 있도록 테스팅 수단(720)을 후퇴하기 위한 축(723) 주위로 회전가능한 암(721)을 포함한다. 실제 테스팅 툴(722)은 암(721)에 고정된다. 도 7a는 암(721)의 테스트 위치를 도시하며, 도 7b는 본딩 동작 중의 암(721)의 위치를 도시한다. 도 5에 도시된 실시예에 비해 도 7a 및 7b에 도시된 실시예의 이점은, 본딩 중에 회전 관성이 작다는 점이며, 단점은 툴 후퇴를 위해 필요한 여유 공간이 보다 크다는 점이다.The testing means 720 includes an arm 721 rotatable about an axis 723 for retracting the testing means 720 so that the bonding tool 712 can operate freely during the wire bonding operation. The actual testing tool 722 is fixed to the arm 721. FIG. 7A shows the test position of the arm 721 and FIG. 7B shows the position of the arm 721 during the bonding operation. Advantages of the embodiment shown in FIGS. 7A and 7B over the embodiment shown in FIG. 5 are the low rotational inertia during bonding, and the disadvantage is that the free space required for tool retraction is greater.
도 7b에 도시된 후퇴를 수행하기 위한 옵션으로는 솔레노이드, 압전 스택, 마이크로-로터리 모터 및 에어 실린더가 포함한다.Options for performing the retraction shown in FIG. 7B include solenoids, piezo stacks, micro-rotary motors and air cylinders.
IC 칩과 기판(예를 들어, 리드 프레임) 사이의 컴퓨터 제어형 본딩 및 와이어 커넥션 테스팅 및 이러한 테스팅에 응답하여 본딩 파라미터를 자동으로 조정하는 방법은 다음과 같은 처리 단계들, 즉,Computer controlled bonding and wire connection testing between the IC chip and the substrate (e.g., lead frame) and a method for automatically adjusting the bonding parameters in response to such testing include the following processing steps:
* 도 3과 결부하여 상술된 컴퓨터 제어하에서 칩과 기판간의 와이어 커넥션을 형성하여, 테스팅 툴이 후퇴 위치인 동안 볼 및 스티치 부착 및 와이어 길이를 생성하는 단계;Forming a wire connection between the chip and the substrate under the computer control described above in conjunction with FIG. 3 to create ball and stitch attachment and wire length while the testing tool is in the retracted position;
* -- 테스팅 영역의 본딩 툴 클리어를 얻기 위해 위쪽으로 Z축을 경사지게 하고,*-Tilt the Z axis upward to get the bonding tool clear of the testing area,
-- 테스트 툴 접지에 클리어런스를 제공하는 교정된 오프셋만큼 X 및 Y 위치 설정 시스템을 이동함으로써 본딩 툴을 테스트 장치로 이동시키는 단계;Moving the bonding tool to the test apparatus by moving the X and Y positioning system by a calibrated offset providing clearance to test tool ground;
* 공칭 "부하 없는" 힘 측정을 설정하도록 테스트 영역을 통해 몇몇 X-Y 통과를 수행하는 단계;Performing some X-Y passes through the test area to establish a nominal “load-free” force measurement;
* 테스팅 툴을 테스칭 위치로 회전시키는 단계;Rotating the testing tool to the testing position;
* 테스팅 툴을 이용하여 Z 축 접지 교정을 수행하는 단계;Performing Z axis ground calibration using a testing tool;
* 전단 응력 테스팅을 위해 프로그램된 양만큼 Z축을 상승시키는 단계;Raising the Z axis by a programmed amount for shear stress testing;
* X-Y 축을 사용하여, 전기적 전류를 테스트 데이타로서 기록하면서 와이어 볼을 전단 변형시키도록 테스트 툴을 구동하는 단계;Using the X-Y axis to drive the test tool to shear strain the wire ball while recording electrical current as test data;
* 전기적 전류로부터 전단 응력을 계산하는 단계;Calculating the shear stress from the electrical current;
* 후속 와이어 커넥션시에 와이어를 끌어당기는 테스팅을 위해 Z 및 X-Y 축의 역할을 역전시키는 단계 - 즉, 테스팅용 툴을 위치 설정하기 위해 X-Y 축을 사용하고, 테스트 측정 중에는 툴 이동을 위해 Z축을 사용하는 단계 -; 및Inverting the role of the Z and XY axes for testing to pull the wire on subsequent wire connections-using the XY axis to position the tool for testing, and using the Z axis to move the tool during test measurements. -; And
* 테스트 데이타에 응답하는 후속 와이어 커넥션의 본딩 파라미터를 자동을 조정하는 단계Automatically adjusting the bonding parameters of subsequent wire connections in response to the test data
로 예시된다.Is illustrated.
도 8a, 8b 및 8c는 테스팅 수단의 교정 처리 단계를 도시한다. 각 도면에는 툴 헤드(801) 및 비젼 서브시스템(802)의 사시도가 도시되어 있다. 툴 헤드(801)에는 본딩 툴(803) 및 테스팅 툴(804)이 부착되어 있다. 테스팅 툴은, IC 제조시에 통상적으로 사용되는 알루미늄과 금속 경도 특성이 유사한 실제 칩 본딩 패드 또는 일반적 미러형 표면일 수도 있는 금속화된 테스팅 표면(805) 상부에 도시되어 있다. 도 8a, 8b 및 8c의 모션 화살표의 써포트를 사용하여, 후속되는 교정 처리 단계는 다음과 같다:8A, 8B and 8C show the calibration process steps of the testing means. Each figure shows a perspective view of tool head 801 and vision subsystem 802. The tool head 801 is attached with a bonding tool 803 and a testing tool 804. The testing tool is shown on top of the metallized testing surface 805, which may be an actual chip bonding pad or a general mirrored surface that is similar in metal hardness properties to aluminum commonly used in IC fabrication. Using the support of the motion arrows of FIGS. 8A, 8B and 8C, the following calibration process steps are as follows:
* 테스팅 장치에 툴 헤드(801)를 배치하는 단계;Placing the tool head 801 in the testing apparatus;
* 단부가 횡방향 돌출면 영역(805)을 갖도록 테스트 영역(805) 상부에 테스트 툴(804)을 배치하는 단계;Placing the test tool 804 over the test region 805 so that the end has a transversely projecting surface region 805;
* X-Y 테이블의 연관된 X-Y 위치를 자동으로 기록하는 단계;Automatically recording the associated X-Y position of the X-Y table;
* Z 구동기를 사용하여, 표면(805)과의 접촉부(도 8b에서 위치(806))로 테스트 툴(804)을 이끄는 단계;Directing the test tool 804 to contact with the surface 805 (position 806 in FIG. 8B) using the Z driver;
* Z 구동기의 연관된 Z 위치를 자동으로 기록하는 단계;Automatically recording the associated Z position of the Z driver;
* Z 구동기를 사용하여, 영역(805) 내에 가시적인 마크(807)(도 6에서 툴(600)의 하부면(68b)를 나타냄)를 생성하도록 테스팅 툴(804)을 이용하여 충분한 압력을 가하는 단계;Using a Z driver, applying sufficient pressure with the testing tool 804 to create a visible mark 807 (representing the bottom surface 68b of the tool 600 in FIG. 6) in the area 805. step;
* 표면(805) 상부의 테스트 툴(804)을 상승시키는 단계;Raising the test tool 804 over the surface 805;
* X-Y 테이블을 사용하여, 비젼 서브시스템(802)의 뷰(808) 필드를 이동하여, 툴 마크(807)의 장소를 근사화하는 단계(도 8c 참조);Using an X-Y table to move the field of view 808 of the vision subsystem 802 to approximate the location of the tool mark 807 (see FIG. 8C);
* X-Y 위치를 자동으로 기록하는 단계;* Automatically recording the X-Y position;
* 비젼 서브시스템을 사용하여, 툴 마크(807) 형태의 정확한 위치를 결정하는 단계;Using the vision subsystem to determine the exact position of the tool mark 807;
* 테스팅 툴(804) 이외에 본딩 툴(803)을 사용하는 모든 교정 처리 단계를 반복하는 단계; 및Repeating all calibration processing steps using the bonding tool 803 in addition to the testing tool 804; And
* 본딩 툴(803), 테스팅 툴(804) 및 비젼 서브시스템(802)의 정확한 상대 위치를 자동으로 교정하는 단계.Automatically correcting the exact relative position of the bonding tool 803, the testing tool 804, and the vision subsystem 802.
본 발명은, 예시적 실시예를 참조로 설명되었지만, 이러한 설명은 제한적 의미로 해석되어서는 안된다. 본 기술 분야의 숙련자는 본 명세서를 참고로 하여 본 발명의 다른 실시예뿐만 아니라 예시된 실시예의 다양한 변형 및 조합이 가능하다는 것을 알 수 있을 것이다. 예를 들어, 반도체 칩의 재료로는 실리콘, 실리콘 게르마늄, 갈륨 비소 또는 반도체 제조시 사용되는 다른 반도체 재료가 포함될 수도 있다. 다른 예로서, 개선된 본더로서는, 일본 도꾜도의 Shinkawa Electric Company Ltd.에서 제조된 Shinkawa UTC-200과 같은 장비를 포함할 수도 있다. 그러므로, 첨부된 특허청구범위는 그러한 임의의 변형 또는 실시예를 포함할 것으로 의도된다.Although the present invention has been described with reference to exemplary embodiments, this description should not be interpreted in a limiting sense. Those skilled in the art will appreciate that various modifications and combinations of the illustrated embodiments, as well as other embodiments of the invention, are possible with reference to the specification. For example, the material of the semiconductor chip may include silicon, silicon germanium, gallium arsenide or other semiconductor materials used in the manufacture of semiconductors. As another example, the improved bonder may include equipment such as Shinkawa UTC-200 manufactured by Shinkawa Electric Company Ltd. of Tokyo, Japan. Therefore, the appended claims are intended to cover any such modifications or embodiments.
본 발명은 완전히 자동이며 본더 머신을 위한 부가적 장비 공간이 필요없는, 반도체 어셈블리에서 와이어 본딩과 와이어 테스팅 동작을 결합하는 기술을 제공한다. 본 발명은 또한 장비 변형 비용을 최소로 유지하고 새로운 기본 자본이 필요없도록 설치되어 있는 제조 장비 베이스를 사용하는 것이며, 또한 상당한 본더 휴지 시간 없이도 본드 품질을 개선하도록 본딩 파라미터가 보정될 수 있도록 테스팅 결과의 실시간 피드백을 제공한다.The present invention provides a technique that combines wire bonding and wire testing operations in a semiconductor assembly that is fully automatic and requires no additional equipment space for the bond machine. The present invention also uses a manufacturing equipment base that is installed to keep equipment modification costs to a minimum and eliminates the need for a new base capital, and also allows for testing parameters to be calibrated to improve the bonding quality without significant bond downtime. Provide real-time feedback.
Claims (23)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11839699P | 1999-02-02 | 1999-02-02 | |
US60/118,396 | 1999-02-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20000057851A true KR20000057851A (en) | 2000-09-25 |
KR100777862B1 KR100777862B1 (en) | 2007-11-21 |
Family
ID=22378320
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR20000004832A KR100777862B1 (en) | 1999-02-02 | 2000-02-01 | Combined system, method and apparatus for wire bonding and testing |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2000223526A (en) |
KR (1) | KR100777862B1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100442697B1 (en) * | 2002-03-11 | 2004-08-02 | 삼성전자주식회사 | Integrated Management System for automated wire bonding processes |
KR100604316B1 (en) * | 2004-06-18 | 2006-07-24 | 삼성테크윈 주식회사 | Wire bonder wherein bonding parameters are automatically setted |
KR102127892B1 (en) | 2013-06-03 | 2020-06-29 | 삼성전자주식회사 | Method of detecting faults of operation recipes in a wire bonding machine and apparatus for performing the same |
CN111856249B (en) * | 2020-07-24 | 2022-12-13 | 安测半导体技术(江苏)有限公司 | Chip test monitoring method, client and system |
CN115533294B (en) * | 2022-12-05 | 2023-03-21 | 宁波尚进自动化科技有限公司 | BTO automatic adjusting system and method of lead bonding machine |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100215340B1 (en) * | 1996-10-18 | 1999-08-16 | 윤종용 | Wire bonder for semiconductor package |
KR19980034123A (en) * | 1996-11-05 | 1998-08-05 | 김광호 | Bonding Control System of Semiconductor Package |
-
2000
- 2000-02-01 KR KR20000004832A patent/KR100777862B1/en active IP Right Grant
- 2000-02-02 JP JP2000025075A patent/JP2000223526A/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
JP2000223526A (en) | 2000-08-11 |
KR100777862B1 (en) | 2007-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6564115B1 (en) | Combined system, method and apparatus for wire bonding and testing | |
US7170304B2 (en) | Selectively configurable probe structures, e.g., selectively configurable probe cards for testing microelectronic components | |
US6034440A (en) | Method of improving interconnect of semiconductor devices by utilizing a flattened ball bond | |
EP0686454A1 (en) | Capillary and method of bonding | |
US9899348B2 (en) | Wire bonding apparatus and method of manufacturing semiconductor device | |
US6715658B2 (en) | Ultra fine pitch capillary | |
EP1381489B1 (en) | Controlled attenuation capillary | |
US6321969B1 (en) | Efficient energy transfer capillary | |
US6555401B2 (en) | Method of controlling bond process quality by measuring wire bond features | |
US20120032354A1 (en) | Wirebonding method and device enabling high-speed reverse wedge bonding of wire bonds | |
KR100777862B1 (en) | Combined system, method and apparatus for wire bonding and testing | |
WO2005018864A2 (en) | Capillary with contained inner chamfer | |
US9887174B2 (en) | Semiconductor device manufacturing method, semiconductor device, and wire bonding apparatus | |
US5269452A (en) | Method and apparatus for wirebonding | |
US6305594B1 (en) | Wire bonding method and apparatus | |
JP2809198B2 (en) | Bonding tool | |
JP2003332363A (en) | Bonding apparatus and method for manufacturing semiconductor device | |
US7705473B2 (en) | Methods and apparatus for determining pad height for a wire-bonding operation in an integrated circuit | |
Nguyen et al. | 70/spl mu/m fine pitch wirebonding | |
Dehaine et al. | Single point ILB at narrow pitch | |
EP1017099A2 (en) | Improvements in or relating to semiconductor devices | |
Lum et al. | 8-Microelectronics wire bonding | |
JPS63211640A (en) | Wire bonding method, wire bonding device and manufacture of semiconductor device using wire bonding device | |
JP3702963B2 (en) | Manufacturing method of semiconductor integrated circuit device | |
Zhong | Recent developments in wire bonding |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121030 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20131030 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20141030 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20150930 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20161028 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20170929 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20180928 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20190924 Year of fee payment: 13 |