KR20000055537A - system for driving of an LCD apparatus and method for an LCD panel - Google Patents

Abstract

PURPOSE: A system for driving liquid crystal display and method for driving liquid crystal panel is provided to enable users to improve charging rate so as to enhance the level of source voltage which will bring enhanced images of the screen. CONSTITUTION: A plasma displaying device with electromagnetic wave screen layer includes the following components. A control TS switching produces a converted wave. The same figures of waves are created in a series. Each waves are authenticated as electrodes according to raw and column of liquid crystal panel(22). A switch level of output voltage is generated through resistant strings. The device enables users to enhance charging rate and improve the level of source voltage so as to produce a better quality of image on the screen.

Description

System for driving of an LCD apparatus and method for an LCD panel

The present invention relates to a driving system of a liquid crystal display device. More particularly, the present invention relates to a temporal superimposition state of a source voltage and a gate voltage applied to each pixel of a liquid crystal module, and a waveform of the source voltage by adjusting a waveform of the source voltage. The present invention relates to a driving system and a liquid crystal panel driving method of a liquid crystal display device so that a desired gray scale can be expressed.

A liquid crystal display device, which is a type of flat panel display device, utilizes the electrical properties of liquid crystals whose light transmittance varies depending on the voltage applied to each pixel. Widely used.

A liquid crystal display device receives an image signal and consists of a liquid crystal module, a backlight assembly, and other fixtures. The liquid crystal module is formed by connecting a liquid crystal panel and a printed circuit board, and a source / gate drive integrated circuit and other elements on the printed circuit board. Components such as controllers are mounted.

Among them, a screen is formed in the liquid crystal panel, a source voltage and a gate voltage are applied to each pixel of the liquid crystal panel, and a gate voltage is applied to switch the source voltage, that is, the data signal. In this case, the gate voltage is applied to a gate electrode of a thin film transistor (TFT) forming a pixel through a gate line formed in the liquid crystal panel, and the TFT is turned on or off according to the level of the gate voltage. When the TFT is turned on or off in accordance with the gate voltage, the arrangement of the liquid crystals varies according to the degree of charge determined between the pixel electrode and the counter electrode by the level of the source voltage, and thus the transmittance is changed.

The liquid crystal is driven for each pixel by the method described above to form a predetermined screen on the liquid crystal panel.

Recently, liquid crystal modules have been developed to have high resolution, and in order to realize high resolution, the turn-on time of the gate voltage is reduced to less than 15 kHz. However, when the turn-on time of the gate voltage is reduced, the time required to charge and charge the source voltage for driving the liquid crystal is reduced by that amount, thereby causing a problem.

This will be described in detail with reference to FIGS. 1 to 3.

In FIG. 1, a gate voltage and a source voltage respectively output from the gate drive integrated circuit 4 and the source drive integrated circuit 6 are applied to the liquid crystal module 2, and the gate voltage is applied to turn on / off the pixels. It is sequentially and repeatedly supplied to (2) in the longitudinal direction, and the source voltage is repeatedly and sequentially supplied to the liquid crystal module 2 in order to drive the liquid crystal. These two voltages are adjusted to overlap the time applied for each pixel by the control signal.

In general, in the conventional case, a delay of a time for applying the gate voltage is generated from the ① position to the ② position of the liquid crystal panel 2, and a delay of a time for the source voltage is applied from the ① position to the ③ position.

In detail, the gate voltage and the source voltage are normally applied as shown in FIG. Here, the gate voltage swings between a turn-on voltage Von of about 20 V and a turn-off voltage Voff of -7 V, the source voltage is adjusted to swing between the black and white levels, and the source voltage for each pixel is set to a specific gray level. It has a voltage value to express.

And, the rising time of the source voltage is later than the gate voltage by the time Ts required for driving. The polling time of the source voltage is also later than the polling time of the gate voltage by Tg.

In the liquid crystal panel 2, there are resistances and capacitances due to the gate lines and the source lines, and these resistances and capacitances have an effect of delaying the application time of the source voltage and the gate voltage. The waveform changes as the waveform moves away from the initial application position as shown in FIG. 2B or 2C due to capacitance.

The source voltage is applied to the liquid crystal module 2 by the gray voltages supplied from the gray scale generator (not shown) having the resistance string as shown in FIG. 3 and applied to the liquid crystal module 2, and the resistor R1 for gray scale generation. In the resistor string in which the resistors RG1, RG2, RG3, and RG4 are connected in series, the gray voltage Vg2 +, the gray voltage VG1 +, the gray voltage Vg0, the gray voltage Vg1-, and the gray voltage Vg2- are output for each branched position.

In the above-described conventional liquid crystal display device, the source voltage and the gate voltage applied to the liquid crystal panel are delayed in time as the waveform is deformed as shown in FIG. 2B or 2C. It is slightly delayed as shown in FIG. 2B, and the source voltage is delayed as shown in FIG.

The source voltage for each pixel must reach a voltage for expressing the gray level when the gate voltage is turned on. However, as described above, when the liquid crystal panel is designed such that the gate voltage has a turn-on time of 15 ms or less, each pixel rises after about 2 to 3 ms after the gate voltage turns on, and in this environment, It is difficult for each pixel to be charged with the voltage for representing the actual specific gray level within the remaining time.

An object of the present invention is to realize a high resolution by modifying the waveform of the source voltage applied to the liquid crystal panel so that the source voltage is charged to each pixel at a desired level within a short time.

Other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

1 is a block diagram illustrating a driving of a conventional liquid crystal module.

2A through 2C are waveform diagrams illustrating a state in which a gate voltage and a source voltage are applied to each pixel of FIG. 1.

FIG. 3 is a circuit diagram illustrating a resistor string configured to generate a gray voltage supplied to a source drive integrated circuit of FIG. 1.

4 is a block diagram showing a preferred embodiment of a drive system for a liquid crystal display according to the present invention.

5 is a detailed block diagram of a source drive integrated circuit of a liquid crystal display device.

6 is a waveform diagram of signals applied to a source drive integrated circuit.

7 is a detailed block diagram of a gate drive integrated circuit of a liquid crystal display.

8A to 8C are waveform diagrams showing waveforms of a gate signal and a source signal applied to each position of a liquid crystal panel according to a first embodiment of the present invention.

9 is a waveform diagram correlating a source signal and a gate signal applied to a liquid crystal panel.

FIG. 10 is a waveform diagram illustrating a correlation between a gradation control signal, a gradation voltage, and a vertical clock signal.

Fig. 11 is a circuit diagram showing the first embodiment of the gradation generator for realizing the present invention.

Fig. 12 is a waveform diagram showing the output of the first embodiment of the gradation generator which is constituted by the embodiment of the present invention.

Fig. 13 is a circuit diagram showing a second embodiment of the gradation generator for implementing the present invention.

Fig. 14 is a circuit diagram showing a third embodiment of the gradation generator for implementing the present invention.

15A to 15C correlate waveforms of a gate signal and a source signal applied for each position of a liquid crystal panel according to a second embodiment of the present invention.

FIG. 16 is a waveform diagram showing a correlation between a source signal and a gate signal applied to another liquid crystal panel of the present invention.

A driving system of a liquid crystal display according to the present invention includes a liquid crystal panel driven by application of a source voltage and a gate voltage, a gate voltage generator for outputting a gate voltage to be applied to the liquid crystal panel, and color data each having a plurality of bits; The controller performs predetermined signal processing, including timing format setting, and outputs the processed color data, the source control signal, the gate control signal, and the gray scale control signal, and divides a predetermined constant voltage to correspond to a plurality of gray levels. It is required by the gray scale generator, the gate voltage generator, the controller and the gray scale generator to output a voltage and switch the output of the gray voltage as the gray scale control signal to load at least one pulse waveform on the gray voltage. A voltage generator providing constant voltages of a predetermined level A source drive integrated circuit and the gate which are applied with a voltage, and output a voltage having a desired level among the gray scale voltages as the source voltage as the color data and the source control signal, and sequentially output the source voltage in the transverse direction of the liquid crystal panel. A gate drive integrated circuit configured to receive an output voltage of a voltage generator and sequentially and repeatedly output in the longitudinal direction of the liquid crystal panel by the gate control signal, and apply a gate voltage applied to a predetermined pixel of the liquid crystal panel The timing is adjusted so that the pulse waveform is located before a predetermined time point in time.

The controller may be configured to output a load signal included in the control signal applied to output a source signal from the source drive integrated circuit as a gray scale control signal.

The controller may be configured such that a source signal applied to the liquid crystal panel from the source drive integrated circuit is delayed for a predetermined time after the application of the gate signal applied to the pixel of the liquid crystal panel ends.

In addition, the pulse waveform is preferably configured to be applied for 2 to 4㎲ before the gate signal is applied.

The liquid crystal panel driving method according to the present invention is sequentially applied to the pixels of the liquid crystal panel in a predetermined order in the vertical and horizontal directions from a gate drive integrated circuit and a source drive integrated circuit, and the source voltage is applied to the pixels. The voltage is applied to the pixel from a predetermined time before the rising time of the voltage to a predetermined time after the polling time.

The source voltage may be applied as quickly as the width of the load signal that determines the output of the source voltage among the control signals applied to the source drive integrated circuit.

The source voltage may be applied by loading a pulse having a different level in a section before the gate signal is applied.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention is configured to apply a source voltage applied to the liquid crystal panel from a predetermined time before the gate voltage is applied, and the driving system of the liquid crystal display device receives a color signal and a control signal of a predetermined bit from a predetermined signal source as shown in FIG. 4. It is configured to receive DC power.

The present invention can be divided into the first embodiment and the second embodiment according to the waveform of the source voltage, the first embodiment is to apply a pulse to the pixel before the gate voltage of the source voltage is applied to the pixel, The second embodiment is to maintain and apply the source voltage from a predetermined time before the gate voltage is applied until after a predetermined time after the application of the gate voltage is terminated.

First, referring to the first embodiment of the present invention, in FIG. 4, the color data and the control signal are input to the controller 10, and the DC power is provided to the power supply 12.

The power supply unit 12 is configured to supply constant voltages necessary for the operation of the controller 10, the gray scale generator 14, and the gate voltage generator 16, and the gate voltage generator 16 is a gate drive integrated circuit 18. The gray level generator 14 is configured to supply the gray level voltages to the source drive integrated circuit 20. The controller 10 outputs a control signal for driving the data and data for determining a gray level for each pixel to the source drive integrated circuit 20, and outputs a control signal for switching control to the gate drive integrated circuit 18. It is configured to.

Here, the controller 10 outputs the gray scale control signal TS for controlling the output of the gray scale voltage to the gray scale generator 14, and the gray scale generator 14 receives the gray scale control signal TS and receives the gray scale control signal TS from FIG. As described below with reference to FIG. 2, a pulse is applied to the gray voltages for a predetermined Ts time before the gate signal rises, and is output to the source drive integrated circuit 20.

Here, the gray scale generator 14 may be variously implemented as shown in FIGS. 11, 13, and 14 to be described later.

5 and 6, the source drive integrated circuit 20 of FIG. 4 includes a shift resist 30, a latch 32, a digital / analog converter 34, and a buffer 36. The resist 30 receives the horizontal clock signal H_CLK and the shift signal STH having a predetermined frequency. In this case, the horizontal clock signal H_CLK has a frequency in which the frequency of the mast clock signal input to the controller 10 is divided into two or four parts, and the shift signal STH is inputted with one pulse every one horizontal period.

The shift resist 30 is configured to sequentially output pulses to the latch 32 in the horizontal direction in a predetermined number of clock units based on the horizontal clock signal H_CLK. When the shift output of the corresponding capacity is completed, a carry out signal is generated. The carry out signal is then applied to the next shift resist (not shown) for output shift operation.

Then, the data for the image output from the controller 10 is serially input to the latch 32, the latch 32 stores the serial data in the order in which the output of the shift resist 30 is shifted and input and the load signal Output data when TP is input.

The digital / analog converter 34 encodes data input from the latch 32 to select a gray voltage to be output for each source line, and selects a specific voltage among the gray voltages applied from the gray generator 14. The encoded result is selected and output from the digital / analog converter 34 to the buffer 36. The output of these gray voltages is performed for each line according to the data input order of the latch 32.

As described above, the gray voltages output from the digital / analog converter 34 are applied to the buffer 36, and the gray voltages are regulated in the buffer 36 and applied to the liquid crystal panel 22 as a source voltage.

7, the gate drive integrated circuit 18 of FIG. 4 includes a shift resist 40, a level shift 42, and an amplifier 44.

The shift resist 40 receives the shift signal STV and the vertical clock signal V_CLK, and the clock output is sequentially made in the longitudinal direction, and the shift resist 40 has the output in the longitudinal direction sequentially, after which the carryout signal is different. Input as a carry-in signal of a shift resist (not shown).

The level shift 42 receives the turn-on voltage Von and the turn-off voltage Voff from the gate voltage generator 16, and converts the level of the input signal of the level shift 42 into the above-described turn-on voltage or turn-off voltage level. The amplification section 44 amplifies the input signal to a predetermined gain value and inputs it to the liquid crystal panel 22 as a gate signal. In this case, the amplifier 44 determines the output by the output enable signal OE.

The source voltage and the gate voltage output by the first embodiment according to the present invention are shown in FIG. 8A. Referring to FIG. 8A, the gate voltage is switched between a Voff level of −7V and a Von of 20V with a temporal width of 15 ms or less. The source voltage is swinged between an arbitrary V + and V-, and the source voltage is loaded with a pulse having a time Ts of about 2 to 3 ms before the rising time of the gate voltage and delayed for a predetermined time Tg after the polling time of the gate voltage. . In this case, the V + and V− levels of the source voltage may be determined by the polarity and the switching voltage of the liquid crystal.

For example, the source voltage swings between 0V and 7V when the liquid crystal is in 3.3V switching mode, and the source voltage swings between 0V and 10V when the liquid crystal is in 5V switching mode. Accordingly, when the liquid crystal is in the switching mode of 3.3 V, the black level becomes 7 V (V +) for the non-inverted pixel to which the positive polarity is applied, and 0 V (V +) to the inverted pixel to which the negative polarity is applied. When the liquid crystal is in the 5 V switching mode, the black level becomes 10 V (V +) for the non-inverted pixel to which the positive polarity is applied, and the black level becomes 0 V (V +) to the inverted pixel to which the negative polarity is applied. Then, the white level V− becomes an intermediate value of the entire source voltage range that is swinged.

In addition, the waveforms of the source voltage and the gate voltage applied according to the position of the liquid crystal panel 22 may vary. That is, the source voltage is not changed in the waveform at the position close to the source drive integrated circuit 20, but the distance is changed as shown in Figure 8c due to the influence of the resistance and capacitance. In addition, although the waveform does not change at a position close to the gate drive integrated circuit 18, the gate voltage is changed as shown in FIG. 8B due to the influence of resistance and capacitance.

As a result, the waveform as shown in FIG. 8A is applied at the ⓐ position of the liquid crystal panel 22 of FIG. 4, the waveform as shown in FIG. 8B is applied at the ⓑ position, and the waveform as shown in FIG. 8C is applied at the © position. The waveforms of FIGS. 8A to 8C are applied to each pixel as shown in FIG. 9 by a method of line inversion or dot inversion in which the waveforms of the liquid crystal panel 22 have polarity according to the rows and columns of the liquid crystal panel 22. .

As described above, the waveform of FIG. 8A is formed according to the gray voltage output of the resistance strings of FIGS. 11, 12, and 13 to be described later by the switching of the gray scale control signal TS, and the gray scale control outputting the determination of the gray voltage. The correlation between the gray scale voltage and the vertical clock signal V_CLK based on the signal TS will be described first with reference to FIG. 10.

The gray scale control signal TS is generated at the rising point of the load signal Tp and is applied from the controller to the gray scale generator, and the pulse delay time is determined to be about 2 ms to 3 ms.

When the gray scale control signal TS is generated and applied as a pulse, the gray scale voltage output from the gray scale generator is output as a waveform containing a pulse having a predetermined high level. At this time, it is preferable that the rising timing coincides with the gray scale control signal TS and the falling timing coincides with the rising timing of the vertical clock signal V_CLK. The pulse generation time of the gradation control signal TS and the pulse of the gradation voltage is appropriately about 2 ms to 3 ms as described above.

The above-described waveform determination of FIG. 10 is based on the operation of the gray scale generator 14, and the gray voltage is as described above in the first embodiment of the gray scale generator 14 and the gray scale generator 14 of FIG. 13. And the third embodiment of the gradation generator 14 of FIG.

Referring to FIG. 11, two divided resistance strings are configured in the gray scale generator 14, and the first resistance string is configured to output a gray voltage selected when a positive polarity is made, and the second resistance string is negative. It is a configuration for outputting a gradation voltage selected when bipolarity is made.

In the first resistor string, resistors R21, RG21, RG22, R22, and a p MOS transistor Q3 are configured in series and a constant voltage Va is applied.

The gray scale control signal TS is applied to the gate side of the p MOS transistor Q3. The resistors R21 and R22 are regulating resistors for outputting a gray voltage, and grayscale voltages are output through nodes between resistors R21 and R22, respectively.

In the second resistor string, resistors R23, RG25, RG26 and RG27 are configured in series and the above-described constant voltage Va is applied. The p MOS transistor Q4 is configured in parallel to the resistors RG25 to RG 27, and a signal TS- in which the gray scale control signal TS is inverted is applied to the gate of the p MOS transistor Q4.

The load control signal TP applied to the source drive integrated circuit may be used as the gray scale control signal TS, and the timing may be set to about 2 to 3 ms, similarly or identical to the Tp signal.

As described above, the first and second resistor strings are configured in the gray scale generator 14, and the p MOS transistor Q3 is turned on and the p MOS transistor Q4 is turned off to maintain a constant voltage Va through nodes between the resistors. Each of the divided voltages is output.

When the gray scale control signal TS as shown in FIG. 12 is applied to the gate of the p MOS transistor Q3, the p MOS transistor Q3 is turned off when the gray scale control signal TS is at a high level, and the p MOS transistor Q4 is conversely opposite to the gray scale control signal TS- at a low level. Is turned on.

Accordingly, when the gray scale control signal TS pulse is applied to each of the p MOS transistors Q3 and Q4 in different phases, the gray scale voltage output through the nodes between the resistors RG21 and R22 of the first resistor string is constant Va during the pulse application period. Becomes The gray voltage output through the nodes between the resistor R23 and the resistor RG27 of the second resistor string is constantly lowered to the ground level during the pulse application period.

Thereafter, when the gray scale control signal TS is returned, the level of the gray scale voltage output through each node of the first and second resistance strings is returned to its original state. The time when the gray scale control signal is applied is about 2 to 3 ms before the time when the gate signal is converted from the Voff level to the Von level.

As described above, the gray voltage is supplied from the source drive integrated circuit 20 to the liquid crystal panel 22 by the gray voltage supplied from the source drive integrated circuit 20 as shown in FIG. 12. Becomes as shown in Fig. 8A. At this time, the time for outputting the source voltage is adjusted to a predetermined time after being applied from about 2 to 3 kV before the gate voltage is applied according to the divided clock.

Meanwhile, the gray scale generator 14 may be configured as shown in FIG. 13 as a second embodiment.

That is, a resistor string to which the constant voltage Va is applied is configured, and the resistor string is connected in series with a resistor R11, a resistor RG11, a resistor RG12, a p MOS transistor Q1, a resistor RG14, a resistor RG15, and a resistor R12. The constant voltage Va is applied to the gate of the p MOS transistor Q1 through the resistor R13, and the p MOS transistor Q2 is connected to the resistor R13. A logic level control signal TS is applied to the gate of the p MOS transistor Q2.

The gray-scale voltages Vg22 +, VG11 +... Where the constant voltage Va is divided by the nodes between the respective resistors in the state where the p MOS transistor Q1 is turned on as described above. Vg11- and Vg22- are output. At this time, the P MOS transistor Q2 is turned off. The p MOS transistor Q1 is switched in conjunction with the switching state of the p MOS transistor Q2, and the p MOS transistor Q1 is turned off when the p MOS transistor Q2 is turned on, and the p MOS transistor Q1 is turned on when the p MOS transistor Q2 is turned off. do.

When TS is applied to the p MOS transistor Q2 as the gray scale control signal, the p MOS transistor Q1 is switched as the p MOS transistor Q2 is switched. When the p MOS transistor Q1 is turned off, the voltage Va is output as a gray voltage through a node between the resistors connected between the resistor RG11 and the p MOS transistor. The gray level voltage of the ground level is output through a node between the resistors connected between the p MOS transistor Q1 and the resistor R12.

Therefore, the second embodiment of the gray scale generator 14 has an output as shown in FIG. 12 in which a pulse is applied to the gray scale voltage as described above.

When the gray scale generator 14 of FIG. 11 is modified, the resistance string of FIG. 14 may be configured in the gray scale generator 14 as a third embodiment.

Referring to FIG. 14, a third resistor string and a fourth resistor string are configured, and the third resistor string includes a resistor R31, a resistor RG31, a resistor RG32. The resistor R32 and the p MOS transistor Q5 are connected in series, and the fourth resistor string includes the resistors R33, RG35, RG36. RG37 is connected in series. The source side of the p MOS transistor Q4 is configured to be connected to the gate of the p MOS transistor Q5 and a node between the resistor R33 and the resistor RG35, and the p MOS transistor Q4 is connected in parallel to the resistors RG35 to RG37, and the p MOS transistor The gray scale control signal TS- is applied to the gate of Q4.

By the above configuration, the p MOS transistor Q5 is turned on when the p MOS transistor Q4 is turned off, and the gate voltage of the level at which the voltage Va is divided is output through the node between the resistors. When the P-MOS transistor Q4 is switched by the gray level control signal TS-, the pulse waveform having Va level is applied to the gray level voltage output from the third resistor string, and the ground voltage is applied to the gray voltage output to the fourth resistor string. A pulse waveform having a level is applied to the gradation voltage. Therefore, the gray scale voltage as shown in FIG. 12 is output.

As described above, the gray scale generator 14 may be variously implemented as shown in FIGS. 11, 13, and 14.

In the first embodiment according to the present invention, a gray voltage as shown in FIG. 12 is applied, and accordingly, a gate signal and a source signal are applied to each pixel as shown in FIGS. 8 and 9.

Therefore, before the gate voltage is applied, the source voltage is applied in advance and precharged. When the pixel is turned on by the gate voltage, the precharged voltage is applied to the pixel electrode. Therefore, even if the application time of the gate voltage is adjusted to a level of 15 mA or less, an equal voltage may be applied to the pixel electrode at the same gray level in each region corresponding to the pixel sufficiently. In particular, a source voltage may be applied to the pixel electrode at a voltage having a desired gray scale value within a limited gate turn-on time even for a pixel that is affected by resistance and capacitance away from the application side.

In addition, the present invention can obtain a similar effect to the first embodiment by applying the source voltage in a waveform different from that shown in FIG. 8A as the second embodiment.

That is, as shown in FIG. 15A, the charging rate is improved by applying a source voltage before and after a predetermined time before the gate voltage is applied. Even in the method of the second exemplary embodiment illustrated in FIG. 14A, as shown in FIGS. 15B and 15C, the waveform may be modified by charging due to the influence of resistance and capacitance as the gate voltage and the source voltage are applied to the terminal.

However, the time for which the source voltage is charged to the pixel before the gate voltage is applied can be secured to reach the gradation level to be applied to the pixel. That is, the charging rate is improved by changing the source voltage application method.

Also in the above-described second embodiment, the gate signal and the source signal are applied to each pixel as shown in FIG. 16, and the source signal may be applied in a dot inversion or a line inversion method.

As described in detail above, the present invention has been described in detail with respect to preferred embodiments, but those skilled in the art to which the present invention pertains, various embodiments of the present invention without departing from the spirit and scope of the present invention It will be appreciated that the present invention may be modified or modified as described above.

Therefore, according to the present invention, since the charging rate at which the source voltage is charged for each pixel is improved, the level of the source voltage is improved so that the desired gradation level is sufficiently reached during the gate signal application time limited by the influence of the resistance and capacitance of the liquid crystal panel. The uniformity of the gray scale of the screen is secured, so that the image quality is improved.

Claims (11)

A liquid crystal panel driven by application of a source voltage and a gate voltage; A gate voltage generator configured to output a gate voltage to be applied to the liquid crystal panel; A controller configured to perform predetermined signal processing, including timing format setting, on the color data and the control signals each having a plurality of bits, and output the signal-processed color data, the source control signal, the gate control signal, and the gray scale control signal; A gradation voltage generator for dividing a predetermined constant voltage to output a gradation voltage corresponding to a plurality of gradations, and switching the output of the gradation voltage as the gradation control signal to load and output at least one pulse waveform on the gradation voltage; A voltage generator providing constant voltages of a predetermined level required by the gate voltage generator, the controller, and the gray scale generator; A source drive integrated circuit receiving the gray voltage and outputting a voltage having a desired level among the gray voltages as a source voltage as the color data and a source control signal, and sequentially outputting the source voltage in a horizontal direction of the liquid crystal panel; And A gate drive integrated circuit receiving the output voltage of the gate voltage generator and repeatedly outputting the gate voltage signal in the longitudinal direction of the liquid crystal panel according to the gate control signal, And a timing is adjusted such that the pulse waveform is positioned a predetermined time before a gate voltage applied to a predetermined pixel of the liquid crystal panel is applied. The method of claim 1, And the controller is configured to output a load signal included in the control signal applied to output a source signal from the source drive integrated circuit as a gray scale control signal. The method of claim 2, And the controller is configured to output a source signal applied to the liquid crystal panel from the source drive integrated circuit to be delayed for a predetermined time after the application of the gate signal applied to the pixel of the liquid crystal panel ends. The method of claim 1, And the pulse waveform is configured to be applied for 2 to 4 kHz before the gate signal is applied. The display device of claim 1, wherein the gray voltage generator comprises: a gray voltage generator; A predetermined number of first series resistors, a first load regulating resistor, and a first switching element to which a constant voltage is applied are connected in series, and the first load regulating resistor and the first switching element are located on the ground side of the series connected resistors, A first resistor string for outputting gray level voltages of which the constant voltage is divided for each node of the first series resistors according to a switching state of the first switching element; A predetermined number of second series resistors are connected in series to a second load regulating resistor to which the constant voltage is applied, and a second switching device is connected in parallel to the second series resistors, and in a switching state of the second switching device. Therefore, a second resistance string for outputting the gray voltages divided by the constant voltage for each node of the second series resistors is provided. The first load regulating resistor is a resistor for compensating a load value of the second resistor string, and the second load regulating resistor is a resistor for compensating a load value of the first resistor string, and the first switching element and the second switching. And the switching state is changed by the gray scale control signal input from the controller, and the switching states are set in reverse. The display device of claim 1, wherein the gray voltage generator comprises: a gray voltage generator; A predetermined number of series resistors to which a constant voltage is applied are bisected by the third switching element, and are configured to output a gradation voltage for each node according to a switching state, and the third switching element is applied by switching a voltage having the same level as the constant voltage. A drive system for a liquid crystal display device, characterized in that configured to be switched by the output of the switching means. The method of claim 6, The switching means has a resistance to which the constant voltage is applied and is connected to the control side of the switching element, and a fourth switching element switched by the gradation control signal input from the controller is connected to the resistance to thereby control the gradation control signal. And a voltage is applied to the third switching element in accordance with a state. The method of claim 1, wherein the gray voltage generator; A predetermined number of third series resistors, a third load regulating resistor and a third switching element to which a constant voltage is applied are connected in series, and the third load regulating resistor and the third switching element are located on the ground side of the series connected resistors, A third resistor string for outputting gray level voltages of which the constant voltage is divided for each node of the third series resistors according to a switching state of the third switching element; A predetermined number of fourth series resistors are connected in series to the fourth load regulating resistor to which the constant voltage is applied, and a fourth switching device is connected in parallel to the fourth series resistors and is connected to the switching state of the fourth switching device. Therefore, the fourth resistor string includes a fourth resistor string for outputting the gray voltages divided by the constant voltage for each node of the fourth series resistors. The third load regulating resistor is a resistor for compensating the load value of the fourth resistor string, the fourth load regulating resistor is a resistor for compensating the load value of the third resistor string, and the third switching element is the fourth. And a fourth switching element operated in response to a control signal input from the controller. The gate drive integrated circuit and the source drive integrated circuit are sequentially applied to the pixels of the liquid crystal panel in a predetermined order in the vertical and horizontal directions, and the source voltage is polled from a predetermined time before the rising time of the gate voltage applied to the pixels. The liquid crystal panel driving method of claim 1, wherein the display device is applied to the pixel from a point in time to a predetermined point in time. The method of claim 9, And the source voltage is applied as fast as a width of a load signal that determines an output of the source voltage among control signals applied to the source drive integrated circuit. The method of claim 9, And the source voltage is applied by applying a pulse having a different level in a section before the gate signal is applied.