KR20000048092A - Tungsten nitride as an oxygen diffusion barrier when used with tantalum pentoxide as part of a metal-oxide-metal capacitor - Google Patents

Abstract

PURPOSE: A method is provided to use a capacitor having a tungsten nitride diffusing barrier instead of a titanium nitride in an integrated circuit when a dielectric material is a five oxide tantalum. CONSTITUTION: A method for manufacturing a capacitor includes steps of forming a first electrode(220), which includes a first barrier layer and a titanium layer selected from the group consisted of a tungsten nitride, a nitrided tungsten silicide(225) and a mixture of them, and which there is really not the titanium nitride layer, on a substrate, forming a dielectric material of the capacitor, which is reduced by the titanium, on the first electrode, and forming a second electrode including an electrical conductive layer(140) on the dielectric material of the capacitor.

Description

Tungsten nitride as an oxygen diffusion barrier when used with tantalum pentoxide as part of a metal-oxide-metal capacitor}

TECHNICAL FIELD The present invention relates to integrated circuits and, more specifically, to an integrated circuit having a capacitor.

In general, the range of use of integrated circuits, and more particularly CMOS, is widening as the user's demand continues to increase for enhanced functionality and improved gain. To meet this requirement, the integrated circuit industry continues to shrink the size of circuit structures to form more circuits within the same size integrated circuit area, increasing the integrated density for a given chip size. In recent years, the structure has progressed from the conventional 1.2 micron gate region (1 megabit capacity) to the latest 0.25 micron (1 gigabit capacity), and will become even smaller in the near future.

Due to the ever-increasing demands on computer memory for increasing computational power and data storage capacity, intensive development is taking place, for example, in the field of dynamic random access memory (DRAM), especially embedded DRAM. . In general, DRAM is usually a collection of transistor elements, each having an integrated circuit capacitor connected to a source electrode to constitute a memory cell. Afterwards, a group of memory cells is arranged in a memory structure using word lines and bit lines to give an address to each memory cell. This integrated capacitor may store a charge to represent a logic "1" as indicated by the word and bit control lines or a logic "0" to store no charge.

The structure of these memory capacitors is typically constructed using a 0.25 micron tungsten (W) plug structure connected to the source of the transistor, followed by a barrier layer, a bottom electrode, a dielectric layer material such as tantalum pentoxide, followed by the top electrode. Support it as it is. Capacitors have a variety of uses in integrated circuits.

As the technology for the size of the CMOS is gradually reduced, as described above, the structure for a given memory size or circuit capacity is equally reduced. The bond pads connecting the integrated circuits to the external circuits cannot be reduced indefinitely, for example. At present, the integrated circuit package includes about 200 50 micron x 50 micron bond pads. The reduced topology associated with the lower limit size of the bond pads creates excessive space around the bond pads. This allows the insertion of additional impregnated memory around the bond pads. The use of high dielectric constant oxides such as tantalum pentoxide in place of silicon dioxide allows for smaller structures.

In order to add the above-mentioned memory to certain conventional CMOS technologies, some manufacturers have formed barrier layers with titanium (Ti) bottom electrodes using conventional silicon dioxide using titanium nitride (TiN). Ti / TiN / 2 silicon oxide / Al / TiN. However, problems arise from the shift from silicon dioxide to tantalum pentoxide (Ta ₂ O ₆ ), which is used as the dielectric layer of the capacitor. The lower Ti layer removes oxygen from the tantalum pentoxide by diffusion through the barrier, reducing tantalum pentoxide to the Ta element, so that an electrical leakage path can be created or shorted. Use of the same structure is excluded. This results in degradation or failure of general circuit performance. If TiN is not optimally deposited, there will be mini cracks or other defects that will form a fast diffusion path.

The interdiffusion of oxygen through TiN described above also oxidizes the underlying Ti. In addition, the TiN underlayer decomposes at about 600 ° C., making subsequent high temperature processing impossible. Accordingly, there is a need for a CMOS technology and a fabrication process that can add impregnated memory without substantially changing the fabrication process commonly used in conventional CMOS technology.

In order to solve the above-mentioned deficiencies of the prior art, the present invention provides a method of using a capacitor having an integrated tungsten nitride (WN) barrier in an integrated circuit instead of titanium nitride when the dielectric is tantalum pentoxide.

In another embodiment, tungsten nitride silicide (WSIN) is used instead of or in addition to titanium nitride when the dielectric is tantalum pentoxide. Silicon contained in WSIN does not easily reduce tantalum pentoxide, so tungsten nitride silicide is an effective barrier.

The capacitor is optionally applied in a memory having a transistor in contact with a connection formed in a dielectric overlapping the transistor. In one embodiment, the memory includes a capacitor located on the dielectric layer in contact with the connection. In this particular embodiment, the capacitor comprises a first electrode located on the connection, the first electrode comprising a titanium layer and tungsten nitride or tungsten nitride silicide and substantially free of titanium nitride layer. Tungsten nitride is preferred. In addition, the thickness of the first electrode may vary depending on the design. However, in one particular embodiment, the first electrode may have a thickness in the range of about 10 nm to about 60 nm.

In the present invention, the capacitor further comprises a capacitor dielectric positioned on the first electrode reduced by titanium. For example, in one embodiment, the capacitor dielectric may be tantalum pentoxide. Additionally, the capacitor includes a second electrode located on the capacitor dielectric.

In another embodiment, the first electrode includes a barrier layer in contact with a capacitor dielectric positioned between the first electrode and the capacitor dielectric. The barrier layer prevents or inhibits cross diffusion of various materials. In this embodiment, the barrier layer may be made of tungsten nitride. In yet another embodiment, the barrier layer may be tungsten nitride silicide and the barrier has a thickness of about 100 nm or less.

In further embodiments, the top electrode may comprise one or both of tungsten nitride and tungsten nitride silicide.

Since the foregoing is a broader and better optional feature of the present invention, those skilled in the art will better understand the following detailed description of the invention. Further features of the invention are described below and form the claims of the invention. It will be apparent to those skilled in the art that the outlined and specific embodiments described above can be readily utilized as a basis for designing or implementing other configurations for carrying out the same purposes of the present invention. In addition, those skilled in the art may realize the equivalent configuration in the widest form without departing from the spirit and scope of the present invention.

The invention is explained in more detail below with reference to the accompanying drawings for a more complete understanding.

1 is a cross-sectional view of a conventional embedded memory cell structure.

2 is a cross-sectional view of one embodiment of an impregnated memory cell structure in accordance with the present invention.

* Description of the simple symbols for the main parts of the drawings *

205 transistor structure 206 source region

207: line 208: bit line

209: drain region 210: interconnect

First, referring to FIG. 1, a conventional capacitor is shown as part of an embedded memory cell structure 100 showing the transistor structure 105, the connection 110, and the capacitor 115. The memory capacitor 105 includes a first (lower) electrode comprising an adhesive / conductive layer 120 and a barrier layer 125, a dielectric material 130, an electrically conductive layer 140, and an optional TiN layer 135. It includes an upper electrode comprising a. As mentioned above, tungsten (W) is typically used with a 0.25 micron technique to form the connection 110. In FIG. 1, titanium (Ti) is used to form layer 120 with titanium nitride (TiN) forming layer 125. Dielectric layer 130 is then formed using silicon dioxide or tantalum pentoxide, with aluminum or copper forming layer 140.

As mentioned above, the Ti / TiN layer is in contact with tantalum pentoxide, which causes Ti to chemically reduce tantalum pentoxide. This results in electrical leakage passages or deficiencies that lead to general circuit degradation or defects and hence poor device reliability when the dielectric is tantalum pentoxide.

Referring now to FIG. 2, this illustrates a preferred embodiment of the capacitor of the present invention, an impregnated memory cell structure 200 showing the transistor structure 205 and the interconnect 210 in contact with the capacitor 215. As shown. The capacitor 215 comprises a first (bottom) electrode comprising a barrier layer comprising a tungsten nitride or tungsten nitride silicide 225 disposed on the adhesive / electrically conductive layer 220 and interconnects as shown; And a barrier layer including an insulating material 230 reduced by titanium located on the first electrode, a second electrode 240 disposed over the insulating material, and an optional layer 235. In the embodiment shown in FIG. 2, the first layer disposed on the interconnect is titanium, and layer 225 is tungsten nitride, tungsten nitride silicide, or any combination thereof. In a preferred embodiment, the first electrodes are laminated to a thickness of 10 to 60 nm at a temperature of approximately 150 to 400 ° C. under a pressure of approximately 2 to 6 milliTorr. Lamination of the first electrode is accomplished by physical vapor deposition at a power of approximately 1-12 kilowatts. Tungsten nitride or tungsten nitride silicide is used to form layer 225 by reactive sputtering of tungsten or tungsten silicide in nitrogen. Tungsten silicide and tungsten nitride may be laminated as functionally gradient materials, where nitrogen and silicon contents are inevitably made to smoothly change within the film thickness. Thereafter, the insulating layer 230 is formed using tantalum pentoxide by a conventional deposition method. Finally, aluminum or copper forms a layer 235 used to make electrical connections. Layer 235 may optionally be capped with titanium nitride or typically tungsten nitride or tungsten silicide.

It should be noted that deposition of tungsten nitride and tungsten nitride silicide may also be achieved by chemical vapor deposition (CVD). Tungsten nitride is usually applied using WF ₆ and ammonia (NH ₃ ) as precursors, and Si ₂ H ₆ is added and mixed to make tungsten nitride silicide. However, the present invention is usually made in the absence of ammonia which generates hydrogen. Without being bound by any theory, it is believed that hydrogen reduces tantalum pentoxide. When using CVD, nitrogen trifluoride should be used as the nitrogen source instead of ammonia.

The embodiment shown in FIG. 2 is almost free of titanium nitride (TiN) at the first electrode, which eliminates the possibility of back reaction with an insulating material using tantalum pentoxide. That is, a reliable oxygen diffusion barrier is provided between the titanium and the insulator in order to prevent the reduction of the insulator which will cause electrical degradation in the structure. In addition, tungsten nitride and tungsten nitride silicides extend thermal costs to allow processing at 800 ° C. prior to deposition of the upper electrode as TiN that is not present decomposes around 600 ° C. Another advantage associated with reducing oxygen diffusion is obtained when a layer of tungsten nitride or tungsten nitride silicide (not shown) is inserted between the insulating layer 230 and the conductive layer 235. Tungsten nitride and tungsten nitride silicide may also be replaced with titanium nitride in select layer 240. Layer 240 is removed by etching when in contact with the top of the electrode.

As shown, the first electrode 220 contacts the interconnect 210, which in turn contacts the source region 206 of the transistor 205. The transistor 205 of the impregnated memory may be a conventional design in that it includes a word (word) line 207, a bit line 208, and a drain region 209. An insulating layer, such as silicon dioxide, is formed over the transistor 205 to electrically insulate it.

Embodiments of the capacitor stack-ups of the present invention include Ti / WN or WSiN or both / Ta ₂ O ₆ or other titanium reducing insulators / WN or WSiN or both / Al or other electrical conductors, Ti / WN or WSiN or Ta ₂ O ₆ or other titanium reducing insulator / WN or WSiN or both / Al or other electrical conductor / TiN.

From the foregoing, it will be apparent that the present invention provides an impregnated memory having a transistor in contact with an interconnect formed in an insulating layer over the transistor for use with an integrated circuit. The impregnation memory may include a capacitor disposed on an insulating layer in contact with the interconnect.

While the invention has been described in detail, those skilled in the art will recognize that various changes and modifications can be made without departing from the spirit and scope of the claims.

According to the present invention, there is provided a CMOS technology and a fabrication process that can add impregnated memory without substantially changing the fabrication process commonly used in conventional CMOS technology.

Claims (20)

Forming a first electrode on the substrate, the first electrode comprising a titanium layer and a first barrier layer selected from the group consisting of tungsten nitride and tungsten nitride silicide and mixtures thereof; Forming a capacitor dielectric on the first electrode to be reduced by titanium; Forming a second electrode over the capacitor dielectric, the second electrode comprising an electrically conductive layer. The method of claim 1, wherein forming the second electrode comprises depositing a second barrier layer selected from the group consisting of tungsten nitride, tungsten nitride silicide, and mixtures thereof, And the second barrier layer is positioned between the capacitor dielectric and the electrically conductive layer. 2. The method of claim 1, wherein forming the capacitor dielectric comprises forming a capacitor dielectric from tantalum pentoxide. The method of claim 1, wherein the barrier layer is in contact with the capacitor dielectric and is located between the first electrode and the capacitor. The method of claim 1 wherein the barrier layer is tungsten nitride and has a thickness of less than about 60 nm. The method of claim 1, wherein forming the first electrode comprises forming a first electrode having a thickness in a range from about 10 nm to about 60 nm. The method of claim 1 wherein the capacitor comprises an electrode made of titanium and tungsten nitride and a tantalum pentoxide dielectric. A first electrode comprising a first barrier layer and a titanium layer selected from the group consisting of tungsten nitride, tungsten nitride silicide and mixtures thereof, substantially free of a titanium nitride layer, A capacitor dielectric disposed on the first electrode and to be reduced by titanium; And a second electrode disposed over said capacitor dielectric, said second electrode comprising an electrically conductive layer. 9. The method of claim 8, wherein the second electrode further comprises a second barrier layer selected from the group consisting of tungsten nitride, tungsten nitride silicide, and mixtures thereof, And the second barrier layer is positioned between the capacitor dielectric and the electrically conductive layer. 9. The capacitor of claim 8 wherein said capacitor dielectric is tantalum pentoxide. 9. The capacitor of claim 8 wherein said barrier layer is in contact with said capacitor dielectric and is located between said first electrode and said capacitor. 9. The capacitor of claim 8 wherein said first barrier layer has a thickness of less than about 30 nm. The capacitor of claim 8, wherein the first electrode has a thickness in a range from about 10 nm to about 60 nm. 9. The capacitor of claim 8 wherein said capacitor comprises a first electrode made of tantalum and tungsten nitride and a tantalum pentoxide dielectric. 10. An integrated circuit memory having a transistor in contact with an interconnect formed in a dielectric layer located above the transistor, wherein: A capacitor located over the dielectric layer and in contact with the interconnect, The capacitor comprises a first barrier layer and a titanium layer selected from the group consisting of tungsten nitride and tungsten nitride silicide, the first electrode being substantially free of the titanium nitride layer and positioned over the interconnects; A capacitor dielectric positioned over the first electrode and to be reduced by titanium; An integrated circuit memory located above the capacitor dielectric and comprising a second electrode. 16. The integrated circuit memory of claim 15 wherein the capacitor dielectric is tantalum pentoxide. The integrated circuit memory of claim 15, wherein the first barrier layer has a thickness of less than about 60 nm. The integrated circuit memory of claim 15, wherein the first electrode has a thickness in a range from about 10 nm to about 60 nm. 16. The integrated circuit memory of claim 15 wherein the first electrode barrier layer is in contact with the capacitor dielectric and is located between the first electrode and the capacitor dielectric. 16. The integrated circuit memory of claim 15, wherein the second electrode comprises a second barrier layer selected from the group consisting of tungsten nitride and tungsten nitride silicide, and substantially free of titanium nitride.