KR20000047699A - Semiconductor integrated circuit device and the method of producing thereof - Google Patents

Abstract

PURPOSE: A semiconductor integrated circuit apparatus and method for manufacturing the same are provided to increase a refresh characteristics of the semiconductor integrated circuit apparatus and a driving capability of the MIS transistor of a logic circuit. CONSTITUTION: A semiconductor integrated circuit apparatus includes a memory cell in which a MIS transistor and a capacity device are connected in series on a semiconductor substrate(1). An active region and a device separating region(4) are provided on the surface of the semiconductor substrate. The MIS transistor is formed to the active region and provides a semiconductor region(5a,8a,8b) for a gate electrode(5g,8g) and a source/drain. A conductive type of the semiconductor region for the source/drain is contrary to a conductive type for the gate electrode. The device separating region is formed by filling a separating groove(4a), which is formed on the surface of the semiconductor substrate, with an insulating film. A gate insulating film(5i) is formed on the semiconductor substrate. A polysilicon film is deposited on the gate insulating. A conductive type impurity contrary to the conductive type for the source/drain is introduced to a region for forming the gate electrode of the MIS transistor in the polysilicon film.

Description

Semiconductor integrated circuit device and its manufacturing method {SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND THE METHOD OF PRODUCING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly, to a semiconductor integrated circuit device having a logic mixed logic memory and a logic circuit installed on the same semiconductor substrate. It is about valid technology.

In recent years, development and manufacture of logic mixed memory in which a DRAM (Dynamic Random Access Memory) and a logic circuit are provided on the same semiconductor substrate have been advanced.

However, a DRAM memory cell is composed of one memory cell select MIS transistor and a capacitor connected in series with it. Since the capacitor is used as a device for storing information, the signal used for storing information is left as it is. The charge leaks over time and the memory is lost.

For this reason, in DRAM, a so-called refresh operation is required in which memory contents are periodically reproduced in order to continuously store information in memory cells, and in order to improve the refresh characteristics of the DRAM as well as to improve this refresh characteristic, various structural features are provided. And circuit research and technology development.

In addition, there is a problem of increasing the Vth (threshold voltage) of the memory cell selection MIS transistor in DRAM, and as a specific means, it is preferable to use p-type polycrystalline silicon as the conductivity type as the gate electrode of the n-channel MIS transistor. Japanese Patent Laid-Open No. 2-214155, Japanese Patent Laid-Open No. 4-58556 or Japanese Patent Laid-Open No. 9-36318 is disclosed.

A memory cell selection MIS transistor is a switching element interposed between a capacitor and a bit line to electrically connect or insulate both of them, and includes a pair of semiconductor regions for source and drain formed on a semiconductor substrate and a gate on the semiconductor substrate. It has a gate electrode formed through an insulating film.

The active region in which the memory cell selection MIS transistor is formed is defined by an element isolation region, and LOCOS (Local Oxidation of Silicon) is generally used for this element isolation region due to ease of manufacture and the like.

However, an impurity region for preventing inversion is required at the boundary between the LOCOS and the semiconductor substrate, and a high concentration impurity region is formed in the semiconductor substrate under the LOCOS in the same conductivity type as the semiconductor substrate.

For this reason, there is a problem that the electric field becomes large at the junction between the semiconductor region and the impurity region of the accumulation node of the memory cell selection MIS transistor, thereby degrading the refresh characteristics of the memory cell.

Further, in the logic mixed DRAM, process integration between the DRAM and the logic circuit is achieved. For example, the DRAM is formed simultaneously with the gate insulating film of the memory cell selection MIS transistor of the DRAM and the MIS transistor of the logic circuit. However, in the memory cell selection MIS transistor, since a high voltage is required at the step-up of the word line potential, the film thickness of the gate insulating film cannot be made very thin from the viewpoint of ensuring the newness. For this reason, the gate insulating film of the MIS transistor of the logic circuit must also be thickened in accordance with the gate insulating film of the memory cell selection MIS transistor, and in the MIS transistor of the logic circuit, the gate insulating film becomes thicker than necessary, and performance improvement such as driving current is hindered. There is a problem.

An object of the present invention is to provide a technique capable of improving refresh characteristics in a semiconductor integrated circuit device having a logic mixed memory.

Another object of the present invention is to provide a technique capable of improving the driving capability of a MIS transistor of a logic circuit in a semiconductor integrated circuit device having a logic mixed memory.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Among the inventions disclosed in the present application, an outline of representative ones will be briefly described as follows.

A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a memory cell in which a MIS transistor and a capacitor are connected in series on a semiconductor substrate, wherein the MIS transistor has a gate electrode provided with polycrystalline silicon in contact with a gate insulating film. The conductivity type of the polycrystalline silicon is opposite to that of the semiconductor region for the source and drain of the MIS transistor, and an element isolation region defining an active region of the semiconductor substrate on which the MIS transistor is formed is separated from the semiconductor substrate. The insulating film is embedded in the groove.

In the semiconductor integrated circuit device of the present invention, a logic circuit is formed around the memory cell, and the conductive region of the gate electrode of the MIS transistor constituting the logic circuit is a semiconductor region for source and drain in the MIS transistor. The conductivity type is the same as the conductivity type.

In the semiconductor integrated circuit device of the present invention, the thickness of the gate insulating film of the MIS transistor of the memory cell is relatively thicker than the thickness of the gate insulating film of the MIS transistor constituting the logic circuit.

In addition, the method for manufacturing a semiconductor integrated circuit device of the present invention is a method for manufacturing a semiconductor integrated circuit device which forms a memory cell in which a MIS transistor and a capacitor are connected in series on a semiconductor substrate.

(a) forming a separation groove on the main surface of the semiconductor substrate, and then forming an isolation region with an insulating film in the separation groove;

(b) forming a gate insulating film on the semiconductor substrate;

(c) depositing a polycrystalline silicon film on the gate insulating film;

(d) a step of introducing an impurity of a conductivity type opposite to that of a semiconductor region of a source / drain of the MIS transistor in a gate electrode formation region of the MIS transistor in the polycrystalline silicon film; In the step of introducing an impurity into the gate electrode formation region in the above, the impurity is simultaneously introduced into the gate electrode formation region of another MIS transistor other than the memory cell selection MIS transistor in the polycrystalline silicon film.

1 is a sectional view of principal parts of a semiconductor integrated circuit device according to one embodiment of the present invention;

2 to 44 are cross-sectional views of principal parts in the manufacturing process of the semiconductor integrated circuit device of FIG. 1;

45 is an impurity concentration distribution in a depth direction at an interface between a semiconductor region and an element isolation region of an accumulation node of an n-channel memory cell selection MIS transistor, and (a) shows an n ⁺ gate in a memory cell selection MIS transistor. Is the impurity concentration distribution of and (b) is the impurity concentration distribution in the memory cell selection MIS transistor of the p ⁺ gate.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on drawing. (In addition, in the whole drawing for demonstrating embodiment, the same code | symbol is attached | subjected and description of the repetition is abbreviate | omitted.).

1 is a cross-sectional view of a main portion of a semiconductor integrated circuit device according to an embodiment of the present invention, FIGS. 2 to 44 are main cross-sectional views of a manufacturing process of the semiconductor integrated circuit device of FIG. the impurity concentration in the depth direction distribution on the interface between the regions, (a) are n ⁺ impurity concentration distribution in the MOS · FET of the n-channel gate, (b) is a p ⁺ gate of the n MOS · FET of the channel Impurity concentration distribution at

First, the cross-sectional structure of the DRAM of the first embodiment will be described with reference to FIG. The semiconductor substrate 1 is made of, for example, a p ⁻ type silicon single crystal, and a deep n well 2nw is formed in the memory region. Phosphorus, for example, of n-type impurities, is introduced into the deep n well 2nw.

The p well 3pwm is formed in the upper layer of this deep n well 2nw. The p well 3pwm is surrounded by the n well 2nw deep around it and is electrically separated from the logic circuit region or the like. For example, boron of p-type impurities is introduced into the p well 3pwm. The concentration of the p-type impurity is, for example, about 10 ¹⁷ to 10 ¹⁸ / cm 3.

In the semiconductor substrate 1 in the logic circuit region or the like, a p well 3pwp is formed in a depth region approximately equal to the p well 3pwm of the memory region. For example, boron of p-type impurities is introduced into the p well 3pwp. The concentration of the p-type impurity is, for example, about 10 ¹⁷ to 10 ¹⁸ / cm 3.

In the semiconductor substrate 1 in the logic circuit region or the like, n wells 3 nwp are formed in a depth region approximately equal to the p wells 3 pwm of the memory region. For example, phosphorus or arsenic (As) of n-type impurities is introduced into the n well 3nwp. The concentration of the n-type impurity is, for example, about 10 ¹⁷ to 10 ¹⁸ / cm 3.

In the upper portion of the semiconductor substrate 1, a shallow groove buried element isolation region 4 is formed. That is, the device isolation region 4 is formed by embedding insulating films 4b ₁ and 4b ₂ for separation in separation grooves 4a having a depth of 0.3 to 0.4 µm, which are dug in the thickness direction of the semiconductor substrate 1. .

The insulating films 4b ₁ and 4b ₂ for separation are made of, for example, silicon dioxide (SiO ₂ ) or the like. In addition, the upper surface of the device isolation region 4 is formed flat so that the height thereof substantially matches the height of the main surface of the semiconductor substrate 1.

The shallow groove buried element isolation region 4 makes it possible to obtain the following effects, for example.

In other words, the semiconductor substrate under the element isolation region 4 is difficult because the conductive type of the semiconductor substrate 1 under the insulating film 4b ₁ , 4b ₂ for separation and having a groove having a depth of 0.3 to 0.4 μm is difficult to reverse. It is not necessary to form an impurity region for preventing inversion in (1). For this reason, the impurity concentration of the pn junction portion at the interface between the impurity region of the storage node and the isolation region 4 of the memory cell selection MISFET described later becomes low, and the junction electric field can be made small. .

DRAM memory cells are formed on the p wells 2pwm of the semiconductor substrate 1 in the memory region (left side of FIG. 1). This memory cell is composed of one memory cell selection MISFET (Q) and one capacitor (information storage capacitor) C.

The memory cell selection MIS / FET Q has a pair of semiconductor regions 5a and 5b formed on top of the p well 3pwm and a gate insulating film 5i formed on the semiconductor substrate 1. And a gate electrode 5g formed thereon. The threshold voltage of the memory cell selection MIS FET Q is around 1V, for example.

The semiconductor regions 5a and 5b are regions for forming the source and drain of the memory cell selection MISFET Q, and As, for example, n-type impurities are introduced into the region. Immediately below the gate electrode 5g between the semiconductor regions 5a and 5b, a channel region of the memory cell selection MIS / FET Q is formed.

The gate electrode 5g is formed by a part of the word line WL, and for example, a low resistance polysilicon film, a titanium nitride (TiN) film and a tungsten film are deposited in order from the lower layer to form a polymetal structure. It consists. As a low resistance gate electrode material, the polymetal has a sheet resistance of 2? /? Because of its low level, it can be used not only as a gate electrode material but also as a wiring material.

For example, boron of p-type impurity is introduced into the low resistance polysilicon film in the gate electrode 5g. Thereby, for example, the following effects can be obtained.

In other words, it is possible to increase the threshold voltage of the memory cell selection MIS / FET Q without increasing the impurity concentration of the semiconductor substrate 1 (that is, the impurity concentration of the p well (3 pwm): hereinafter referred to as the substrate concentration). Therefore, it is not necessary to introduce impurities for adjusting the threshold voltage in the channel region immediately below the gate electrode 5g, and the substrate concentration can be reduced.

This is because the work function of p ⁺ polysilicon is about 5.15V and about 1V about 4.15V of n ⁺ type polysilicon, so the n-channel using the gate electrode of p ⁺ polysilicon is used even if the substrate concentration is the same. This is because the threshold voltage of the type memory cell selection MISFET Q can be about 1V higher than that of the n-channel type memory cell selection MISFET using an n ⁺ type polysilicon gate electrode. .

By reducing the substrate concentration, the electric field in the vicinity of the junction of the semiconductor region 5a to which the capacitor C is connected can be relaxed, so that the leakage current between the accumulation node and the semiconductor substrate 1 can be reduced. have. Further, since the subthreshold current of the memory cell selection MISFET Q can be reduced by reducing the substrate concentration, the leakage current of the MISFET can be reduced even at the same threshold. By reducing these leak currents, it is possible to improve the refresh characteristics of the memory cells.

The gate insulating film 5i is made of SiO ₂ , for example, and the thickness thereof is set to, for example, about 6 to 12 nm, preferably about 8 nm.

The gate electrode 5g of the memory cell selection MISFET Q, that is, the upper surface of the word line WL is formed of, for example, silicon nitride through an insulating film made of, for example, SiO ₂ . ) An insulating film 6 is formed. The insulating film under the cap insulating film 6 is for relieving the stress from the cap insulating film 6.

Further, for example, nitride is formed on the main surface of the semiconductor substrate 1 between the surface of the cap insulating film 6, the side of the gate electrode 5g (word line WL), and the word line WL adjacent to each other. An insulating film 7 made of silicon is formed.

On the other hand, an n-channel MISFET Qn is formed on the p well 3pwp in the logic circuit region (right side in Fig. 1). The n-channel MISFET Qn has a pair of semiconductor regions 8a and 8b formed on the p well 3pwp and separated from each other, and a gate insulating film 8i formed on the semiconductor substrate 1 and formed thereon. It has the gate electrode 8g. In addition, the threshold voltage in MISFET Qn is about 0.1V, for example.

The semiconductor regions 8a and 8b are regions for forming the source / drain of the n-channel MISFET Qn. The semiconductor regions 8a and 8b are located directly below the gate electrode 8g between the semiconductor regions 8a and 8b. A channel region of the channel type MIS FET Qn is formed.

The semiconductor regions 8a and 8b have an LDD (Lightly Doped Drain) structure. That is, the semiconductor regions 8a and 8b have low concentration regions 8a ₁ and 8b ₁ and high concentration regions 8a ₂ and 8b ₂ , respectively. The low concentration regions 8a ₁ and 8b ₁ are formed on the channel region side, and the high concentration regions 8a ₂ and 8b ₂ are disposed outside thereof.

In this low concentration region 8a ₁ , 8b ₁ , As, for example, n-type impurity is introduced. In addition, although n type impurity As is introduced into the high concentration regions 8a ₂ and 8b ₂ , the impurity concentration is set higher than the impurity concentration in the low concentration regions 8a ₁ and 8b ₁ . In addition, a silicide layer 8c made of titanium silicide (TiSi _x ) or the like is formed in the upper layer portions of the semiconductor regions 8a and 8b.

The gate electrode 8g is formed by, for example, depositing a low resistance polysilicon film, a TiN film, and a tungsten film in order from the lower layer. For example, phosphorus or As of n-type impurity is introduced into the low-resistance polysilicon film in the gate electrode 8a. In addition, a metal film such as a tungsten film forming the gate electrode 8g has a function of reducing the sheet resistance of the gate electrode 8g to about 2 to 2.5? / ?. This makes it possible to improve the operation speed of the DRAM.

The gate insulating film 8i is made of, for example, SiO ₂ , and the thickness thereof is the same as that of the gate insulating film 5i of the memory cell selection MISFET Q, for example, about 6 to 12 nm, preferably Is set to about 8 nm. Or the thickness is set to about 4 nm, for example, may be set thinner than the gate insulating film 5i of the memory cell selection MISFET (Q), and the operation speed of an n-channel type MISFET (Qn) may be set. It is possible to improve.

On the upper surface of the gate electrode 8g, a cap insulating film 6 made of, for example, silicon nitride is formed through an insulating film made of SiO ₂ or the like. The insulating film under the cap insulating film 6 is for relieving the stress from the cap insulating film 6.

In addition, sidewalls 9 made of, for example, silicon nitride are formed on the side surfaces of the cap insulating film 6 and the gate electrode 8g. This sidewall 9 is mainly used as a mask for ion implantation for forming the low concentration regions 8a ₁ , 8b ₁ and the high concentration regions 8a ₂ , 8b ₂ described above on the semiconductor substrate 1. have.

Further, a p-channel MISFET Qp is formed on the n well 3nwp in the logic circuit area. The p-channel MISFET Qp includes a pair of semiconductor regions 10a and 10b formed on the n well 3nwp and spaced apart from each other, a gate insulating film 10i formed on the semiconductor substrate 1, and It has the gate electrode 10g formed on it. In addition, the threshold voltage in this MISFET Qp is about 0.1V, for example.

The semiconductor regions 10a and 10b are regions for forming the source / drain of the p-channel MISFET Qp, and are directly below the gate electrode 10g between the semiconductor regions 10a and 10b. A channel region of the channel type MIS FET Qp is formed.

The semiconductor regions 10a and 10b have an LDD (Lightly Doped Drain) structure. In other words, the semiconductor regions 10a and 10b have low concentration regions 10a ₁ and 10b ₁ and high concentration regions 10a ₂ and 10b ₂ , respectively. The low concentration regions 10a ₁ and 10b ₁ are formed on the channel region side, and the high concentration regions 10a ₂ and 10b ₂ are disposed outside thereof.

In the low concentration regions 10a ₁ and 10b ₁ , for example, boron of p-type impurity is introduced. Further, for example, boron of p-type impurities is introduced into the high concentration regions 10a ₂ and 10b ₂ , but the impurity concentration is set higher than the impurity concentration in the low concentration regions 10a ₁ and 10b ₁ . In addition, a silicide layer 10c made of titanium silicide (TiSi _x ) or the like is formed in the upper layer portions of the semiconductor regions 10a and 10b.

The gate electrode 10g is formed by, for example, depositing a low-resistance polysilicon film, a TiN film, and a tungsten film in order from the lower layer.

For example, boron of p-type impurity is introduced into the low resistance polysilicon film in the gate electrode 10g. As a result, the threshold voltage of the p-channel MISFET Qp corresponding to the low voltage operation can be lowered, and the characteristics and the operation reproducibility are improved. Further, a metal film such as a tungsten film forming the gate electrode 8g has a sheet resistance of 2 to 2.5? /? Of the gate electrode 8g. It has a function that can be reduced to a degree. This makes it possible to improve the operating speed of the DRAM.

The gate insulating film 10i is made of, for example, SiO ₂ , and the thickness thereof is, for example, about 6 to 12 nm, preferably the same as that of the gate insulating film 5i of the memory cell selection MISFET Q. Is set to about 8 nm. Alternatively, the thickness may be set to, for example, about 4 nm, and may be set thinner than the gate insulating film 5i of the memory cell selection MISFET Q, and the operation speed of the p-channel MISFET Qp may be set. It is possible to improve.

On the upper surface of the gate electrode 10g, a cap insulating film 6 made of, for example, silicon nitride is formed through an insulating film made of SiO ₂ or the like. The insulating film under the cap insulating film 6 is for relieving the stress from the cap insulating film 6.

Moreover, the sidewall 9 which consists of silicon nitride etc. is formed in the side surface of this cap insulating film 6 and the gate electrode 10g, for example. This sidewall 9 is mainly used as a mask for ion implantation for forming the low concentration regions 10a ₁ , 10b ₁ and the high concentration regions 10a ₂ , 10b ₂ on the semiconductor substrate 1. have.

In addition, these n-channel MISFETs (Qn) and p-channel MISFETs (Qp) allow DRAM sense amplifier circuits, column decoder circuits, column driver circuits, rod decoder circuits, load driver circuits, and I. Logic circuits such as / O selector circuits, data input buffer circuits, data output buffer circuits, and power supply circuits are formed.

Such semiconductor integrated circuit elements as the memory cell selection MISFET (Q), p-channel MISFET (Qp), and n-channel MISFET (Qn) are deposited on the semiconductor substrate 1. Covered with the interlayer insulating films 11a to 11c.

The interlayer insulating films 11a to 11c are made of SiO ₂ , for example. Among these, the interlayer insulating film 11a is deposited by SOG (Spin On Glass) method, for example. The interlayer insulating films 11b and 11c are deposited by, for example, plasma CVD. The top surface of the interlayer insulating film 11c is formed to be flat so that the heights of the interlayer insulating films 11c are substantially the same in the memory area and the logic circuit area.

Connection holes 12a and 12b exposed by the semiconductor regions 5a and 5b are drilled in the interlayer insulating films 11a to 11c and the insulating film 7 in the memory region. The widthwise dimension of the gate electrode 5g (word line WL) at the lower portion of the connection holes 12a and 12b is an insulating film on the side of the gate electrode 5g (word line WL) adjacent to each other. It is prescribed by part 7). That is, the connection holes 12a and 12b are self-aligned with the insulating film 7 on the side of the gate electrode 5g (word line WL).

As a result, in the exposure processing for transferring the patterns of the connection holes 12a and 12b, the plane position relative to the pattern of the connection holes 12a and 12b and the active area of the memory cell selection MISFET Qs. Is slightly shifted, a part of the gate electrode 5g (word line WL) is not exposed from the connection holes 12a and 12b.

Plugs 13a and 13b are embedded in these connection holes 12a and 12b, respectively. The plugs 13a and 13b are made of low-resistance polysilicon containing, for example, phosphorus of n-type impurities, and are electrically connected to the semiconductor regions 5a and 5b of the MISFET Q for memory cell selection, respectively. It is. In addition, a silicide film such as TiSi _{x is} formed on the upper surface of the plug 13b.

An interlayer insulating film 11d is deposited on the interlayer insulating film 11c. This interlayer insulating film 11d is made of SiO ₂ , for example, and is formed by, for example, plasma CVD. On this interlayer insulating film 11d, bit lines BL and first layer wirings 14 (14a to 14b) are formed.

The bit line BL is formed by, for example, a Ti film, a TiN film, and a tungsten film deposited sequentially from the lower layer, and is electrically connected to the plug 13b through a connection hole 15 drilled in the interlayer insulating film 11d. In addition, it is electrically connected to the semiconductor region 5b of the memory cell selection MIS / FET Q through the plug 13b. The insulating films 16 made of, for example, silicon nitride are coated on the surfaces (top and side surfaces) of the bit lines BL.

In addition, the bit line BL extends in the direction intersecting with the extending direction of the word line WL. Therefore, although the bit line BL is not normally shown in the cross section shown in FIG. 1, in order to show the wiring layer in which the bit line BL is disposed, the insulating film 16 coated on the surface of the bit line BL is further shown. The bit line BL is shown for reasons such as to be described later.

On the other hand, the first layer wiring 14 of the logic circuit region is formed in the same manner as the bit line BL, for example, by depositing a Ti film, a TiN film and a tungsten film in order from the lower layer, and the surfaces thereof (upper and side surfaces). An insulating film 16 made of, for example, silicon nitride is coated on the substrate.

The first layer wiring 14a is electrically connected to the semiconductor region 8a of the n-channel MISFET Qn through a connection hole 17 bored in the interlayer insulating films 11a to 11d. In the first layer wiring 14b, the semiconductor region 8b of the n-channel MISFET Qn and the p-channel MISFET are connected through a connection hole 17 in which the interlayer insulating films 11a to 11d are also drilled. It is electrically connected to the semiconductor region 10a of (Qp). The first layer wiring 14c is electrically connected to the semiconductor region 10b of the p-channel MISFET Qp through a connection hole 17 bored in the interlayer insulating films 11a to 11d.

On the upper surface of the interlayer insulating film 11d, the interlayer insulating films 11e to 11g are deposited in order from the lower layer, whereby the insulating film 16 is covered. The interlayer insulating films 11e to 11g are made of SiO ₂ , for example. Among them, the interlayer insulating film 11e is deposited by, for example, a spin on glass (SOG) method. The interlayer insulating films 11f and 11g are formed by, for example, plasma CVD. The top surface of the interlayer insulating film 11g is formed to be flat so that the heights of the interlayer insulating films 11g are substantially the same in the memory area and the logic circuit area.

In the interlayer insulating films 11d to 11g in the memory region, connection holes 18 exposed by the upper surface of the plug 13a are drilled. In this embodiment, since the insulating film 16 which consists of silicon nitride etc. is coat | covered on the surface of the bit line BL, the planar position of this connection hole 18 shifts in the width direction of the bit line BL, and bit Even if the wire BL overlaps the line BL, since the insulating film 16 made of silicon nitride or the like functions as an etching stopper, it is possible to prevent the bit line BL from being directly exposed from the connection hole 18. It is.

The plug 19 is embedded in the connection hole 18. The plug 19 is made of, for example, low-resistance polysilicon containing phosphorus of n-type impurities, electrically connected to the plug 13a, and through this, the semiconductor region of the MISFET Q for memory cell selection. It is electrically connected with 5a.

Interlayer insulating films 11h and 11i are deposited on the upper surface of the interlayer insulating film 11g. The interlayer insulating film 11h is made of silicon nitride, for example, and is mainly formed to cover the memory region. The interlayer insulating film 11i is made of SiO ₂ , for example. In the interlayer insulating films 11h and 11i, an opening 20 exposed by the top surface of the plug 19 is opened, and the capacitor C of the memory cell is formed in the opening 20.

The capacitor C is formed, for example, in the shape of a crown, and is composed of the storage electrode 21a, the capacitor insulating film 21b coated on the surface thereof, and the plate electrode 21c coated on the surface thereof.

The storage electrode 21a of the capacitor C is made of, for example, low-resistance polysilicon, and a plurality of minute unevennesses are formed on the surface thereof to increase the capacity without increasing the occupied area of the capacitor C. ) Is formed.

The lower part of the storage electrode 21a is electrically connected to the plug 19 through the opening 20, and is electrically connected to the semiconductor region 5a of the MISFET FET Q for memory cell selection. Incidentally, the storage electrode 21a1 disposed in the boundary region (nearly centered in FIG. 1) between the memory region and the logic circuit region of FIG. 1 is a dummy.

The capacitor insulating film 21b of the capacitor C is made of, for example, tantalum oxide (Ta ₂ O ₅ ) or the like. The plate electrode 21c of the capacitor C is made of TiN or the like, for example, and is formed to cover the plurality of storage electrodes 21a.

On the interlayer insulating film 11i, an interlayer insulating film 11j is deposited, thereby covering the plate electrode 21c. The interlayer insulating film 11j is made of SiO ₂ , for example, and second layer wirings 22 (22a and 22b) are formed on the upper surface thereof.

The second layer wiring 22 is formed by, for example, depositing a TiN film, an aluminum (Al) film, and a Ti film sequentially from the lower layer. The second layer wiring 22b in the logic circuit region is connected to the first layer wiring through the interlayer insulating films 11e to 11g, 11i and 11j and the conductor film 24 in the connection hole 23 bored in the insulating film 16. It is electrically connected with 14b). The conductor film 24 is formed by, for example, depositing a TiN film and a tungsten film sequentially from the lower layer.

On the interlayer insulating film 11j, the interlayer insulating films 11k, 11m, and 11n are deposited in order from the lower layer, whereby the second layer wirings 22 are covered. The interlayer insulating films 11k and 11n are made of SiO ₂ , for example, and are formed by, for example, plasma CVD. The interlayer insulating film 11m is made of SiO ₂ , for example, and is formed by SOG method or the like.

Third layer wirings 25 (25a to 25c) are formed on the interlayer insulating film 11n. The third layer wiring 25 is formed by, for example, depositing a TiN film, an Al film, and a Ti film sequentially from the lower layer.

Among them, the third layer wiring 25b in the logic circuit region is electrically connected to the plate electrode 21c through the conductor film 27 in the connection hole 26 bored in the interlayer insulating films 11j, 11k, 11m, and 11n. Is connected. The third layer wiring 25c in the logic circuit region is electrically connected to the second layer wiring 22b through the conductor film 29 in the connection hole 28 bored in the interlayer insulating films 11k, 11m, and 11n. It is. The conductor films 27 and 29 are formed by, for example, depositing a TiN film and a tungsten film sequentially from the lower layer.

The passivation film which consists of two layers of insulating films etc. which laminated | stacked the silicon oxide film and the silicon nitride film, for example is formed in the upper part of the 3rd layer wiring 25, The illustration is abbreviate | omitted.

Next, an example of the manufacturing method of the semiconductor integrated circuit device of Embodiment 1 is demonstrated with reference to FIGS.

First, as shown in Fig. 2, the semiconductor substrate 1 made of p-type Si single crystal is heat-treated to form a pad film 30 made of SiO ₂ or the like having a film thickness of about 10 to 30 nm on the surface thereof. Thereafter, an oxide resistant film 31 made of, for example, silicon nitride having a film thickness of about 100 to 200 nm is deposited on the pad film 30 by CVD (Chemical Vapor Deposition) method.

Subsequently, as shown in FIG. 3, the photoresist 32a formed on the oxidation resistant film 31 is used as an etching mask, and the oxidation resistant film 31, the pad film 30, and the semiconductor substrate 1 in the element isolation region. By sequentially etching, the isolation grooves 4a having a depth of about 350 to 400 nm are formed in the semiconductor substrate 1. At this time, the gas for etching the oxidation resistant film 31 is used, for example, CF ₄ + CHF ₃ + Ar or CF ₄ + Ar, the gas for etching the semiconductor substrate 1 is, for example, HBr + Cl ₂ + Use He + O ₂ .

Thereafter, in order to remove the damage layer caused the inner wall of the separation groove (4a) by means of etching as shown in Fig. 4, for example, an insulating film (4b made of a SiO ₂ subjected to the oxidation treatment to the inner surface of the separation grooves (4a) After forming ₁ ), an insulating film 4b ₂ made of, for example, SiO ₂ or the like is deposited on the semiconductor substrate 1 by the CVD method as shown in FIG. 5. At this time, the insulating film 4b _{2 is} formed by, for example, a plasma CVD method using TEOS (Tetraethoxysilane) gas.

Subsequently, an insulating film 33 made of silicon nitride, for example, is deposited on the insulating film 4b ₂ by the CVD method or the like, and then the photoresist 32b is used as an etching mask as shown in FIG. 7. Thus, a pattern of the insulating film 33a made of silicon nitride or the like is formed on the element isolation region having a relatively large width (area).

The insulating film 33a made of silicon nitride or the like remaining on the upper portion of the device isolation region has a relatively large area when the insulating film 4b ₂ is polished and planarized by the chemical mechanical polishing (CMP) method in the following process. separation grooves phenomenon (4a) an insulating film (4b ₂₎ as compared with the inner insulating layer (4b ₂₎ of the separation grooves (4a) of the device isolation region in a relatively small area deep polishing the interior of the (dishing: dishing) to prevent It is formed to.

Subsequently, the insulating film 4b ₂ is polished by the CMP method using the insulating films 31 and 33a as a stopper and left in the separation groove 4a, thereby leaving the element isolation region 4 as shown in FIG. Form. At this time, in this embodiment, the insulating film 4b ₂ for separation in the device isolation region 4 is formed by providing a pattern of the insulating film 33a on the element isolation region 4 having a relatively large width (area). It can prevent the top surface from chipping. For this reason, the height of the upper surface of the insulating film 4b ₂ for separation in the element isolation region 4 can be made substantially equal to the height of the main surface of the semiconductor substrate 1.

Subsequently, the oxidation resistant film 31 and the insulating film 33a are removed by thermal phosphoric acid or the like, and the pad film 30 is removed, followed by pre-oxidation processing on the semiconductor substrate 1.

Subsequently, after forming a photoresist pattern for forming a deep n well on the semiconductor substrate 1 that the memory region is exposed, phosphorus of, for example, n-type impurities is formed in the memory region of the semiconductor substrate 1 using the mask as a mask. Ion implant.

Thereafter, after removing the photoresist pattern for deep n well formation, a photoresist pattern exposing the p well region is formed on the semiconductor substrate 1, and the p well formation region of the semiconductor substrate 1 is used as a mask. For example, boron etc. of p-type impurity are ion-implanted.

Subsequently, after removing the photoresist pattern for forming the p well, a photoresist pattern exposing the n well region is formed on the semiconductor substrate 1, and as a mask, in the n well formation region of the semiconductor substrate 1, For example, phosphorus etc. of n type impurity are ion-implanted.

Subsequently, after removing the photoresist pattern for forming the n well, the semiconductor substrate 1 is subjected to heat treatment, so that n wells 2nw deep and p wells 3pwm deep in the semiconductor substrate 1 are shown in FIG. , 3pwp) and n wells (3nwp).

The deep n well 2nw is formed to prevent noise from entering the p well 3pwm of the memory region through the semiconductor substrate 1 in the input / output circuit or the like and to prevent the accumulation of accumulated charge in the memory cell.

Thereafter, thermal oxidation treatment or weight oxidation treatment is performed on the semiconductor substrate 1, so that SiO of, for example, about 6 to 12 nm, preferably about 8 nm, is formed on the active surface of the semiconductor substrate 1. Gate insulating films 5i, 8i, and 10i made of _two are formed.

10, the polysilicon film 34 is deposited on the semiconductor substrate 1 by CVD or the like.

Subsequently, the process proceeds to the impurity introduction step for setting the conductivity type in the gate electrode of the MISFET formed on the semiconductor substrate 1.

That is, as shown in FIG. 11, after forming the photoresist 32c on the polysilicon film 34 which the n-channel type MISFET formation region in a logic circuit area exposes, it is made into a mask, for example, for example. Phosphorus or arsenic (As) of n-type impurities is ion implanted into the polysilicon film 34.

Subsequently, after removing the photoresist 32c, as shown in Fig. 12, the photoresist 32d exposed by the p-channel type MISFET formation region in the memory cell selection MISFET formation region and the logic circuit region is exposed. After forming, using this as a mask, for example, boron or BF ₂ of p-type impurity is ion-implanted into the polysilicon film 34.

The implantation energy is controlled during ion implantation of p-type impurities such as boron or BF ₂ to prevent boron or the like from reaching a very deep position of the polysilicon film 34.

This is because when boron or the like is introduced to the deep position of the lower layer portion of the polysilicon film 34, boron or the like passes through the gate insulating film 5i and diffuses into the semiconductor substrate 1 by a subsequent thermal process. It is to suppress it because it is considered easy.

Next, as shown in FIG. 13, the barrier metal film 35 which consists of TiN, tungsten nitride, etc., for example, the metal film 36 which consists of tungsten, etc., for example, is nitrided on the polysilicon film 34, for example. The insulating film 6 made of silicon is deposited in order from the lower layer.

Subsequently, as shown in FIG. 14, the etching process is performed using the photoresist 32e for forming the gate electrode formed on the insulating film 6 as an etching mask, so that the gate electrode 5g (that is, the word line WL). ), The gate electrodes 8g and 10g and the cap insulating film 6 are pattern-formed.

The gate electrode 5g forms part of the memory cell selection MISFET and functions as a word line WL in regions other than the active region. The width of the gate electrode 5g (word line WL), i.e., the gate length, is the minimum within the allowable range in which the short channel effect of the MISFET for selecting a memory cell can be suppressed and the threshold voltage can be secured to a predetermined value or more. It consists of a dimension (for example 0.24 micrometer). Moreover, the space | interval of two adjacent gate electrodes 5g (word line WL) is comprised by the minimum dimension (for example, 0.22 micrometer) determined by the resolution limit of photolithography. The gate electrode 8g and the gate electrode 10g constitute each part of the n-channel MISFET and the p-channel MISFET of the logic circuit.

Subsequently, after forming the photoresist exposed by the n-channel MISFET (including the memory cell selection MISFET) on the semiconductor substrate 1, the semiconductor substrate 1 is used as a mask, for example. For example, ion of As-type impurity is implanted.

Subsequently, after removing the photoresist for the n-channel MISFET, a photoresist exposed by the p-channel MISFET is formed on the semiconductor substrate 1, and the semiconductor substrate 1 is used as a mask. ) Is implanted with, for example, boron of a p-type impurity. After ion implantation, annealing at about 800 캜 is performed. These impurity introduction steps are impurity introduction steps for forming the low concentration regions 5a ₁ , 5b ₁ , 8a ₁ , 8b ₁ , 10a ₁ , 10b ₁ shown in FIG. 15.

Next, as shown in FIG. 16, an insulating film 7 made of, for example, silicon nitride is deposited on the semiconductor substrate 1 by a CVD method or the like, and then a photo formed on the insulating film 7 as shown in FIG. The anisotropic dry etching process is performed using the resist 32f as an etching mask. As a result, the insulating film 7 is left in the memory region, and the sidewall 9 made of silicon nitride or the like is formed on the side surfaces of the gate electrodes 8g and 10g in the logic circuit region.

In order to minimize the amount of reduction of the insulating films 4b ₁ and 4b ₂ embedded in the gate insulating films 5i, 8i and 10i or the element isolation region 4, the etching rate of the silicon nitride film against the silicon oxide film is large. It is performed using an etching gas as much as possible. In addition, in order to minimize the amount of reduction of the insulating film 6 made of the silicon nitride film or the like on the gate electrodes 8g and 10g, the amount of over etching is minimized as necessary.

Subsequently, a photoresist is formed on the semiconductor substrate 1 to expose the formation region of the n-channel MISFET in the logic circuit region, and then the photoresist, the gate electrode 8g and the sidewall 9 are formed. As a mask, for example, n-type impurity As is introduced by an ion implantation method or the like.

Subsequently, a photoresist is formed on the semiconductor substrate 1 to expose the formation region of the p-channel MISFET in the logic circuit region, and then the photoresist, the gate electrode 10g, and the site wall 9 are masked. For example, boron of p-type impurities is introduced by ion implantation or the like.

Thereafter, the semiconductor substrate 1 is subjected to a heat treatment, for example, in a nitrogen gas atmosphere, thereby providing the high concentration regions 8a ₂ , 8b ₂ , 10a ₂ , 10b _{2 in} the logic circuit region of the semiconductor substrate 1. Form. As a result, as shown in FIG. 18, n-channel MISFETs Qn and p-channel MISFETs Qp for logic circuits are formed.

Then, an interlayer insulating film (11a) made of SiO _2, such as, for example, on a semiconductor substrate 1 as shown in Fig. 19 or the like is deposited by SOG method.

Subsequently, an insulating film made of SiO ₂ or the like is deposited on the interlayer insulating film 11a by, for example, plasma CVD method using TEOS (Tetraethoxysilane) gas, and then the upper part is etched back by CMP method or the like. Thus, as shown in FIG. 20, the interlayer insulating film 11b is formed on the interlayer insulating film 11a.

After that, an interlayer insulating film 11c made of SiO ₂ or the like is formed on the interlayer insulating film 11b by, for example, a plasma CVD method using TEOS gas. The interlayer insulating film 11c has a function of covering damage or the like formed on the top of the interlayer insulating film 11b by the CMP method, and its upper surface is formed flat so that the height thereof is substantially the same in the memory area and the logic circuit area. .

Next, as shown in FIG. 21, the photoresist 32g which the plug connection hole exposes is formed on the interlayer insulation film 11c. At this time, in the first embodiment, since the upper surface of the interlayer insulating film 11c is flattened, sufficient photolithography margin can be ensured and good pattern transfer can be performed.

Thereafter, the photoresist 32g is used as an etching mask to perform an etching process for drilling a connection hole for a plug. In this embodiment, the etching process is performed as follows, for example.

First of all, carries out, the insulating film (7) or cap, but the insulating film 6, such as a SiO ₂ film is removed so that the etching is stopped at the exposed point, the etching process is a difficult condition to remove the silicon nitride film as shown in Fig. As the etching gas at this time, for example, a mixed gas such as C ₄ F ₈ / argon (Ar) is used.

Subsequently, the etching conditions are changed to conditions in which the silicon nitride film is removed but the SiO ₂ film is difficult to remove, so that the connection holes 12a and 12b for plugs exposed by a part of the semiconductor substrate 1 are exposed as shown in FIG. do. Thereby, the connection holes 12a and 12b which have a fine diameter below the resolution limit of photolithography can be formed. As the etching gas at this time, a mixed gas such as CHF ₃ / Ar / CF ₄ is used.

The reason for performing such an etching process is an element isolation region exposed from the plug connection holes 12a and 12b by an etching process for forming the plug connection holes 12a and 12b. This is because the insulating films 4b ₁ and 4b ₂ for separation (4) are etched away, resulting in a defect.

Thereafter, after removing the photoresist 32g, phosphorus of, for example, n-type impurity is implanted into the semiconductor substrate 1 exposed from the connection holes 12a and 12b. This is an impurity introduction process for electric field relaxation.

Subsequently, a low-resistance polysilicon containing, for example, an n-type impurity is deposited on the semiconductor substrate 1 by CVD, or the like, and then etched back to the low-resistance polysilicon, as shown in FIG. 23. Plugs 13a and 13b are formed in the connection holes 12a and 12b for the dragon.

As shown in FIG. 24, the upper surfaces of the plugs 13a and 13b are covered by depositing an interlayer insulating film 11d made of, for example, SiO ₂ or the like on the semiconductor substrate 1 by the CVD method or the like.

In addition, Figure 24 numeral 5a _2, 5b ₂ is a high-concentration region containing introduced by the impurity introducing step for the above-mentioned electric-field stress is, the high concentration region (5a _2, 5b ₂₎ and the low-concentration region (5a of the _first, 5b ₁ ), the semiconductor regions 5a and 5b of the MISFET Q for memory cell selection are formed.

After that, as shown in FIG. 25, the photoresist 32h for forming connection holes for bit lines is formed on the interlayer insulating film 11d, and the plug 13b is attached to the interlayer insulating film 11d using this as an etching mask. Punctures the connection hole 15 exposed by the top surface.

Subsequently, after removing the photoresist 32h, as shown in FIG. 26, a photoresist 32i for forming connection holes for logic circuits is formed on the interlayer insulating film 11d, and it is used as an etching mask. The connection hole 17 exposed by the upper surface (semiconductor regions 8a, 8b, 10a, 10b) of the semiconductor substrate 1 is drilled in the interlayer insulating films 11a-11d.

Subsequently, after the photoresist 32i is removed, a Ti film and a TiN film are deposited on the semiconductor substrate 1 in order from the lower layer, for example, by a sputtering method or the like, as shown in FIG. 27. The film is laminated by a CVD method or the like to form the conductor film 37, and an insulating film 16a made of, for example, silicon nitride is deposited thereon by the CVD method.

Reference numerals 8c and 10c in FIG. 27 denote silicide layers such as TiSi _x formed by, for example, a heat treatment reaction between the Ti film under the conductive film 37 and the semiconductor substrate 1.

Then, as shown in FIG. 28, the photoresist 32j for wiring formation is formed on the insulating film 16a, and the insulating film 16a and the conductor film 37 are patterned by the etching method using it as an etching mask. By doing so, the bit line BL and the first layer wiring 14 are formed.

Subsequently, after removing the photoresist 32j, an insulating film made of, for example, silicon nitride is deposited on the semiconductor substrate 1, and then the insulating film is etched back, as shown in FIG. ) And sidewalls 16a are formed on the side surfaces of the first layer wirings 14.

Then, as shown in Fig. 30, for example, covering the bit line (BL) and a first layer wiring 14, by deposition by an interlayer insulating film (11e) made of SiO _2, such as SOG method or the like.

Subsequently, an insulating film made of SiO ₂ or the like is deposited on the interlayer insulating film 11e by, for example, plasma CVD method using TEOS gas, and then the upper part is etched back by CMP method or the like. As shown, an interlayer insulating film 11f is formed on the interlayer insulating film 11e.

Thereafter, an interlayer insulating film 11g made of SiO ₂ or the like is formed on the interlayer insulating film 11f by, for example, a plasma CVD method using TEOS gas. The interlayer insulating film 11g has a function of covering damages or the like formed by the CMP method on the top of the interlayer insulating film 11f, and the top surface of the interlayer insulating film 11g is made to have almost the same height in the memory area and the logic circuit area. It is formed flat.

Next, as shown in FIG. 32, the photoresist 32k which exposes the connection hole for plugs is formed on the interlayer insulation film 11g. At this time, in this embodiment, since the upper surface of the interlayer insulating film 11g is flattened, sufficient photolithography margin can be ensured and good pattern transfer can be performed.

Thereafter, the photoresist 32k is used as an etching mask, and the photoresist 32k is removed after the connection holes 18 through which the upper surface of the plug 13a is exposed are exposed to the interlayer insulating films 11d to 11g. .

In this time, the present embodiment is performed under the condition that at the time of this etching process the etching rate of silicon nitride film on the SiO ₂ film significantly. As a result, since the insulating film 16 made of silicon nitride is formed on the surface of the bit line BL, a relative position shift occurs between the connection hole 18 and the plug 13a, and thus the connection hole 18 ) Pattern is superimposed on the bit line BL, the insulating film 16 becomes an etching stopper, so that it is possible to prevent the bit line BL from being exposed in the connection hole 18.

Subsequently, a conductor film made of, for example, low-resistance polysilicon is deposited on the semiconductor substrate 1 by CVD, or the like, and then etched back so that the conductor film remains only in the connection hole 18, as shown in FIG. Similarly, the plug 19 is formed in the connection hole 18.

34, an insulating film 11h made of silicon nitride, for example, is deposited on the semiconductor substrate 1 by CVD or the like, and then a photoresist 32m is formed to cover the memory region thereon. The insulating film 11h is patterned by the etching method using it as an etching mask.

After removing the photoresist 32m, an interlayer insulating film 11i made of SiO ₂ or the like is formed on the semiconductor substrate 1 by, for example, plasma CVD using TEOS gas or the like, as shown in FIG. .

Subsequently, after forming the photoresist 32n for capacitor formation on the interlayer insulating film 11i, the interlayer insulating films 11i and 11h exposed by the photoresist 32n are removed by using it as an etching mask. The opening 20 which the upper surface of the plug 19 exposes is formed.

Next, as shown in FIG. 36, the conductor film 38 which consists of low resistance polysilicon, for example is deposited on the semiconductor substrate 1 by CVD method. As a result, the conductor film 38 is deposited on the upper surface of the interlayer insulating film 11i and the inner surface of the opening 20.

Then, as shown in Figure 37, it is deposited by, for example, on a semiconductor substrate 1 made of a SiO ₂ insulating film, etc. (39) SOG method or the like. Here, the insulating film 39 is deposited to such an extent that the upper surface of the insulating film 39 is substantially flat.

Subsequently, the insulating film 39 is etched away to the extent that the conductive film 38 on the interlayer insulating film 11i is exposed, and then the exposed conductive film 38 is etched back to open the opening (as shown in FIG. 38). An accumulation electrode 21a and a dummy accumulation electrode 21a ₁ made of low resistance polysilicon and the like are formed in 20).

39, a photoresist 32p covering the dummy storage electrode 21a ₁ and the logic circuit region is formed on the semiconductor substrate ₁ , and then the interlayer insulating film 11i is used as an etching mask. Is removed by a wet etch method or the like to expose the surface of the accumulation station 21a. At this time, the interlayer insulating film 11h functions as an etching stopper in the wet etching process and also as a member for fixing the storage electrode 21a.

The end portion of the photoresist 32p is disposed on the boundary between the memory region and the logic circuit region, that is, on the dummy storage electrode 21a ₁ . In this case, even when misalignment occurs at the end of the photoresist 32p, an insulating film remains inside the storage electrode 21a formed at the outermost side of the memory area, or the interlayer insulating film 11i in the logic circuit area is etched. There is nothing to do.

Thereafter, after removing the photoresist 32p, as shown in FIG. 40, the surface of the storage electrode 21a is nitrided, and the capacitor insulating film 21b made of, for example, tantalum oxide (Ta ₂ O ₅ ). )).

Subsequently, as shown in FIG. 41, a conductor film made of TiN is deposited on the semiconductor substrate 1, and then the patterned photoresist 32q for forming a plate electrode formed on the upper surface of the conductor film is formed as an etching mask. Thus, the plate electrode 21c is formed. This forms the capacitor C for storing information.

Subsequently, after the photoresist 32q is removed, an interlayer insulating film 11j made of SiO ₂ or the like is formed on the semiconductor substrate 1 by, for example, a plasma CVD method using TEOS gas or the like, as shown in FIG. . This covers the plate electrode 21c.

Thereafter, after forming the photoresist 32r for forming the connection hole of the logic circuit on the interlayer insulating film 11j, the connection hole 23 exposed by a part of the first layer wiring 14b is used as an etching mask. Perforate).

Subsequently, after removing the photoresist 32r, TiN and tungsten are deposited on the semiconductor substrate 1 in order from the lower layer, for example, by a sputtering method or the like, and then etched back, thereby connecting as shown in FIG. 43. The conductor film 24 is embedded in the hole 23.

Subsequently, for example, TiN, Al, and Ti are deposited on the semiconductor substrate 1 in order from the lower layer by sputtering or the like, and then patterned by photolithography or dry etching, as shown in FIG. 44. Similarly, the second layer wirings 22 are formed on the interlayer insulating film 11j.

Thereafter, a third layer wiring 25 is formed on the semiconductor substrate 1 through the same wiring forming process as that of forming the second layer wiring 22 to form a DRAM.

Next, FIG. 45 shows the impurity distribution in the depth direction at the interface between the semiconductor region and the element isolation region of the storage node of the MISFET for memory cell selection. (a) is the impurity concentration distribution in the conventional n ⁺ gate memory cell selection MIS FET, and (b) is the impurity concentration distribution in the p ⁺ gate memory cell selection MISFET of this embodiment.

In the conventional n ⁺ gate memory cell selection MIS / FET, impurity concentration needs to be introduced into the channel region, so that the impurity concentration at the junction between the semiconductor region of the storage node and the semiconductor substrate is about 10 ¹⁸ cm ⁻³ . In contrast, in the memory cell selection MIS / FET of the p ⁺ gate of the present embodiment, no impurity is introduced into the channel region, so that the impurity concentration at the junction is low, about 5x10 ¹⁶ cm ^-3 , It is possible to reduce the electric field strength at.

Thus, according to this embodiment, it becomes possible to acquire the following effects.

(1) Impurity concentration (i.e., p) of the semiconductor substrate 1 by setting the conductivity type of the low resistance polysilicon constituting the gate electrode 5g of the memory cell selection MISFET Q to be p ^+. It is possible to increase the threshold voltage of the memory cell selection MISFET (Q) without raising the impurity concentration of the well 3 pwm (substrate concentration).

(2) Since the p-type impurity region for the inversion prevention does not need to be formed in the semiconductor substrate 1 under the element isolation region 4, the capacitor C of the memory cell selection MISFET Q is connected. The junction electric field in the vicinity of the interface between the semiconductor region 5a and the device isolation region 4 can be relaxed.

(3) Since the substrate concentration can be reduced by the above (1), the electric field in the vicinity of the junction of the semiconductor region 5a to which the capacitor C is connected can be relaxed. For this reason, it is possible to reduce the leakage current between the accumulation node and the semiconductor substrate 1.

(4) Since the substrate concentration can be reduced by the above (1), the sub-threshold current of the memory cell selection MIS / FET (Q) can be reduced. For this reason, it is possible to reduce the leakage current of the MISFET even at the same threshold.

(5) By (2), (3) and (4), it becomes possible to improve the refresh characteristic of a memory cell.

(6) The thicknesses of the gate insulating films 8i and 10i of the n-channel type MISFET Qn and p-channel type MISFET Qp for logic circuits are determined by the thickness of the MISFET Q for memory cell selection. By making it thinner than the thickness of the gate insulating film 5i, it becomes possible to improve the drive capability of the n-channel type MISFET (Qn) and p-channel type MISFET (Qp) for a logic circuit.

(7) With (1) above, it becomes possible to eliminate the step of ion implanting impurities into the channel region of the p well 3pwm.

(8) In the polysilicon film 34 for forming the gate electrode, when the p-type impurity is introduced into the gate electrode formation region of the memory cell selection MISFET Q, the same p-type impurity is used as the photoresist. By using the mask as a mask, it is also introduced into the gate electrode formation region of the p-channel MISFET Qp for the logic circuit, so that the process of forming the photoresist pattern can be reduced compared with the case where the impurity introduction process is performed separately. Can be.

(9) Since (7) and (8) can simplify the manufacturing process of the DRAM, the development and manufacturing time of the semiconductor integrated circuit device can be shortened, and the semiconductor integrated circuit having the DRAM It is possible to promote the cost reduction of the apparatus.

As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it is needless to say that this invention is not limited to the said embodiment and can be variously changed in the range which does not deviate from the summary.

For example, in the above embodiment, a case has been described in which the gate electrodes of the memory cell selection MISFET and the MISFET on the semiconductor substrate are formed by laminating a metal film on a polysilicon film. It is also possible, for example, to have a structure in which a silicide film such as tungsten silicide is laminated on a single film of polysilicon or a polysilicon film.

In the above embodiment, the case where the information storage capacitor is provided on the upper layer of the bit line has been described. However, the present invention is not limited to this. The information storage capacitor may be provided below the bit line.

In addition, in the said embodiment, although the case where the information storage capacitor | condenser was made into the crown shape was demonstrated, it is not limited to this, For example, it may be a fin shape.

In the above description, the case in which the invention made mainly by the present inventors is applied to DRAM technology, which is the background of the field of use, is not limited thereto. For example, the p-channel load MIS transistor and the n-channel type are described. N-channel transmission and flip-flop circuit consisting of an SRAM technology or a load resistance element and an n-channel driving MIS transistor having a flip-flop circuit comprising a driving MIS transistor and a memory cell consisting of an n-channel transmission MIS transistor. The present invention can also be applied to SRAM technology having a memory cell made of a MIS transistor for use.

Among the inventions disclosed by the present application, the effects obtained by the representative ones are briefly described as follows.

(1) According to the semiconductor integrated circuit device of the present invention, the conductive type of the gate polysilicon electrode (polycrystalline silicon in contact with the gate insulating film) of the MIS transistor of the memory cell constituting the memory circuit is the source and drain of the MIS transistor of the memory cell. By setting the conductivity type opposite to the conductivity type of the semiconductor region cited above, it is possible to increase the threshold voltage of the MIS transistor of the memory cell without increasing the impurity concentration of the semiconductor substrate.

(2) According to the semiconductor integrated circuit device of the present invention, an element isolation region defining an active region of a semiconductor substrate on which a MIS transistor of a memory cell constituting a memory circuit is formed is formed by embedding a separator in a separation groove formed in the semiconductor substrate. Since the semiconductor substrate under the element isolation region does not have to be formed of an impurity region of the same conductivity type as the semiconductor substrate for inversion prevention, the junction electric field near the interface between the semiconductor region of the storage node of the memory cell and the element isolation region. Can alleviate

(3) According to (1), the impurity concentration of the semiconductor substrate in the memory circuit region can be reduced, so that the electric field near the junction of the semiconductor region of the storage node in the MIS transistor of the memory cell can be relaxed. As a result, it is possible to reduce the leakage current between the accumulation node and the semiconductor substrate.

(4) According to (1), the impurity concentration of the semiconductor substrate in the memory circuit region can be reduced, so that the sub-threshold current of the MIS transistor of the memory cell can be reduced. For this reason, it is possible to reduce the leakage current of the MIS transistor of the memory cell even at the same threshold.

(5) By (2), (3) and (4), it becomes possible to improve the refresh characteristic of a memory cell.

(6) By forming the thickness of the gate insulating film of the MIS transistor constituting the logic circuit relatively thinner than the thickness of the gate insulating film of the MIS transistor of the memory cell constituting the memory circuit, the driving capability of the MIS transistor for the logic circuit is improved. It is possible to improve.

(7) With (1) above, it becomes possible to eliminate the step of ion implanting impurities into the channel region of the MIS transistor of the memory cell constituting the memory circuit.

(8) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, a method for manufacturing a semiconductor integrated circuit device having a logic mixed memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate, wherein the semiconductor integrated circuit device is deposited on a semiconductor substrate. In the gate electrode formation region of the MIS transistor of the memory cell constituting the memory circuit in the polycrystalline silicon film for forming the gate electrode, the conductivity type is opposite to that of the semiconductor region of the source / drain semiconductor region of the MIS transistor of the memory cell. Forming a gate electrode of an MIS transistor other than the MIS transistor of the memory cell in the polycrystalline silicon film in the step of introducing an impurity into the gate electrode forming region in the polycrystalline silicon film. In the case where the impurity introduction step is performed separately by simultaneously introducing into the regions, On the other hand, the process of forming the photoresist pattern can be reduced.

(9) Since (7) and (8) can simplify the manufacturing process of the semiconductor integrated circuit device having the logic mixed memory, the development and manufacturing time of the semiconductor integrated circuit device can be shortened. In addition, it is possible to promote cost reduction of a semiconductor integrated circuit device having a logic mixed memory.

Claims (30)

In a semiconductor integrated circuit device having a memory cell in which a MIS transistor and a capacitor are connected in series on a semiconductor substrate, (a) a semiconductor substrate having an active region and a device isolation region on its surface; (b) a MIS transistor formed in the active region and provided with a gate electrode and a semiconductor region for source and drain, The conductivity type of the semiconductor region for the source and drain and the conductivity type of the gate electrode are opposite to each other, and the device isolation region is formed by embedding an insulating film in a separation groove formed on the surface of the semiconductor substrate. A semiconductor integrated circuit device. The method of claim 1, And the insulating film in the isolation groove is an oxide film formed by a chemical vapor deposition method. The method of claim 1, And the MIS transistor has a gate electrode provided with polycrystalline silicon in contact with the gate insulating film. The method of claim 1, A logic circuit is formed around the memory cell, and the conductivity type of the gate electrode of the MIS transistor constituting the logic circuit is the same conductivity type as that of the semiconductor region for the source / drain of the MIS transistor. Semiconductor integrated circuit device, characterized in that. The method of claim 1, A logic circuit is formed around the memory cell, and the thickness of the gate insulating film of the MIS transistor of the memory cell is relatively thicker than the thickness of the gate insulating film of the MIS transistor constituting the logic circuit. Device. The method of claim 1, The impurity ions for adjusting the threshold voltage are not introduced into the channel region of the MIS transistor. The method of claim 1, And said memory cell is a DRAM cell comprising a memory cell selection MIS transistor and an information storage capacitor connected in series therewith. The method of claim 1, And said memory cell is a flip-flop circuit comprising a p-channel load MIS transistor and an n-channel driving MIS transistor, and an n-channel transfer MIS transistor. The method of claim 1, And said memory cell is a flip-flop circuit comprising a load resistance element and an n-channel driving MIS transistor, and an SRAM cell comprising an n-channel transmission MIS transistor. The method of claim 7, wherein And the conductivity type of the semiconductor region for source and drain of the memory cell selection MIS transistor is n type, and the conductivity type of the gate electrode of the memory cell selection MIS transistor is p type. The method of claim 7, wherein A logic circuit is formed around the memory cell, and the conductivity type of the semiconductor region for the source and drain of the memory cell selection MIS transistor is n type, and the conductivity type of the gate electrode of the memory cell selection MIS transistor is p-type, the conductivity type of the gate electrode of the p-channel MIS transistor constituting the logic circuit is p-type, and the conductivity type of the gate electrode of the n-channel MIS transistor constituting the logic circuit is n-type. A semiconductor integrated circuit device. The method of claim 8, The conductive type of the gate electrode of the p-channel type load MIS transistor is n-type, and the conductive type of the gate electrode of the n-channel driving MIS transistor and the n-channel type transfer MIS transistor is p-type. A semiconductor integrated circuit device. The method of claim 9, And the conductivity type of the gate electrode of the n-channel driving MIS transistor and the n-channel transmission MIS transistor is p-type. In the manufacturing method of a semiconductor integrated circuit device forming a memory cell in which a MIS transistor and a capacitor connected in series on a semiconductor substrate, (a) forming a separation region on a main surface of the semiconductor substrate and then filling an insulating film in the separation groove to form a separation region; (b) forming a gate insulating film on the semiconductor substrate; (c) depositing a polycrystalline silicon film on the gate insulating film; (d) a step of introducing an impurity of a conductivity type opposite to that of a semiconductor region of a source / drain of the MIS transistor in a gate electrode formation region of the MIS transistor in the polycrystalline silicon film; A method for manufacturing a semiconductor integrated circuit device. The method of claim 14, In the step of introducing the impurity into the gate electrode forming region in the polycrystalline silicon film, the impurity is simultaneously introduced into the gate electrode forming region of another MIS transistor other than the MIS transistor of the memory cell in the polycrystalline silicon film. Method of manufacturing a semiconductor integrated circuit device. A method for manufacturing a semiconductor integrated circuit device, comprising forming a logic circuit around a memory cell in which a MIS transistor and a capacitor are connected in series on a semiconductor substrate, (a) forming a separation region by forming an isolation groove on a main surface of the semiconductor substrate and then embedding an insulating film in the separation groove; (b) forming a gate insulating film on the semiconductor substrate; (c) depositing polycrystalline silicon on the gate insulating film; (d) introducing p-type impurities into the gate electrode forming region of the n-channel MIS transistor of the memory cell and the gate electrode forming region of the p-channel MIS transistor constituting the logic circuit in the polycrystalline silicon film; The manufacturing method of the semiconductor integrated circuit device characterized by having a process. The method of claim 16, The thickness of the gate insulating film of the MIS transistor of the memory cell is formed relatively thicker than the thickness of the gate insulating film of the MIS transistor constituting the logic circuit. A memory cell including a first MISFET and a capacitor; and a second MISFET; (a) a semiconductor substrate having a first semiconductor region of a first conductivity type on its surface, and a second semiconductor region of a first conductivity type on another region of the first semiconductor region; (b) a third semiconductor region of a second conductivity type formed in the first semiconductor region and functioning as a source or a drain of the first MISFET; (c) a first conductor layer located between the third semiconductor regions on the semiconductor substrate and functioning as a gate of the first MISFET; (d) a fourth semiconductor region of a second conductivity type formed in the second semiconductor region and functioning as a source or a drain of the second MISFET; (e) A semiconductor integrated circuit device comprising a second conductor layer located on the semiconductor substrate between the fourth semiconductor regions and functioning as a gate of the second MISFET. The first conductor layer has a laminated structure of a first polysilicon layer of a first conductivity type and a first metal layer, and the second conductor layer is a second polysilicon layer and a second metal layer of a second conductivity type. A semiconductor integrated circuit device comprising a stacked structure of a semiconductor device. The method of claim 18, And the first and second metal films are formed of a tungsten layer. The method of claim 19, And a third metal film is interposed between the first polysilicon film and the first metal film and between the second polysilicon film and the second metal film. The method of claim 20, And the third metal film is a tungsten nitride film. The method of claim 18, And a metal silicide layer on the surface of the fourth semiconductor region. A memory cell including a first MISFET and a capacitor; and a second MISFET; (a) a semiconductor substrate having a first semiconductor region of a first conductivity type on its surface and a second semiconductor region of a first conductivity type on a region different from the first semiconductor region; (b) a third semiconductor region of a second conductivity type formed in the first semiconductor region and functioning as a source or a drain of the first MISFET; (c) a first conductor layer located between the third semiconductor regions, formed on the semiconductor substrate via a first gate insulating film, and functioning as a gate of the first MISFET; (d) a fourth semiconductor region of a second conductivity type formed in the second semiconductor region and functioning as a source or a drain of the second MISFET; (e) A semiconductor integrated circuit device comprising a second conductor layer located between said fourth semiconductor region and formed on said semiconductor substrate via a second gate insulating film, and functioning as a gate of said second MISFET. , The first conductor layer has a first polysilicon layer of a first conductivity type, the second conductor layer has a second polysilicon layer of a second conductivity type, And the film thickness of said first gate insulating film is thicker than the film thickness of said second gate insulating film. The method of claim 23, The first conductor layer has a laminated structure of a first polysilicon layer of a first conductivity type and a first metal layer, and the second conductor layer is a second polysilicon layer and a second metal layer of a second conductivity type. A semiconductor integrated circuit device comprising a stacked structure of a semiconductor device. The method of claim 24, And the first and second metal films are formed of a tungsten layer. The method of claim 25, And a third metal film is interposed between the first polysilicon film and the first metal film and between the second polysilicon film and the second metal film. The method of claim 26, And the third metal film is a tungsten nitride film. The method of claim 23, And a metal silicide layer on the surface of the fourth semiconductor region. A memory cell comprising a first MISFET and a capacitor; a second MISFET; and a third MISFET; (a) A semiconductor having a first semiconductor region of a first conductivity type, a second semiconductor region of a first conductivity type, and a third semiconductor region of a second conductivity type in a region different from the first semiconductor region on its surface; Substrate, (b) a fourth semiconductor region of a second conductivity type formed in the first semiconductor region and functioning as a source or a drain of the first MISFET; (c) a first conductor layer located between the fourth semiconductor regions on the semiconductor substrate and functioning as a gate of the first MISFET; (d) a fifth semiconductor region of a second conductivity type formed in the second semiconductor region and functioning as a source or a drain of the second MISFET; (e) a second conductor layer located between the fifth semiconductor regions on the semiconductor substrate and functioning as a gate of the second MISFET; (f) a sixth semiconductor region of a first conductivity type formed in the third semiconductor region and functioning as a source or a drain of the third MISFET; (g) A semiconductor integrated circuit device comprising a third conductor layer located on the semiconductor substrate between the sixth semiconductor regions and functioning as a gate of the third MISFET. The first conductor layer has a laminated structure of a first polysilicon layer of a first conductivity type and a first metal film, and the second conductor layer is a second polysilicon layer and a second metal film of a second conductivity type. And the third conductor layer has a laminated structure of a third polysilicon layer of a first conductivity type and a third metal film. A memory cell comprising a first MISFET and a capacitor; a second MISFET and a third MISFET; (a) A semiconductor having a first semiconductor region of a first conductivity type, a second semiconductor region of a first conductivity type, and a third semiconductor region of a second conductivity type in a region different from the first semiconductor region on its surface; Substrate, (b) a fourth semiconductor region of a second conductivity type formed in the first semiconductor region and functioning as a source or a drain of the first MISFET; (c) a first conductor layer located between the fourth semiconductor regions and formed on the semiconductor substrate via a first gate insulating film, and functioning as a gate of the first MISFET; (d) a fifth semiconductor region of a second conductivity type formed in the second semiconductor region and functioning as a source or a drain of the second MISFET; (e) a second conductor layer located between the fifth semiconductor regions and formed on the semiconductor substrate via a second gate insulating film to function as a gate of the second MISFET; (f) a sixth semiconductor region of a first conductivity type formed in the third semiconductor region and functioning as a source or a drain of the third MISFET; (g) A semiconductor integrated circuit device comprising a third conductor layer located between said sixth semiconductor region and formed on said semiconductor substrate via a third gate insulating film and functioning as a gate of said third MISFET. , The first conductor layer has a first polysilicon layer of a first conductivity type, the second conductor layer has a second polysilicon layer of a second conductivity type, and the third conductor layer is a first conductive type first 3 has a polysilicon layer, The film thickness of the first gate insulating film is thicker than the film thicknesses of the second gate insulating film and the third gate insulating film.