JPH02214155A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a threshold voltage without increasing an ion dose into a channel by a method wherein impurities whose conductivity type is different from that of impurities introduced into a source region and a drain region are introduced into a gate electrode of a MIS-type semiconductor element constituting a memory cell. CONSTITUTION:A diffusion layer 8 is formed in a semiconductor substrate 7 composed of p-type silicon or the like; the diffusion layer 8 is an impurity layer forming a source region and a drain region for a MOS and is constituted by introducing n-type impurities such as arsenic or the like into the semiconductor substrate 7; a gate electrode 10a for a MOS 4a of a high threshold voltage (Vth) and a gate electrodes 10b for MOS's 4b of a low Vth are formed on its surface. Then, p-type impurities such as boron or the like as impurities whose conductivity type is different from that of the n-type impurities introduced into the diffusion layer 8 are introduced into a polysilicon layer 11 of the gate electrode 10a. Thereby, a flat-band voltage is enhanced; the Vth can be enhanced without increasing an ion dose into a channel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor device technology, and for example, to high-speed access technology for semiconductor memory.

[Conventional technology]

For example, ROM (ROM) is a read-only semiconductor memory.
Read 0nly Memory)
There is a description in Japanese Patent Application Laid-Open No. 52-30388, and the memory cell is depletion type and enhancement type M.
A technique for miniaturizing the area occupied by a memory cell by using an OS transistor and using a p diffusion layer for forming source and drain regions as a data output line is described.

Incidentally, in recent years, in semiconductor memories, from the viewpoint of high-speed access, n-channel MOS transistors (hereinafter referred to as
nMO3) is used. Polysilicon is used for the gate electrode material of nMO3 or the blended electrode material of dynamic RAM from the viewpoint of self-alignment, etc., but conventionally, polysilicon is used for this polysilicon electrode from the viewpoint of capturing mobile ions, etc. An n+ type polysilicon electrode into which n type impurities were introduced was used.

On the other hand, mask ROM (hereinafter referred to as MROM) is a ROM in which data is written in advance during the manufacturing process using a mask pattern.
). As a data writing method for MROM, for example, the threshold voltage (V = h
) to write H” data and “L” data.
plant) method.

This method, as shown in FIGS. 15(a) and (b),
Using the photoresist 40 as a mask, boron ions (or boron fluoride ions), which are p-type impurities, are used only in the formation region X of the high Vthn MO 341 where "H" data is written.
etc., and enter this high V ih n M 0541 V
This is a method of writing H" data by setting th to a high value. In this case, VLp was set even higher by increasing the ion dose.

[Problem to be solved by the invention]

However, according to studies conducted by the present inventors, it has been found that the above-mentioned conventional technique in which the ion dose is increased in order to increase V Lh has the following problems.

That is, firstly, when the ion dose amount is increased, the junction capacitance of the bit line increases, the bit line capacitance increases, and high-speed access is inhibited.

Second, for example, a semiconductor device configured with MOS, when aged, has a voltage of about 1.6
In order to apply twice the voltage, the junction breakdown voltage of the bit line with respect to the silicon substrate needs to be 8V or more, but if the ion dose is increased to increase VLh, the junction breakdown voltage of the bit line, or the diffusion layer and channel The pn junction breakdown voltage with the stopper region was lowered.

In addition, there is a method of setting Vo higher even at the same dose by setting the substrate bias voltage.
In this case, the voltage applied to the junction also increases by the substrate bias voltage, resulting in a decrease in the junction breakdown voltage of the bit line or the pn junction breakdown voltage between the diffusion layer and the channel stopper region.

The present invention has been made with attention to the above-mentioned problems, and its purpose is to reduce the VV without increasing the amount of impurity ions introduced.
The purpose of the present invention is to provide a technology that allows th to be set high.

Another object of the present invention is to provide a technique that can increase the access speed of a semiconductor memory.

The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, first, a semiconductor device in which impurities of a conductivity type different from the impurities introduced into the source and drain regions of the MIS type semiconductor element are introduced into the gate electrode of an MIS type semiconductor element constituting at least a memory cell of a semiconductor memory. It is a structure.

Second, in a MOS transistor which uses the semiconductor memory as a mask ROM and stores data depending on the level of threshold voltage of an MIS type semiconductor element constituting the memory cell, the gate electrode is connected to the high threshold voltage of the memory cell. M of value voltage
This is a semiconductor device structure formed in an OS.

Third, memory cells are made up of capacitors and switching MOS
Dynamic RAM configured with transistors
A semiconductor device structure in which an impurity of a conductivity type different from the impurity introduced into the source and drain regions of the switching MOS transistor is introduced into at least one of the plate electrode of the capacitor or the gate electrode of the switching MOS transistor. That is.

[Effect]

According to the above-mentioned first to third means, the flat band band As the voltage increases, Vth can be increased without increasing the ion dose to the channel.

[Embodiment 1] FIG. 1 is a plan view showing a memory cell of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, and FIG. -■ line cross-sectional view, Figure 4 is Figure 1 I
5 is a circuit diagram showing the memory cell circuit system of this semiconductor device, FIG. 6 is an overall configuration diagram of this semiconductor device, and FIGS. 7(a) to (e) are peripheral circuits. 8(a)-('') are peripheral circuit regions and cross-sectional views of main parts of a semiconductor substrate showing the manufacturing process of a semiconductor device taken along the line If-n in FIG. A cross-sectional view of a main part of a semiconductor substrate showing the manufacturing process of a semiconductor device in cross section, FIG. 9 is a graph showing the relationship between ion implantation amount, Vthl, and bit line junction breakdown voltage, and FIG. 10 is a graph showing the relationship between the bit line voltage and data read time. It is a graph diagram showing the relationship.

The semiconductor device of Example 1 shown in FIG. 6 is, for example, MR
This is a semiconductor chip la in which an OM is configured, and a memory mat A arranged on the semiconductor chip la is divided into a plurality of peripheral circuit areas B and C in order to shorten the wiring length of the word line system and prevent signal delay. ing. Note that memory pine) A is shown with diagonal lines to make the drawing easier to read.

In the peripheral circuit area B, an X decoder circuit, a word driver circuit, etc. are arranged, and in the peripheral circuit area C
A sense amplifier circuit is arranged corresponding to each memory mat A to detect and amplify a minute signal voltage. Note that these peripheral circuits are CM OS (Complemen
It is composed of a MOS (tary MOS) structure.

The memory cell circuit system shown in FIG. 5 has a vertical ROM structure in order to increase the speed of the bit line system. Two bit lines 2 are connected on both sides of the sense amplifier circuit placed in the center.
．． 2 is distributed and arranged, this bit line 2.2
A plurality of word lines 3 are arranged perpendicularly to the word lines 3. One MOS 4, which is a memory cell, is arranged at the intersection of the bit line 2 and the word line 3. Data writing to each MO34 is set by the high or low Vtl+ of MOS4, and MOS4a of high Vth (see Figure 4) is a cell in which H" data is written, and MOS4 of low Vth
S4b (see FIG. 4) is a cell in which "L" data is written. Note that the memory cells are composed of nMOS in order to achieve high speed performance. Furthermore, two dummy MOs 86 and 6 of the same size as the low Vth MOS are connected in series to the dummy word line 5.

Next, the MOS 4 constituting the memory device A of the semiconductor device of the first embodiment will be explained with reference to FIGS. 1 to 4.

In FIG. 4, the high Vth MOS 4a is placed in the center, and the low VLb MOS 4b is placed on both sides thereof. Further, in FIG. 1, word lines 3 are shown with diagonal lines to make the drawing easier to read.

For example, a diffusion layer 8 is formed in an X shape (FIG. 1) in a semiconductor substrate 7 made of p-type silicon with a specific resistance of about 10ΩcI11. The diffusion layer 8 is an impurity layer that forms the source and drain regions of the MOS 4, and is formed by introducing an n-type impurity such as arsenic into the semiconductor substrate 7.

A gate oxide film 9 made of silicon dioxide or the like is formed on the upper surface of the channel region E (FIG. 4) formed between the source and drain regions described above, and a high Vth MOS 4a is further formed on the upper surface. A gate electrode 10a and a gate electrode tab of a low-vth MOS 4b are formed.

The gate electrodes 10a and 10b constitute a part of the word line 3, and have a polycide structure consisting of a polysilicon layer 11 and a silicide layer 12 such as WS i laminated on top of the polysilicon layer 11. . Note that LDD (Light
Spacers 13 are formed to provide a structured structure.

In the semiconductor device of Example 1, the gate electrode 10a
A p-type impurity such as boron, which is an impurity of a conductivity type different from the n-type impurity introduced into the diffusion layer 8, was introduced into the polysilicon layer 11. That is, the gate electrode 10a of the MO 34a with high Vth is made into a p'' type gate.
If a p' type gate is used for 5, the flat band voltage will be approximately 1.1 V higher than that of the conventional technology that uses an n+ type agate for nMO3, so vth can be increased accordingly without increasing the ion dose. Can be set.

Note that a p-type impurity such as boron is introduced into the channel region E of the high Vth (DMOS 4a) (shown by the broken line in FIG. 4).

Furthermore, an n-type impurity such as arsenic is introduced into the polysilicon layer 11 of the gate electrode 10b. That is, low VL
The gate electrode 10b of the MO 34b of h is an n-type gate as in the conventional case.

An insulating film 14 made of BPSG or the like is deposited on the upper layer of the word line 3 (FIG. 3) so as to cover the word line 3. Note that the reason why BPSG was selected for the insulating film 14 is to capture mobile ions and flatten the surface of the insulating film. In addition, the insulating film 14 contains a small amount of SOG (spin on glass) containing a small amount of phosphorus, etc.
It may also be formed using a film or the like.

Each of the plurality of bit lines 2 disposed on the upper surface of the insulating film 14 is electrically connected to the above-mentioned diffusion layer 8 via a contact hole 15. Bit line 2 is Mo5iz
It consists of a barrier metal layer (not shown) such as, and an aluminum-silicon-copper alloy layer (not shown) laminated on top of the barrier metal layer. In addition, aluminum-silicon-
The reason why the barrier metal layer is formed below the copper alloy layer is to prevent silicon in the aluminum-silicon-copper alloy layer from precipitating at the bottom of the contact hole 15 and increasing the resistance value.

Each MO 34 is electrically isolated by a field oxide film 16 made of silicon dioxide or the like and a channel stopper region (not shown) formed by introducing p-type impurities below the field oxide film 16.

Next, an example of manufacturing such a semiconductor device is shown in FIGS. 7(a) to 7(a).
This will be explained with reference to (e) and FIGS. 8(a) to (j). The left side of FIG. 7 shows a cross-sectional view of the semiconductor substrate in the peripheral circuit area, and the right side shows a cross-section of the semiconductor substrate taken along the line 1--2 of FIG.

First, the semiconductor substrate 7 is subjected to oxidation treatment for 20 minutes in a dry oxygen atmosphere set at about 1000°C.
A thermal oxide film 17a having a thickness of about 23 am is formed on the 00) surface. After a silicon nitride film 18a with a thickness of about 5 Qnm is deposited on the upper surface of the thermal oxide film 17a by low-pressure CVD or the like, the silicon nitride film 18a in the open area of the photoresist 19a coated on the upper surface is coated with Freon gas plasma. Remove by etching method etc. Thereafter, in order to form an n-well 20 (see FIG. 7, etc.) to be described later, phosphorus, which is an n-type impurity, is ionized and applied to the semiconductor substrate 7 using photoresist 19a as a mask at a rate of about 1.2XIO''/cm.
' Dope. Note that during ion doping, the energy given to the ions is approximately 125 KeV (7th
Figure (a)).

Next, the photoresist 19a is removed, and the silicon nitride film 1
After silicon dioxide, etc. formed by oxidation of 8a is etched by an etching method using hydrogen fluoride, etc., the semiconductor substrate 7 is subjected to an oxidation treatment for a predetermined time in a dry oxygen atmosphere set at about 1000°C, and silicon nitride is etched. A thermal oxide film 17b is formed using the film 18a as a mask.

Subsequently, after removing the silicon nitride film 18a by a Freon gas plasma etching method or a hot phosphoric acid treatment, an etching process of approximately 1200 nm is performed to activate the n-type impurity doped for the n-well 20 and to achieve a predetermined impurity distribution. Thermal diffusion treatment is performed for 6 hours in a nitrogen atmosphere set at .degree. C. to form the above-mentioned n-well 20 (FIG. 7(b)).

Next, after pre-cleaning by an etching method using hydrogen fluoride or the like, oxidation treatment is performed for a predetermined time in a dry oxygen atmosphere set at about 1000° C. to form a thermal oxide film 17c with a thickness of about 20 am. Subsequently, a silicon nitride film 18c with a thickness of about 140 nm is deposited on the upper surface of the thermal oxide film 17C by low-pressure CVD, etc., and a photoresist 19 is further deposited on the upper surface of the silicon nitride film 18c.
Apply b. Then, the photoresist 19b is etched leaving only the element forming area, and the silicon nitride film 1 in the opening area is etched using the remaining photoresist 19b as a mask.
8c is etched (Fig. 7(C)).

After that, a photoresist 19C is applied to the pMO8 formation region F, and using this as a mask, p-type impurities such as boron fluoride are ionized, and the semiconductor substrate 7 is coated with approximately 3.0×10”
dope/crI. In addition, when doping with ions,
The energy given to the ions is about 50 KeV. Through this process, the field oxide film 16 (FIG. 7(e)
A channel stopper region (not shown) for nMO3 is formed in order to increase the Vo below (see FIG. 7(6)).

Next, the thermal oxide film 17c is etched by about 3 nm using an etching method using hydrogen fluoride, and after pre-cleaning its surface, it is subjected to oxidation treatment for 90 seconds in a steam oxidation atmosphere set at about 1000°C. A field oxide film 16 with a thickness of about 500 nm is formed. Furthermore, the thermal oxide film 17c is etched by about 30 nm by an etching method using hydrogen fluoride, and the surface thereof is cleaned, and then the silicon nitride film 18c described above is removed by a hot phosphoric acid treatment or the like (see FIG. 7).
e)).

Next, steps after the above-described removal process of the silicon nitride film 18c will be explained with reference to FIGS. 8(a) to 8('').

Note that the left side of FIG. 8 shows the cross section of the semiconductor substrate in the peripheral circuit area as in FIG. 7, and the right side shows the cross section of the semiconductor substrate in the peripheral circuit area as in FIG.
A cross section of the semiconductor substrate taken along the V line is shown.

First, the thermal oxide film 17c is etched by about 25 nm by an etching method using hydrogen fluoride, and the semiconductor substrate 7 is exposed. Next, the semiconductor substrate 7 is subjected to pre-oxidation treatment for a predetermined time in a steam oxidation atmosphere set at about 850° C. to form an oxide film (not shown) with a thickness of about 60 nm.
This oxide film is removed by etching using hydrogen fluoride. This step is a step for oxidizing and removing the silicon nitride film (not shown) formed at the interface between silicon and silicon dioxide in the step of forming the field oxide film 16.

Thereafter, the semiconductor substrate 7 is subjected to oxidation treatment in a steam atmosphere set at about 850° C. to form a gate oxide film 9 with a thickness of about 25 nm.

Next, pMOs 21aSnM in the peripheral circuit area, which will be described later.
In order to set the VLh of O522 (see FIG. 8 CD) to about 0°6 V, fluorine fluoride, which is a p-type impurity, is ionized and doped into the semiconductor substrate 7 at about I x 1012 atoms/cd. Note that the energy given to the ions during ion doping is approximately 3QKeV.

Next, a polysilicon layer 11 with a thickness of about 200 nm is formed on the upper surfaces of the gate oxide film 9 and the field oxide film 16 by thermally decomposing silane (SiHl) gas or the like using a low-pressure CVD method or the like.
Deposit.

Then, gate electrodes 23 and 24 of 9MO321a1 and nMO322 in the peripheral circuit area (FIG. 8(j)
In order to make the gate electrode 10b (see Fig. 4) of the low Vth M○s4b in the memory cell into an n0 type gate, arsenic, which is an n type impurity, is ionized and the polysilicon layer 11 is coated with approximately 5×10 The energy given to the ions during ion doping is about 40 KeV (FIG. 8(a)).

Next, after coating a photoresist 19d on the upper surface of the polysilicon layer 11 described above, in order to agate the gate electrode 10a of the high Vth MO 34a (see FIG. 8 (D)) into a p+ type, a high Vth MOS formation region H is formed. A hole is opened in the photoresist 19d, and the polysilicon layer 11 in the high Vth MO3 formation region H is ionized with boron fluoride, which is a p-type impurity, and doped with approximately 2×10'' boron fluoride/cd. is about 40
KeV (Figure 8 (c)).

After that, in order to write "H" data into the above-mentioned high Vth MO 34a, boron, which is a p-type impurity of a conductivity type different from the impurity introduced into the diffusion layer 8, is ionized into the high Vth MOS 4a formation region H, and the semiconductor substrate is For example, about 5×10”/cI11 is doped into 7.The energy given to the ions during ion doping is about 12
It is 0 KeV (Fig. 8(C)).

Next, CVD is applied to the upper layer of the polysilicon layer 11 described above.
A silicide layer 12 made of WSi2 is deposited by a method or a sputtering method, and then, using a resist pattern (not shown) as a mask, SF gas and C2C1!2F are deposited.
! The laminated film of the polysilicon layer 11 and the silicide layer 12 is etched into a predetermined shape in a mixed gas atmosphere to form gate electrodes IQa, 10b and gate electrodes 23.
Form 24. Note that the gate electrodes 10b, 23.24
Boron or arsenic contained in the silicide layer 12 may diffuse into the silicide layer 12, and the n-type polysilicon layer may become p-type. In such a case, for example, the polysilicon layer 11
and the silicide layer 12.

It is sufficient to form a silicon dioxide film (not shown) of nm thickness (
Figure 8(d)).

Subsequently, photoresist) 19e was applied, and then nMO
Remove only the photoresist 19e in the 5 formation region,
Using the remaining photoresist 19e as a mask, phosphorus, which is an n-type impurity, is ionized to form approximately lXl0''/
Dope cI11. This is n- in the LDD structure.
This is a step for forming a region (FIG. 8(e)).

Next, after removing the photoresist 19e, a silicon dioxide film (not shown) with a thickness of about 300 nm is deposited by low-pressure CVD or the like, and this is etched by reactive ion etching (RIE).
) etc. to form the spacer 13 so that it remains only on the side walls of the gate electrodes 10a, 10b and the gate electrodes 23 and 24. Further, after the RIE etching process, a silicon dioxide film (not shown) with a thickness of about 20 nm is deposited by CVD or the like (FIG. 8(f)).

Thereafter, a photoresist 19f is applied, holes are opened only in the nMO3 region of the photoresist 19f, and arsenic, which is an n-type impurity, is ionized to form the source and drain regions of nMO3, and gate electrodes 10a, lOb, and gate electrodes are formed. Approximately 5×10” pieces/c on the semiconductor substrate 7 using 24 as a mask
rl dope. Note that during ion doping, the energy given to the ions is approximately 80 KeV (see Figure 8 (
(to)).

Subsequently, after removing the photoresist 19f, a new photoresist 19g is applied, and holes are opened in the photoresist 19g only in the pMO3 forming region F. Then, in order to form the source and drain regions of the pMO321 (see FIG. 8(i)), boron fluoride, which is a p-type impurity, is ionized and doped with approximately 2×101S atoms/cI11 into the semiconductor substrate 7 using the gate electrode 10a as a mask. . Note that the energy given to the ions during ion doping is approximately 3QKeV (Figure 8 (Company)).

Then, in order to activate the n-type and p-color impurities doped into the semiconductor substrate 7 and to obtain a predetermined impurity distribution,
Heat treatment is performed for about 30 minutes at 00° C. in a nitrogen atmosphere to form a diffusion layer 8.25. Through this step, pM is formed on the semiconductor substrate 7 to form MOs 54a and 4b, which are memory cells, and peripheral circuits.

321, nMO3''22 is formed (Figure 8 (1))
.

Next, a silicon dioxide film (not shown) with a thickness of about 200 nm is deposited by CVD or the like, and then an insulating film 14 made of BPSG with a thickness of about 600 nm is deposited by CVD or the like. Thereafter, in order to flatten and increase the density of the insulating film 14, a glass reflow process is performed at about 950° C. in a nitrogen atmosphere for about 30 minutes.

Next, in order to be able to apply a voltage to the source, drain, and gate, the insulating film 14 is selectively etched by RIE using CHF or gas using a photoresist (not shown) as a mask to form the gate electrode 10a. , 10b,
Contact holes 15 are opened to expose the gate electrodes 23, 24 and the semiconductor substrate surface.

Subsequently, M with a thickness of about 20 nm is formed by sputtering or the like.
After depositing the oSi2 layer (not shown), an aluminum-silicon-copper alloy layer with a thickness Q of about 8 nm is deposited by the same sputtering method or the like.

Furthermore, after that, using a photoresist (not shown) as a mask, the above-described laminated film of the MoSi□ layer and the aluminum-silicon-copper alloy layer is patterned by RIE using CCβ4 gas, etc. to form bit lines. form 2. Note that the peripheral circuit constitutes an 0MO5 structure by pMOS21 and nMO322.

Finally, in order to recover from damage caused by sputtering, etc., heat treatment is performed at approximately 400°C in a hydrogen atmosphere for approximately 30 minutes, and then a PSG film with a thickness of approximately 1.0 μm is formed using a CVD method, etc.
A semiconductor device is manufactured by applying a surface protective film (not shown) consisting of (FIG. 8(J)).

By the way, it is conventionally better for a high vth MOS to have a high resistance in the channel. In other words, the higher V (1° is, the better. However, if this is increased by increasing the ion dose as in the prior art, the junction capacitance of the bit line will increase. Focusing on the bit line, the bit line capacitance is largest when all MOSs connected to this bit line have a high Vth, and is smallest when all MOSs connected to this bit line have a low Vth. Depending on the "H" and "L" patterns of the connected MOSs, large variations occur in the bit line capacitance of the memory cells and dummy cells.

To explain this in more detail in FIGS. 16(a) and (b), as shown in FIG. 16(a), when the ion dose of the high Vth MOS is low, the junction capacitance of the bit line does not increase. , bit line voltage variation ΔVs~ΔV7
is small, but in this case, the voltage drop on the H'' side is large, so the detection signal voltage V, , which operates the sense amplifier circuit is
It takes time to obtain 1, (usually 100 mV), resulting in a large delay time. Note that "H" indicates that the accessed bit is high Vth, and "L" indicates that the accessed bit is low Vth.

Furthermore, as shown in FIG. 16, etc., when the ion dose of the high Vth MOS is high, the voltage drop on the H'' side is small and good, but the bit line voltage variation ΔV, ~ΔV
IO becomes large and V is sufficient.

It takes time to obtain this, resulting in a large delay time.

Here, the effects of the MROM of the first embodiment will be explained with reference to FIGS. 9 and 10. In FIG. 9, the channel length is approximately 1.3 μm, and the channel width W is approximately 2.0 μm. (l
um, gate oxide film thickness t, , 8 is approximately 25 nm, and the energy given to boron fluoride during ion doping is approximately 80 K.
eV, and the substrate potential is OV.

According to the MROM of Example 1, for example, as shown in FIG. 9, even with the same ion dose (for example, 5×1012 ions/ca!), Vth is reduced by about 1 compared to the conventional one (indicated by the broken line). .1 V can be increased.

In addition, the same V+h can be achieved with less than half the ion dose of the conventional one.
(for example, 2.5V).

In other words, as shown in FIG. 10, the bit line voltage variations Δv1 to Δv3 due to the increase in bit line capacitance can be reduced, so the delay time of the bit line system can be significantly shortened, and data read can be accelerated.

Furthermore, according to the MROM of the first embodiment, for example, the ninth
As shown in the figure, while maintaining the same junction breakdown voltage as before,
The voltage is about 1. In addition, even if the vth is the same as the conventional one, the junction breakdown voltage can be significantly improved compared to the conventional one.

That is, a highly reliable semiconductor device can be provided.

[Embodiment 2] FIG. 11 is a plan view of a main part of a semiconductor chip showing a memory cell of a semiconductor device according to another embodiment of the present invention, FIG. 12 is a sectional view taken along line XI-XI in FIG. 11, and FIG. The figure is Figure 11xn
-xn line cross-sectional view, Fig. 14 is Fig. 11 x m -x,
It is a sectional view taken along the m-line.

In the semiconductor device of the second embodiment, as shown in FIGS. 11 to 14, the memory cell is composed of a capacitor 26 that stores memory in the form of charge, and a switching MO 327 that reads and writes this charge. This semiconductor chip lb includes a dynamic RAM (hereinafter referred to as DRAM).

The capacitor 26 is formed by introducing a plate electrode 28 made of polysilicon or the like, a capacitor insulating film 29 made of silicon dioxide or the like formed below the plate electrode, and an n-type impurity introduced into the semiconductor substrate 7 below the capacitor insulating film 29. It is composed of a diffusion layer 30. Note that the diffusion layer 30 constitutes the source and drain regions of the switching MO 327. Further, below the field oxide film 16, there is a parasitic MO
In order to set the Vth of 8 high, a p-type impurity such as boron is introduced to form a channel stopper region 31.

On the other hand, the switching MO 327 includes a gate electrode 32 made of polysilicon or the like, a gate oxide film 9 formed below the gate electrode 32, a source formed on the semiconductor substrate 7 below the gate oxide film 9 and on both sides of the gate electrode 32, It is composed of diffusion layers 30 and 30 which are drain regions. Diffusion layer 3
0 is formed by introducing n-type impurities, and the switching MO 327 is an n MOS. Note that the gate electrode 32 constitutes a part of the word line 3. The word line 3 is formed on the upper surface of an insulating film 33 covering the plate electrode 28, and an insulating film 14 is deposited on the upper layer thereof. A bit line 2 is arranged perpendicularly to the word line 3 on the upper surface of the insulating film 14 .

In the second embodiment, n introduced into the diffusion layer 30 of the switching MO 327 is applied to the plate electrode 28 of the capacitor 26 and the gate electrode 32 of the switching MO 327.
A p-type impurity such as boron, which is an impurity of a conductivity type different from the type impurity, was introduced.

That is, the plate electrode 28 and the gate electrode 32 are
It was shaped like a gate.

Therefore, the Vth of the parasitic MO3 formed in the field oxide film 16 region can be set high without increasing the ion dose.

Furthermore, the voltage of the switching MO 327 can be set high without increasing the ion dose.

According to the second embodiment, the following effects can be obtained.

(1) Since the VLh of the switching MO 327 can be set high without increasing the ion dose, the junction capacitance of the bit line 2 can be significantly reduced. As a result, variations in the signal voltage on the bit line 2 are reduced, and the detection signal voltage of the sense amplifier circuit (not shown) can be increased, allowing high-speed access.

(2) Parasitic M formed in the field oxide film 16 region
Since the Vth of O3 can be set high without increasing the ion dose, the junction breakdown voltage of the n''/p junction at the junction between the diffusion layer 30 and the channel stopper region 31 can be improved. , leakage current, etc. can be prevented, and a highly reliable semiconductor device can be provided.

Incidentally, in recent years, in order to lower the electric field strength of the capacitor insulating film 29, the plate electrode 28 is being set to a voltage of 1/2 Vcc, but in this case, the VL of the parasitic MO3
Since it is necessary to set h higher than the conventional Ov, it is particularly effective to make the plate electrode 28 of the second embodiment p-shaped.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

For example, in the first embodiment, the case where only the gate electrode of the high voltage MOS is a p-type gate is explained. However, the present invention is not limited to this.
The gate electrode of the Lh MOS or the gate electrode of the MOS constituting the peripheral circuit may be a p-type gate. In this case, n-type impurities are ion-implanted into the channel regions of the low Vth MOS and the MOS constituting the peripheral circuit, and the V, which has been increased by about 1.1V due to the p°-type gate, is lowered by about 1.1V.

Further, in the first embodiment, W is formed on the polysilicon.
Although the case has been described in which silicide layers made of Si2 are laminated, the present invention is not limited to this, and other silicide layers may be used.

In addition, in the first embodiment, the gate electrode is a polycide structure MO comprising a polysilicon layer and a silicide layer.
Although the case where S is formed has been described, the present invention is not limited to this, and for example, a salicide structure MOS may be formed. In this case, it is possible to prevent an increase in diffusion layer resistance due to shallow junctions of the source and drain.

In addition, in the above embodiment 1.2, the case where a p-type agate was used for nMO3 in order to increase vth was explained, but when the MOS is p-channel MO8, Vt
In order to increase h, an n-type gate is used as the gate.

In this case as well, without increasing the ion dose, v
th can be set high.

The above explanation will mainly focus on the mask ROMSDR, which is the field of application that was the background of the invention made by the present inventor.
Although the case where only AM is applied to a semiconductor device formed on a semiconductor chip has been described, it is not limited to this and can be applied in various ways, such as a composite gate array in which a logic circuit and a semiconductor memory are formed on the same semiconductor chip. It can also be applied to other semiconductor devices such as.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

That is, by introducing impurities of a conductivity type different from the impurities introduced into the source and drain regions of the MIS type semiconductor element into the gate electrode of the MIS type semiconductor element constituting at least the memory cell of the semiconductor memory,
Compared to the case where the impurities introduced into the source and drain regions and the impurities introduced into the gate electrode have the same conductivity type, the flat band voltage is higher, so VLh can be adjusted without increasing the ion dose to the channel. can be made higher.

Therefore, an increase in bit line capacitance due to an increase in ion dose is prevented, and high-speed access becomes possible.

In addition, the junction breakdown voltage of the bit line due to the increase in ion dose, or the p
A highly reliable semiconductor device is provided in which a decrease in n-junction breakdown voltage is prevented.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a memory cell of a semiconductor device according to an embodiment of the present invention, and FIGS.
5 is a circuit diagram showing the memory cell circuit system of this semiconductor device. FIG. 6 is an overall configuration diagram of this semiconductor device. FIG. 7(a)
~(e) is a sectional view of the main part of the semiconductor substrate showing the peripheral circuit area and the manufacturing process of the semiconductor device taken along the line ■-n line in FIG. 1. FIG. 8(a)~0) is the peripheral circuit area, and Figure 1■-
■A cross-sectional view of the main parts of a semiconductor substrate showing the manufacturing process of a semiconductor device in a line cross section, Figure 9 is a graph showing the relationship between the ion implantation amount, V, and bit line junction breakdown voltage, Figure 10 is a 11 is a graph diagram showing the relationship between line voltage and data read time; FIG. 11 is a plan view of a main part of a semiconductor chip showing a memory cell of a semiconductor device according to another embodiment of the present invention; FIGS. 12 to 14 are respectively Xr-xr in FIG.
a, xn-xUm% xm-xm line cross-sectional view, Figures 15 (a) and (b) are cross-sectional views of a semiconductor substrate showing the conventional method of setting V, Figure 16 (a), ( b) is a graph diagram showing the relationship between the conventional bit line voltage and data read time. la, lb...semiconductor chip, 2...bit line, 3
...War, Do line, 4...MOS, 4a...High VT
h MO814b...low V th (D M O3
,5...Dummy word line,6...Gummy-MO817
... Semiconductor substrate, 8, 30... Diffusion layer (source, drain region), 9... Gate oxide film, 10a... Gate electrode of high VLh MOS, 10b... Low V th
(DMOS (D gate electrode, 11... polysilicon layer, 12... silicide layer, 13... spacer, 14.33... insulating film, 15... contact hole, 16... Field oxide film, 17a-1'7c
...Thermal oxide film, 18a-18C''...Silicon nitride film, 19a-19g...Photoresist, 20...ln
Well, 21...pMOS, 22...-nMO5
, 23° 24... Gate electrode, 25... Diffusion layer, 2
6... Capacitor, 27... Switching MO51
28... Plate electrode, 29... Capacitor insulating film, 31... Channel stopper region, 32... Gate electrode, A... Memory mat, B, C... Peripheral circuit area, D...・Memory cell circuit system, E...channel region, F...9MO8 formation region, H...high V th
MOS formation region, 40... photoresist, 41...
・Conventional high VLhnMO8Sx...Conventional high Vthn
Formation region of MO3, Δv1 to ΔV+O...Variation in signal voltage, vs,...Detection signal voltage. 8 Layout layer (to source/drain) Figure Figure Figure Figure ROMIFFZ analysis BF;
mz>Figure 10, Figure 16! J Figure 14 1h Figure 15 (b)

Claims (1)

[Claims] 1. M constituting at least a memory cell of a semiconductor memory
1. A semiconductor device, wherein an impurity of a conductivity type different from that introduced into the source and drain regions of the MIS type semiconductor element is introduced into the gate electrode of the IS type semiconductor element. 2. The semiconductor memory is a mask ROM, the MIS type semiconductor element constituting the memory cell is a MOS transistor that performs storage depending on the level of the threshold voltage, and the gate electrode is connected to the high threshold voltage of the memory cell. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed as a MOS. 3. A semiconductor device comprising a dynamic RAM whose memory cells include a capacitor and a switching MOS transistor, wherein the source of the switching MOS transistor is connected to at least one of the plate electrode of the capacitor or the gate electrode of the switching MOS transistor. A semiconductor device characterized in that an impurity of a conductivity type different from the impurity introduced into the drain region is introduced.