KR20000046744A - Method for producing flash memory cell - Google Patents

Abstract

PURPOSE: A method for producing a flash memory cell is to improve a reliability of a device by preventing a drain disturb phenomenon at programming and preventing an erroneous operation of non-selected cell when reading operation is made. CONSTITUTION: A method for producing a flash memory cell comprises the steps of: forming a sacrificing film on an active area on a first conductive semiconductor substrate(31) and forming a first gate oxide film(37) on a remaining part; forming a first polycrystalline silicon layer on the first gate oxide film and forming a side wall(41) on a part corresponding to a side of the sacrificing film of the polycrystalline silicon layer; patterning the first polycrystalline silicon layer and the side wall longitudinally to form a plotting gate and forming a plotting gate by etching back the polycrystalline silicon layer using the side wall as a mask; exposing one side of the plotting gate by selectively removing the sacrificing film; forming a second gate oxide film and a second polycrystalline silicon layer on the semiconductor substrate and forming a control gate by patterning a predetermined part of the semiconductor substrate; and forming a secondary conductive type source and drain area on the semiconductor substrate.

Description

Manufacturing method of flash memory cell

The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to a method of manufacturing a flash memory cell capable of erasing data accumulated in a floating gate into a source region.

A flash memory cell is an inactive memory device having a high erase speed because it can erase memory array cells at the same time.

The flash memory cell applies a voltage of about 5V to the drain while the semiconductor substrate and the source are grounded, and injects hot electrons generated near the drain region into the floating gate by applying a high voltage of about 12V to the control gate. To program the data. Then, the semiconductor substrate and the control gate are grounded and a drain is floated, and a high voltage of about 12 V is applied to the source to erase the programmed data by Fowler-Nordheim tunneling electrons from the floating gate to the source.

In a flash memory having an ETOX (EEPROM Tunneling Oxide) structure, a cell has a floating gate formed on a gate oxide film, also called a tunneling oxide film, on which the silicon oxide or silicon oxide / silicon nitride / silicon oxide ( An interlayer dielectric film (hereinafter referred to as ONO) is formed, and has a structure in which a control gate is superimposed on the interlayer dielectric film.

1A to 1D are manufacturing process diagrams of a flash memory cell according to the prior art.

Referring to FIG. 1A, a field insulating layer 13 is formed on a P-type semiconductor substrate 11 to define an active region of a device by a local oxide of silicon (LOCOS) method or a shallow trench isolation (STI) method.

A gate oxide film 15 used as a tunneling oxide film is formed in the active region of the device where the field insulating film 13 of the semiconductor substrate 11 is not formed by a thermal oxidation method. On the field insulating film 13 and the gate oxide film 15, the first polysilicon layer 17 is deposited thickly by chemical vapor deposition (hereinafter, referred to as CVD). The first polysilicon layer 17 is patterned by photolithography to have a stripe shape in the longitudinal direction of the channel.

Referring to FIG. 1B, an interlayer insulating film 19 having an ONO structure covering the patterned first polysilicon layer 17 is formed on the semiconductor substrate 11, and the interlayer insulating film 19 is formed on the interlayer insulating film 19 by a CVD method. 2 polysilicon layer 21 is formed.

Referring to FIG. 1C, a photoresist (not shown) is applied on the second polysilicon layer 21 and then patterned in the width direction of the channel perpendicular to the length direction of the channel by exposure and development.

Then, using the photoresist as a mask, the second polysilicon layer 21, the interlayer insulating film 19, the first polysilicon layer 17, and the gate oxide film 15 are sequentially patterned. At this time, portions of the first and second polysilicon layers 17 and 21 that remain unetched under the photoresist are the floating gate 18 and the control gate 22, respectively. Remove the photoresist.

The photoresist 23 is applied to the entire surface of the above-described structure, and then exposed and developed to expose one side of the floating gate 18 and the control gate 22 of the semiconductor substrate 11. Then, using the photoresist 23 as a mask, N-type impurities having a high diffusion rate such as phosphorus (P) in the exposed portions of the semiconductor substrate 11 may be approximately 5 × 10 ^{14 to} 1 × 10 ¹⁵ / cm 2. Ion implantation into the dose forms the low concentration region 25. At this time, the low concentration region 25 is also diffused laterally so as to overlap a predetermined portion with the floating gate 18.

Referring to FIG. 1D, the photoresist 23 is removed. Using the control gate 22 as a mask, N-type impurities having a slow diffusion rate such as As are ion-infused with a dose of about 5 × 10 ^{15 to} 1 × 10 ¹⁶ / cm 2 to obtain a high concentration source and drain region ( 27) form 28. At this time, since impurities such as As have a slow diffusion rate, the source and drain regions 27 and 28 are formed to have a shallow depth. In particular, the source region 27 has a low concentration region 25 and a double diffusion. Structure.

The flash memory cell formed as described above suppresses the occurrence of a breakdown phenomenon in which the junction between the source region and the semiconductor substrate is destroyed by the low concentration region when the high voltage is applied to the source region to tunnel the charge stored in the floating gate to the source region and erased. In the above, since the tunneling oxide film is thin, tunneling of charges is easy.

However, the flash memory cell manufactured according to the prior art has a thin gate oxide film.

A drain disturb occurs when an unwanted cell is programmed by a drain voltage applied during programming, or when the cell is over erased, a threshold voltage (Vt) is lowered, thereby causing a read operation. An adjacent cell that is not selected at the time of malfunction has a problem of lowering the reliability of the device.

Accordingly, an object of the present invention is to manufacture a flash memory cell that can improve the reliability of the device by preventing drain disturb during programming and also preventing malfunction of the overerased adjacent cells which are not selected during a read operation. In providing a method.

A method of manufacturing a flash memory cell according to the present invention for achieving the above object comprises the steps of forming a sacrificial film having a side surface in a predetermined portion of the active region on the first conductive semiconductor substrate and forming a first gate oxide film in the remaining portion; Forming a first polysilicon layer covering the sacrificial layer on the first gate oxide layer and forming sidewalls in a portion corresponding to a side surface of the sacrificial layer of the first polysilicon layer; and the first polysilicon layer; Forming a floating gate by patterning sidewalls to have a stripe shape in the longitudinal direction of the channel, and etching back the first polysilicon layer using the sidewalls as a mask to form a floating gate; and selectively removing the sacrificial layer Exposing one side of the floating gate and the floating on the semiconductor substrate Forming a second gate oxide film and a second polysilicon layer to cover the gate, overlapping a predetermined portion of the semiconductor substrate and one side of the floating gate, and forming a control gate by patterning a stripe shape in the width direction of the channel; And forming a source and drain region of a second conductivity type on the semiconductor substrate using the control gate as a mask.

1A to 1D are manufacturing process diagrams of a flash memory cell according to the prior art.

2A to 2E are manufacturing process diagrams of a flash memory cell according to the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are manufacturing process diagrams of a flash memory cell according to the present invention.

Referring to FIG. 2A, a field insulating film 33 defining an active region of an element is formed on a P-type semiconductor substrate 31 by the LOCOS method or the STI method.

A silicon nitride having an etch selectivity different from that of the field insulating film 33 is deposited on the semiconductor substrate 31 to a thickness of about 3000 to 10000 GPa and patterned so as to remain only on the active region of the device to form a sacrificial film 35. Then, the portion of the semiconductor substrate 31 where the field insulating film 33 and the sacrificial film 35 are not formed is oxidized to a thickness of about 50 to 100 Å to form a first gate oxide film 37 used as a tunneling oxide film.

Referring to FIG. 2B, polycrystalline silicon doped with impurities on the field insulating layer 33 and the first gate oxide layer 37 is deposited to cover the sacrificial layer 35 by a CVD method to form the first polycrystalline silicon layer 39. Form.

An insulating material having a different etching selectivity from that of the sacrificial film 35, that is, silicon oxide, is deposited on the first polysilicon layer 39 by CVD. The sacrificial film of the first polysilicon layer 39 is etched back by etching the insulating material by using a reactive ion etching method such that the surface of the first polysilicon layer 39 is exposed. The side wall 41 is formed in a portion corresponding to the side surface of the 35.

Referring to FIG. 2C, the first polysilicon layer 39 and the sidewalls 41 are patterned by photolithography to have a stripe shape in the longitudinal direction of the channel.

Using the sidewall 41 as a mask, the first polysilicon layer 39 is etched back by the RIE method so that the semiconductor substrate 31 and the sacrificial film 35 are exposed. At this time, the remaining first polysilicon layer 39 becomes a floating gate, and the tunneling region is defined by the floating gate 39 and the sidewalls 41.

The sacrificial layer 35 is selectively removed by a wet method to expose one side of the floating gate 39. In this case, the field insulating layer 33 and the sidewall 41 are not etched because the etching selectivity is different from that of the sacrificial layer 35.

Referring to FIG. 2D, a second gate oxide film 43 having a thickness of about 200 to 400 Å is formed on the surface of one side of the semiconductor substrate 31 and the floating gate 39, and impurities are formed on the second gate oxide film 43. The doped polysilicon is deposited by CVD to form a second polysilicon layer 45.

The second polysilicon layer 45 and the second gate oxide layer 43 are patterned by a photolithography method so as to overlap the semiconductor substrate 31 and the floating gate 39 and have a stripe shape in the width direction of the channel. . At this time, the remaining second polysilicon layer 45 becomes a control gate. In addition, the remaining portion of the second gate oxide film 43 overlapping with the floating gate 39 is used as the interlayer insulating film, and the portion formed on the semiconductor substrate 31 is used as the gate oxide film.

The photoresist 47 is applied to the surface of the structure described above, and then patterned by exposure and development to expose the other side of the floating gate 39 of the semiconductor substrate 31. Then, using the photoresist 47 as a mask, N-type impurities having a high diffusion rate such as phosphorus (P) in the exposed portions of the semiconductor substrate 31 are formed in a range of 5 × 10 ^{14 to} 1 × 10 ¹⁵ / cm 2. Ion implantation into the dose forms a low concentration region 49. At this time, the low concentration region 49 is also diffused laterally so as to overlap a portion of the floating gate 39.

Referring to FIG. 2E, the photoresist 47 is removed. Then, using the control gate 45 as a mask, N-type impurities having a slow diffusion rate such as As are ion-implanted with a dose of about 5 × 10 ^{15 to} 1 × 10 ¹⁶ / cm 2 to obtain a high concentration source and drain region ( 51 and 53 are formed. At this time, since impurities such as As have a slow diffusion rate, the source and drain regions 51 and 53 are formed to have a shallow depth. In particular, the source region 51 has a low concentration region 49 and a double diffusion. Structure.

In the flash memory cell manufactured as described above, a thick second gate oxide layer 43 is formed near the drain region 53, thereby preventing hot electrons from being injected into the floating gate of the cell that is not selected by the drain voltage applied during programming. This prevents drain disturb in which the cell is programmed. If the over erased cell is not selected during the read operation, the control gate 45 is grounded even if the threshold voltage (Vt) of the portion where the floating gate 39 is formed is lowered. The cell is turned off and is not operated, thereby preventing the cell from malfunctioning.

Therefore, the present invention not only prevents a drain disturb phenomenon during programming but also prevents malfunction of adjacent cells which are not selected during a read operation, thereby improving reliability of the device.

Claims (3)

Forming a sacrificial film having a side surface at a predetermined portion of the active region on the first conductive semiconductor substrate and forming a first gate oxide film at the remaining portion; Forming a first polycrystalline silicon layer covering the sacrificial film on the first gate oxide film and forming sidewalls at a portion corresponding to a side surface of the sacrificial film of the first polycrystalline silicon layer; Patterning the first polysilicon layer and the sidewall to have a stripe shape in the longitudinal direction of the channel to form a floating gate, and using the sidewall as a mask to etch back the first polysilicon layer to form a floating gate; Selectively removing the sacrificial layer to expose one side of the floating gate; Forming a second gate oxide layer and a second polysilicon layer on the semiconductor substrate to cover the floating gate, overlapping a predetermined portion of the semiconductor substrate and one side of the floating gate, and patterning a stripe shape in a width direction of the channel; Forming a control gate, And forming a source and drain region of a second conductivity type on the semiconductor substrate using the control gate as a mask. The method of claim 1, wherein the sacrificial layer is formed of silicon nitride. The method of claim 1, wherein the sidewalls are formed of silicon oxide having an etch ratio different from that of the sacrificial layer.