KR20000045459A - Method for etching semiconductor device - Google Patents
Method for etching semiconductor device Download PDFInfo
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- KR20000045459A KR20000045459A KR1019980062017A KR19980062017A KR20000045459A KR 20000045459 A KR20000045459 A KR 20000045459A KR 1019980062017 A KR1019980062017 A KR 1019980062017A KR 19980062017 A KR19980062017 A KR 19980062017A KR 20000045459 A KR20000045459 A KR 20000045459A
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- 238000005530 etching Methods 0.000 title claims abstract description 134
- 238000000034 method Methods 0.000 title claims abstract description 114
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 claims abstract description 32
- 239000007789 gas Substances 0.000 claims description 99
- 239000000460 chlorine Substances 0.000 claims description 12
- 238000004544 sputter deposition Methods 0.000 claims description 10
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052801 chlorine Inorganic materials 0.000 claims description 6
- 229910015844 BCl3 Inorganic materials 0.000 claims description 4
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- -1 and one of N2 Substances 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 2
- 230000004907 flux Effects 0.000 abstract 5
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
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Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 반도체장치의 제조함에 있어서, 플라즈마를 이용한 건식 식각공정기술 및 스트립공정, PE-CVD, 스퍼터링공정 등 플라즈마를 이용한 반도체제조공정기술에 적합한 반도체소자의 식각방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, in manufacturing a semiconductor device, suitable for dry etching using plasma and semiconductor manufacturing using plasma such as strip process, PE-CVD, sputtering process, etc. It relates to an etching method of a semiconductor device.
기존 반도체장치의 제조공정용 건식식각 공정기술의 경우는, 도 1 에 도시된 바와같이, 식각타겟트층에 대한 주요식각단계와 하부층이 들어나기 시작하는 시점(end of process)부터 적용되는 과식각단계로 구성된다.In the case of the dry etching process technology for the manufacturing process of the existing semiconductor device, as shown in Figure 1, the main etching step for the etching target layer and the over-etching step applied from the end of the process (end of process) begins to enter It consists of.
또한, 식각타겟트층이 다층의 적층구조로 이루어진 경우는, 도 2 에 도시된 바와같이, 주요 식각단계가 다시 수개의 세분화된 단계로 구분된다.In addition, when the etch target layer is formed of a multilayer structure, as shown in Figure 2, the main etching step is divided into several subdivided steps again.
이러한 단계들은 공정가스, 공급전력, 공정압력, 공정온도, 공정시간 등 여러 공정변수들의 조합으로서 일정한 공정단계의 경우 모든 변수들은 일정한 값으로 유지된다.These stages are a combination of several process variables such as process gas, supply power, process pressure, process temperature, and process time. For a given process step, all variables remain constant.
상기 여러 공정변수들중 공정가스의 경우, 해당 공정의 식각률을 결정하는 타겟트층과 화학적 반응성이 높은 주요 식각가스와 그 외 식각 프로파일, PR 선택도(selectivity) 등의 부수적인 공정 요구조건을 만족시키기 위한 여러 추가 가스들의 일정한 혼합으로 이루어진다.Among the above process variables, in case of process gas, the target layer which determines the etch rate of the process, main etching gas having high chemical reactivity, and other process requirements such as etching profile, PR selectivity, etc. are satisfied. Constant mixing of several additional gases.
여러 공정가스들의 혼합비는 여러 공정요구 조건들이 최대한 만족될 수 있도록 결정되지만, 각 가스간의 역할차이에 의한 트레드-오프(trade-off) 관계로 존재할 경우 식각률에 비중을 두게 된다.The mixing ratio of the various process gases is determined so that various process requirements can be satisfied as much as possible, but when there is a trade-off relationship due to the role difference between each gas, the etch rate is weighted.
이런 경우에, 잔류물을 제거하기 위하여 과식각 타겟트가 길어지므로 플라즈마유도 전하에 의해 손상이 증가하게 된다.In such a case, the overetch target is lengthened to remove the residues, thereby increasing damage due to plasma induced charges.
또한, 프로파일 유지를 위하여 높은 바이어스전력(high bias power) 공정조건을 적용하면 높은 이온에너지충격(bonbardment)에 의한 플라즈마유도 물리적 손상이 증가한다.In addition, applying a high bias power process condition to maintain the profile increases physical damage to the plasma induced by high ion energy impact (bonbardment).
보다 구체적인 예로 반도체소자용 Al 패터닝공정을 살펴보면 다음과 같다.A more specific example of the Al patterning process for semiconductor devices is as follows.
Al 식각공정의 경우, 대부분 일정한 혼합비의 Cl2와 BCl3 가스를 이용한다. 도 4 에 도시된 바와같이, Cl2 가스량이 증가할수록 Al 식각률이 증가하지만, 식각프로파일은 식각단면에 형성되는 폴리머의 감소로 공정 마진이 감소하는데, 심한 경우에는 보울링(bowing)등의 문제를 나타내게 된다.In the case of Al etching process, Cl2 and BCl3 gas are usually used in a constant mixing ratio. As shown in FIG. 4, the Al etching rate increases as the amount of Cl2 gas increases, but the etching profile decreases the process margin due to the decrease of polymers formed in the etching cross-section, and in severe cases, shows problems such as bowing. .
또한, 아래 표 1 에 도시된 바와같이, Al 층에 포함되어 있는 여러 금속성분들에 대한 식각률의 차이로 Cl2 혼합비가 증가할수록 Al 식각률은 증가하지만, Cu 에 대한 낮은 식각률로 Cu 입자가 식각장벽역할을 하여 잔류물은 증가하게 된다.In addition, as shown in Table 1 below, the Al etching rate increases as the Cl2 mixing ratio increases due to the difference in etching rates for the various metal components included in the Al layer, but the Cu particles act as an etching barrier due to the low etching rate for Cu. The residue is then increased.
<표 1>TABLE 1
이러한 여러 공정 결과들의 트레드-오프(trade-off)관계로 종래의 공정은 적당한 Al 식각률과 적당한 프로파일, 잔류물 특성등을 얻을 수 있는 가스혼합비를 선택하여 사용한다.As a result of the trade-off of these various process results, the conventional process selects and uses a gas mixture ratio to obtain an appropriate Al etch rate, a suitable profile, and residue characteristics.
그러므로, 부족한 공정결과를 보상하기 위한 과도한 과식각타겟트, 좁은 공정마진 등의 문제점을 감수하여야만 하고, 구현가능한 공정 결과도 제한을 받는다.Therefore, it is necessary to bear the problems of excessive over-etching target and narrow process margin to compensate for the insufficient process result, and the process result that can be implemented is also limited.
이에, 본 발명은 상기 종래의 제반 문제점을 해소하기 위하여 안출한 것으로서, 식각공정에 있어서의 식각프로파일을 개선시키고, 식각잔류물을 효과적으로 제거할 수 있는 반도체소자의 식각방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide an etching method of a semiconductor device capable of improving the etching profile in an etching process and effectively removing the etching residues. .
또한, 본 발명의 다른 목적은 공정마진을 증가시키며, 식각공정에서의 손상을 감소시키므로써 반도체소자의 제조공정수율을 향상시킬 수 있는 반도체소자의 식각방법을 제공함에 있다.In addition, another object of the present invention is to provide an etching method of a semiconductor device that can increase the process margin and reduce the damage in the etching process to improve the manufacturing process yield of the semiconductor device.
상기 목적을 달성하기 위한 본 발명은, 반도체 제조 공정용 식각공정에 있어서, 한 공정단계내에서 식각공정에 이용하는 주식각가스 및 추가식각가스들의 유량을 시간에따라 변화시키면서 식각공정을 실시하는 것을 특징으로한다.In the present invention for achieving the above object, in the etching process for semiconductor manufacturing process, the etching process is performed while changing the flow rate of the stock angle gas and the additional etching gas used for the etching process in one process step with time Should be.
본 발명의 기술적 요지는, 종래의 플라즈마를 이용한 반도체 제조용 식각 공정에서는 한 단계내에서 일정하게 유지되던 공정가스의 혼합비를 시간에 따라 변화시키므로써 각 가스들에 대한 특정공정 결과를 극대화할 수 있으며, 가스펄스 간격 및 유량을 조절하므로써 트레드-오프(trade-off)관계에 있는 공정결과들을 동시에 만족시킬 수 있다.Technical aspect of the present invention, in the etching process for semiconductor manufacturing using a conventional plasma by maximizing the mixing ratio of the process gas was kept constant in one step with time can maximize the specific process results for each gas, By adjusting the gas pulse interval and flow rate, the process results in the trade-off relationship can be satisfied simultaneously.
도 1 은 종래기술에 따른 반도체장치의 제조공정에 있어서 식각타겟트층에 대한 주 식각단계와 과 식각단계를 설명하기 위한 단면도,1 is a cross-sectional view for explaining the main etching step and the etching step for the etching target layer in the semiconductor device manufacturing process according to the prior art,
도 2 는 종래기술에 따른 다수개의 적층구조로된 식각타겟트층에 대한 주 식각단계와 과식각단계를 설명하기 위한 단면도,2 is a cross-sectional view for explaining the main etching step and the over-etching step for the etching target layer having a plurality of laminated structure according to the prior art,
도 3 은 종래기술에 따른 반도체장치의 제조공정에 있어서의 주 식각단계와 과식각단계에 대한 시간에 따른 파라미터의 변화를 나타낸 그래프,3 is a graph showing a change of a parameter with time for a main etching step and an over etching step in the manufacturing process of a semiconductor device according to the prior art;
도 4 는 종래기술에 따른 반도체장치의 제조공정에 있어서, Cl2 / (Cl2 + BCl3)에 대한 Al 유량의 변화를 나타낸 그래프,4 is a graph showing a change in Al flow rate for Cl 2 / (Cl 2 + BCl 3) in the manufacturing process of a semiconductor device according to the prior art;
도 5 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 식각단계에서 시간에 따른 가스유량을 나타낸 그래프,5 is a graph showing a gas flow rate with time in an etching step in a manufacturing process of a semiconductor device according to the present invention;
도 6 은 본 발명에 따른 반도체장치의 제조공정에 있어서, 구간 A 에서의 식각진행 및 구간 B에서의 폴리머의 증착을 설명하기 위한 단면도,6 is a cross-sectional view for describing an etching process in a section A and deposition of a polymer in a section B in a manufacturing process of a semiconductor device according to the present invention;
도 7 는 본 발명에 따른 반도체장치의 제조공정에 있어서, Cl2 및 BCl3 플라즈마의 스퍼터링에의한 현저한 반응특성을 설명하기 위한 단면도,7 is a cross-sectional view for explaining the remarkable reaction characteristics by sputtering of Cl 2 and BCl 3 plasma in the manufacturing process of a semiconductor device according to the present invention;
도 8a 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 주 식각가스에 대한 일정 펄스 / 일정 유량을 나타낸 그래프,8A is a graph showing a constant pulse / constant flow rate for a main etching gas in the manufacturing process of a semiconductor device according to the present invention;
도 8b 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 주 식각가스에 대한 일정 펄스 / 변화 유량을 나타낸 그래프,8B is a graph showing a constant pulse / change flow rate for the main etching gas in the manufacturing process of the semiconductor device according to the present invention;
도 8c 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 주 식각가스에 대한 변화 펄스 / 일정 유량을 나타낸 그래프,8C is a graph showing a change pulse / constant flow rate for a main etching gas in the manufacturing process of a semiconductor device according to the present invention;
도 8d 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 주 식각가스에 대한 변화 펄스 / 변화 유량을 나타낸 그래프,8D is a graph showing a change pulse / change flow rate for a main etching gas in the manufacturing process of a semiconductor device according to the present invention;
도 9a 내지 9d 는 본 발명에 따른 반도체장치의 공정에 있어서, 추가가스일정펄스 / 일정유량을 공급시킬때의 그래프,9A to 9D are graphs for supplying additional gas constant pulse / constant flow rate in the process of the semiconductor device according to the present invention;
도 10 은 본 발명에 따른 반도체장치의 공정에 있어서, 주 식각가스 및 추가 가스펄스의 공급을 나타낸 그래프이다.10 is a graph showing the supply of the main etching gas and additional gas pulses in the process of the semiconductor device according to the present invention.
이하, 본 발명에 따른 반도체소자의 식각방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, an etching method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 5 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 식각단계에서 시간에 따른 가스유입량을 나타낸 그래프이다.5 is a graph showing a gas inflow rate with time in an etching step in the manufacturing process of a semiconductor device according to the present invention.
도 6 은 본 발명에 따른 반도체장치의 제조공정에 있어서, 구간 A 에서의 식각진행 및 구간 B에서의 폴리머의 증착을 설명하기 위한 단면도이다.6 is a cross-sectional view for describing an etching process in a section A and deposition of a polymer in a section B in a manufacturing process of a semiconductor device according to the present invention.
도 7 는 본 발명에 따른 반도체장치의 제조공정에 있어서, Cl2 및 BCl3 플라즈마의 스퍼터링에의한 현저한 반응특성을 설명하기 위한 단면도이다.7 is a cross-sectional view for explaining the remarkable reaction characteristics by sputtering of Cl2 and BCl3 plasma in the semiconductor device manufacturing process according to the present invention.
본 발명은 제조공정내에서 공급되어지는 가스의 유량을 시간에 따라 제어하므로써 구현된다.The present invention is implemented by controlling the flow rate of the gas supplied in the manufacturing process over time.
먼저, 반도체소자용 금속배선의 패터닝의 경우를 살펴 보면 다음과 같다.First, a case of patterning metal wiring for semiconductor devices is as follows.
주요단계에서 공급되어지는 주 식각가스(Cl2)의 유량을, 도 5 에 도시된 바와같이, 시간에 따라 변화시킨다.The flow rate of the main etching gas Cl 2 supplied in the main step is changed over time, as shown in FIG. 5.
Cl2유량이 상대적으로 농후해지는 "구간 A"에서는 Cl2의 높은 Al 식각률 특성으로 인한 식각반응이 주를 이루게 되며, 상대적으로 BCl3유량이 농후해지는 "구간 B" 에서는 스퍼터링반응이 주를 이루게 된다.In "section A" where the Cl 2 flow rate is relatively concentrated, the etching reaction is mainly caused by the high Al etch rate characteristic of Cl 2 , and sputtering reaction is predominant in "section B" where the BCl 3 flow rate is enriched. .
또한, 도 6 에 도시된 바와같이, "구간 B"의 시간을 조절하므로써 BCl3플라즈마의 폴리머 리치(rich) 특성으로 식각 프로파일이 개선된다.In addition, as shown in Figure 6, by controlling the time of the "section B", the etching profile is improved by the polymer rich characteristics of the BCl 3 plasma.
그리고, 도 7 에 도시된 바와같이, BCl3플라즈마의 스퍼터링의 현저한(dominant) 지배적인 반응특성으로 Cu 입자에 대한 높은 식각률로 잔류물을 효과적으로 감소시킬 수 있다.And, as shown in Figure 7, the dominant reaction characteristics of the sputtering of the BCl 3 plasma can effectively reduce the residue with a high etching rate for the Cu particles.
이러한 개념으로, 가스펄스 간격 및 유량을 조절하므로써 공정가스 각각에 대해서 요구되어지는 공정결과들에 대한 선별적인 제어가 가능하다.This concept allows selective control of the process results required for each process gas by adjusting the gas pulse interval and flow rate.
기존의 일정가스혼합비방식으로는 제한되었던 트레드-오프(trade-off)관계의 공정결과들을 동시에 만족시킬 수 있는 최적의 공정조건을 구현할수 있다.Existing constant gas mixture ratio method can realize the optimum process condition that can satisfy the trade result of the tread-off relationship.
적용가능한 펄스가스 공급방식들중, 추가가스유량을 일정하게 유지한 상태에서 주 식각가스에 대한 펄스 / 유량공급을 나타낸 실시예들을 도 8a 내지 8d를 참조하여 설명하면 다음과 같다.Among the applicable pulse gas supply methods, embodiments showing the pulse / flow rate supply for the main etching gas in a state where the additional gas flow rate is kept constant will be described with reference to FIGS. 8A to 8D.
도 8a 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 주요 식각가스에 대한 일정 펄스 / 일정 유량을 나타낸 그래프로서, 이는 식각공정(주요 또는 과식각)에서 주요 식각가스를 일정펄스(0∼300 초)/일정 유량(0∼1000 sccm) 공급방식으로 제어하는 방식이다.FIG. 8A is a graph showing a constant pulse / constant flow rate for a main etching gas in a manufacturing process of a semiconductor device according to the present invention, which represents a constant pulse (0 to 300) for a main etching gas in an etching process (major or overetching). Second) / constant flow rate (0 to 1000 sccm)
또한, 도 8b 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 주요 식각가스에 대한 일정 펄스 / 변화 유량을 나타낸 그래프로서, 이는 식각공정(주요 또는 과식각)에서 주요 식각가스를 일정펄스(0∼300 초) / 변화 유량(0∼1000 sccm) 공급방식으로 제어하는 방식이다.8B is a graph showing a constant pulse / change flow rate for the main etching gas in the manufacturing process of the semiconductor device according to the present invention, which is a constant pulse (0) for the main etching gas in the etching process (main or overetching). 300 seconds) / change flow rate (0 to 1000 sccm) supplying method.
그리고, 도 8c 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 주요 식각가스에 대한 변화 펄스 / 일정 유량을 나타낸 그래프로서, 이는 식각공정(주요 또는 과식각)에서 주요 식각가스를 변화펄스(0∼300 초)/일정 유량(0∼1000 sccm) 공급방식으로 제어하는 방식이다.8C is a graph showing a change pulse / constant flow rate for the main etching gas in the manufacturing process of the semiconductor device according to the present invention, which is used to change the main etching gas in the etching process (main or overetching). To 300 seconds) / constant flow rate (0 to 1000 sccm).
또한, 도 8d 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 주요 식각가스에 대한 변화 펄스 / 변화 유량을 나타낸 그래프로서, 이는 식각공정(주요 또는 과식각)에서 주요 식각가스를 변화펄스(0∼300 초) / 변화 유량(0∼1000 sccm) 공급방식으로 제어하는 방식이다.8D is a graph showing a change pulse / change flow rate for the main etching gas in the manufacturing process of the semiconductor device according to the present invention, which is used to change the main etching gas in the etching process (main or overetching). 300 seconds) / change flow rate (0 to 1000 sccm) supplying method.
한펴, 주식각가스 공급을 일정하게 유지한 상태에서 추가가스에 대한 펄스/유량 공급방식의 실시예들을 도9a 내지 9d을 참조하여 설명하면 다음과같다.In the meantime, the embodiments of the pulse / flow rate supply method for the additional gas in the state of maintaining the stock angular gas supply are as follows with reference to Figs. 9A to 9D.
도 9a 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 추가 식각가스에 대한 일정 펄스 / 일정 유량을 나타낸 그래프로서, 이는 식각공정(주요 또는 과식각)에서 추가 식각가스를 일정펄스(0∼300 초)/일정 유량(0∼1000 sccm) 공급방식으로 제어하는 방식이다.FIG. 9A is a graph showing a constant pulse / constant flow rate for an additional etching gas in a manufacturing process of a semiconductor device according to the present invention, which is a constant pulse (0 to 300) for an additional etching gas in an etching process (main or overetching). Second) / constant flow rate (0 to 1000 sccm)
또한, 도 9b 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 추가 식각가스에 대한 일정 펄스 / 변화 유량을 나타낸 그래프로서, 이는 식각공정(주요 또는 과식각)에서 추가 식각가스를 일정펄스(0∼300 초) / 변화 유량(0∼1000 sccm) 공급방식으로 제어하는 방식이다.In addition, Figure 9b is a graph showing a constant pulse / change flow rate for the additional etching gas in the manufacturing process of the semiconductor device according to the present invention, which is a constant pulse (0) to the additional etching gas in the etching process (main or over-etching) 300 seconds) / change flow rate (0 to 1000 sccm) supplying method.
그리고, 도 9c 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 추가 식각가스에 대한 변화 펄스 / 일정 유량을 나타낸 그래프로서, 이는, 식각공정(주요 또는 과식각)에서 추가 식각가스를 변화펄스(0∼300 초)/일정 유량(0∼1000 sccm) 공급방식으로 제어하는 방식이다.9C is a graph showing a change pulse / constant flow rate for the additional etching gas in the manufacturing process of the semiconductor device according to the present invention, which indicates that the additional etching gas is changed in the etching process (main or overetching). 0 to 300 seconds) / constant flow rate (0 to 1000 sccm).
또한, 도 9d 는 본 발명에 따른 반도체장치의 제조공정에 있어서, 추가 식각가스에 대한 변화 펄스 / 변화 유량을 나타낸 그래프로서, 이는, 식각공정(주요 또는 과식각)에서 추가 식각가스를 변화펄스(0∼300 초) / 변화 유량(0∼1000 sccm) 공급방식으로 제어하는 방식이다.9D is a graph showing a change pulse / change flow rate for the additional etching gas in the manufacturing process of the semiconductor device according to the present invention, which indicates that the additional etching gas is changed in the etching process (main or overetching). 0 to 300 sec) / change flow rate (0 to 1000 sccm)
도 10 은 본 발명에 따른 반도체장치의 식각공정에 있어서, 주요가스 대 추가가스의 펄스 공급을 나타낸 그래프이다.10 is a graph showing pulse supply of main gas versus additional gas in the etching process of the semiconductor device according to the present invention.
상기와 같은 가스공급방식을 식각공정이외의 스트립(strip), PECVD, 스퍼터링 등 플라즈마를 이용하는 반도체 제조공정에 이용할 수 있다.The gas supply method as described above may be used for semiconductor manufacturing processes using plasma, such as stripping, PECVD, and sputtering, in addition to etching processes.
한편, 본 발명에 따른 다른 실시예들로써, 식각 타겟트층으로 상기에서 보여준 알루미늄층외에 산화막, 텅스텐층, 폴리실리콘층등을 선택적으로 사용할수 있다.Meanwhile, as other embodiments according to the present invention, an oxide film, a tungsten layer, a polysilicon layer, etc. may be selectively used in addition to the aluminum layer shown above as the etching target layer.
이때, 상기 식각타겟트층이 알루미늄막인 경우에 주식각가스로는 클로린계가스를 사용하며, 추가가스로는 BCl3, Ar, N2, HBr 등을 사용할 수 있다.In this case, when the etching target layer is an aluminum film, chlorine-based gas may be used as the stock angle gas, and BCl 3, Ar, N 2, HBr, or the like may be used as the additional gas.
또한, 상기 식각타겟트층이 산화막인 경우에 주식각가스로는 플로린계가스를 사용하며, 추가가스로는 Ar, N2, O2, CO 등을 사용할 수 있다.In addition, when the etching target layer is an oxide film, a florin gas may be used as the stock angle gas, and Ar, N 2, O 2, CO, or the like may be used as the additional gas.
그리고, 상기 식각타겟트층이 텅스텐층인 경우에 주식각가스로는 클로린계가스를 사용하며, 추가가스로는 Ar, N2, SF6 등을 사용할 수 있다.When the etch target layer is a tungsten layer, chlorine-based gas may be used as the stock angle gas, and Ar, N2, SF6, or the like may be used as the additional gas.
게다가, 상기 식각타겟트층이 폴리실리콘층인 경우에 주식각가스로는 클로린계 또는 SF6 가스를 사용하며, 추가가스로는 N2, HBr, O2 등을 사용할 수 있다.In addition, when the etching target layer is a polysilicon layer, chlorine-based or SF6 gas may be used as the stock angle gas, and N2, HBr, O2, or the like may be used as the additional gas.
상기한 바와같이, 본 발명에 따른 반도체소자의 식각방법에 있어서는 다음과 같은 효과가 있다.As described above, the etching method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 종래의 식각단계에 펄스가스공급방식을 이용하여 폴리머 리치 공정구간을 선별적으로 구현, 제어하므로써 식각프로파일을 개선할 수 있다.In the present invention, the etching profile can be improved by selectively implementing and controlling the polymer rich process section using the pulse gas supply method in the conventional etching step.
또한, 종래의 식각단계에 펄스가스공급방식을 이용하여 스퍼터링반응 지배적인 구간을 선별적으로 구현하고 제어하므로써 식각잔류물을 효과적으로 제거할 수 있다.In addition, by using the pulse gas supply method in the conventional etching step, by selectively implementing and controlling the dominant section of the sputtering reaction, the etching residues can be effectively removed.
그리고, 종래의 식각 단계에서는 일정한 비율로 동시에 진행되던 식각과 스퍼터링 반응을 펄스가스공급방식을 이용하여 구분하고, 펄스시간조절로 상대적인 비중을 제어하므로써 이온 충격(bombardment)에 의한 물리적 손상을 감소시킬 수 있다.In the conventional etching step, the etching and the sputtering reaction, which are simultaneously performed at a constant rate, are distinguished by using a pulse gas supply method, and the physical damage due to ion bombardment can be reduced by controlling the relative specific gravity by controlling the pulse time. have.
또한, 본 발명에 있어서는, 효과적인 잔류물의 제어로 과식각타겟트가 감소되므로써 플라즈마 유도(induced) 손상을 감소시킬 수 있다.In addition, in the present invention, the over-etching target is reduced by controlling the effective residue, thereby reducing the plasma induced damage.
그리고, 공정 가스들의 혼합비에 제한을 받지 않으므로 안정적인 공정 마진을 확보할 수 있다.In addition, since the mixing ratio of the process gases is not limited, a stable process margin may be secured.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6893970B2 (en) | 2000-12-15 | 2005-05-17 | Sharp Kabushiki Kaisha | Plasma processing method |
| KR100685123B1 (en) * | 2005-09-29 | 2007-02-22 | 동부일렉트로닉스 주식회사 | Metal line formation method of semiconductor device |
| KR101021906B1 (en) * | 2007-10-15 | 2011-03-18 | 씨케이디 가부시키 가이샤 | Fluid flow distribution and supply uint and flow distribution control program |
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1998
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6893970B2 (en) | 2000-12-15 | 2005-05-17 | Sharp Kabushiki Kaisha | Plasma processing method |
| KR100553299B1 (en) * | 2000-12-15 | 2006-02-20 | 샤프 가부시키가이샤 | Plasma processing method |
| KR100685123B1 (en) * | 2005-09-29 | 2007-02-22 | 동부일렉트로닉스 주식회사 | Metal line formation method of semiconductor device |
| KR101021906B1 (en) * | 2007-10-15 | 2011-03-18 | 씨케이디 가부시키 가이샤 | Fluid flow distribution and supply uint and flow distribution control program |
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