KR20000044315A - Communication system's process board managing multiple number of node board - Google Patents

Abstract

PURPOSE: A communication system's process board that manages multiple number of node board is disclosed to enhance system's function by increasing direct relationship of D-BUS and M-BUS, eliminating process board s communication port overload, and providing communication system and control processor s nodes. CONSTITUTION: A communication system's process board that manages multiple number of node board is composed of D-Bus driver, logic modules, IPC communication driver, M-Bus driver, and node module. D-BUS driver(24) transmits data through D-BUS. All data lines, except for D-BUS control signal, are of in mode and controlled by logic module(22) to be referenced by CPU(20). Logic modules are composed of CPLD and FPGA. CPLD decodes each node s chip selection signal and FPGA generates synchronous signal for node bus turn, provides node bus turn s master clock, inspects incoming dual data, and transmits to CPLD. IPC communication driver(26), composed of RS-422, is connected to node modules(30) of processor s interior and converts data that is outgoing through communication port into parallel data and the data received through data bus into a series data and outputs the data. M-BUS driver(28), composed of RS485, is needed for control and supervision of each node. Nod module(30), composed of 4 nodes, connects CPU s address, allocates 8bit data bus, and connected to FPGA and enables high speed communication between nodes within D bus.

Description

Process board managing multiple node boards in communication system

The present invention relates to a process board for managing a plurality of node boards in a communication system, and more particularly to a process board for managing a plurality of node beams having a node board in a communication system.

Typically, a communication system represents a code division multiple access (CDMA) system, a personal communication services (PCS) system, etc., which has many communication paths. The system has a process board for managing each node. There is a communication path between boards, and there are many packet transmission paths between each path.

1 is a diagram illustrating a connection structure of a plurality of transmission node boards and a process board in a conventional communication system.

The process boards 10 and 12 have a master board and a slave board for redundancy, and control the BUS TURN of the D-BUS (high-speed bus for packet switching) and the master clock related thereto. It is in charge of the transmission, and has been responsible for the node control of the first-nth node boards (101-10n) and the management of their information through the M-BUS (maintenance bus). ASTCLK (Asynchronous Clock) and FRS (Frame Synchronization) are transmitted from the active board among the process boards 10 and 12. ASTCLK is to increase the counter of each node for D-BUS TURN. This signal controls the maximum increase of the bus turn. The M-BUS master clock and transmit data are sent from the processor board where M-BUS is also active, and the node board analyzes commands to inform the control and status of the node. The communication of the process boards 10 and 12 is connected to the nodes of the process board through the communication cable to perform the IPC (Inter Process Communition) communication.

FIG. 2 is a detailed configuration diagram of the process board of FIG. 1.

The D-BUS is made through the D-BUS driver 24. The remaining data lines except for the D-BUS control signals (ASTCLK, FRS) are monitored in the logic module 22 as the IN mode and the CPU 20 It is intended for reference. The communication ports of the process boards 10 and 12 are connected to nodes of the processors 10 and 12 through the IPC communication driver 26 connected by RS-422. The M-BUS is required for control and monitoring of each node through the M-BUS driver 28. This approach adds an OVER LOAD and M-BUS function to monitor the D-BUS on the process boards 10 and 12 and requires a separate port for communication. Utilizes the D-BUS directly on the process boards 10 and 12, and the overload of the port for the node's process boards 10 and 12 and the M-BUS also provide more integration for the process boards 10 and 12. A higher utilization point of view has emerged, and a communication node with a higher structure is directly connected to and controlled by the process boards 10 and 12.

The conventional node management method has a complicated configuration because an overload and M-BUS function for monitoring a D-BUS in a process board should be added and a separate IPC port should be provided for communication.

Accordingly, an object of the present invention is to increase the D-BUS and M-BUS density and eliminate the communication port overload of the process board by placing a node module in a process board that controls several node boards in a communication system, Provides a process board that improves functionality by providing nodes.

A redundant process board for managing a plurality of node boards in the communication system of the present invention for achieving the above object, the CPU for controlling the overall operation to manage the plurality of node boards, and data through the D-BUS It consists of a D-BUS driver, CPLD and FPGA to transmit the signal, decodes the chip select signal of each node in the CPLD, generates a synchronization signal for the node's bus turn in the FPGA, and master clock of the node bus turn. And a logic module that monitors the redundant data received on the D-BUS and transmits fault information to the CPLD, connects an address (5: 0) of the CPU, and allocates an 8-bit data bus. A node module connected to the FPGA of the module for high speed communication between the nodes on the D bus, and connected to the node module, is received through the communication port. It consists of IPC communication driver that converts data to parallel data, converts data received through data bus into serial data, and M-BUS driver that controls and monitors each node through M-BUS. It is done.

1 is a connection structure diagram of a plurality of transmission node board and a process board in a conventional communication system

2 is a detailed configuration diagram of the process board of FIG.

3 is a connection structure diagram of a plurality of transmission node boards and a process board in a communication system according to an embodiment of the present invention;

4 is a detailed configuration diagram of a process board according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

3 is a diagram illustrating a connection structure of a plurality of transmission node boards and a process board in a communication system according to an exemplary embodiment of the present invention.

The process boards 10 and 12 have a master board and a slave board for redundancy, and a bus turn of the D-BUS (high speed bus for packet switching) including two nodes for adding nodes. It is responsible for controlling and transmitting the master clock associated with it, and managing node control and information of the first to nth node boards 101-10n through M-BUS (maintenance bus). It plays a role. ASTCLK (Asyncronous Clock) and FRS (Frame Syncronization) are transmitted from the active board among the process boards 10 and 12. ASTCLK is to increase the counter of each node for D-BUS TURN, and FRS is a node. This signal controls the maximum increase of the bus turn. The M-BUS master clock and transmit data are sent from the processor board where M-BUS is also active, and the node board analyzes commands to inform the control and status of the node. The communication of the process boards 10 and 12 is connected to the nodes of the process board through the communication cable to perform the IPC (Inter Process Communition) communication.

4 is a detailed configuration diagram of a process board according to an embodiment of the present invention.

The D-BUS driver 24 transmits data through the D-BUS. The data lines other than the D-BUS control signals (ASTCLK, FRS) are monitored in the logic module 22 in the IN mode and the CPU (20) is for reference. The logic module 22 is composed of a CPLD and a field programmable gate array (FPGA), and decodes a chip select signal of each node in the CPLD, and the FPGA generates a synchronization signal for the bus turn of the node and It provides a master clock and audits the redundant data received on the D bus to send fault information to the CPLD. The IPC communication driver 26 is composed of RS-422 and is connected to an additional node module 30 in the processors 10 and 12. The IPC communication driver 26 converts data received through the communication port into parallel data and converts the data bus. Converts data received through serial data to output. The M-BUS driver 28 is composed of RS485 and is required for control and monitoring of each node through the M-BUS. The node module 30 is composed of four nodes to connect the addresses (5: 0) of the CPU 20 and to allocate an 8-bit data bus, and is connected to the FPGA of the logic module 22 to connect D between nodes. High speed communication on the bus.

3 to 4, the operation of the preferred embodiment of the present invention will be described in detail.

The D bus driver 24 transmits communication data coming through the D bus to the node module 30 via the FPGA of the logic module 22. The node module 30 checks the received data transmitted and sends the data to the IPC communication driver 28 through the D bus. In this case, the IPC communication driver 26 converts the received data into serial and outputs it to the communication port. In this case, the communication port is dually configured to increase the reliability to select one port from other packet forwarding processors, and at the same time, a dual structure provided by the existing first to nth node boards 101 to 10n in a specific processor packet path. The density is further increased by making all of them single. And the data coming through the communication port is converted into parallel data through the IPC communication driver 26 is applied to the node module 30 is transferred to the D bus and transferred to another node. Here, the utilization of the D bus in the FPGA of the logic module 22 participates in the packet distribution directly as well as the monitoring function. That is, the FPGA of the logic module 22 generates a synchronization signal for the node's buston, provides a master clock of the node buston, monitors the redundant data received on the D bus, and sends fault information to the logic module ( 22) and the CPLD generates a control signal to select only one port. The FPGA acts as an intermediate path for sending and receiving packets to and from the node. The CPU 20 of the process boards 10 and 12 accesses the nodes to manage the nodes and has information about the nodes in the boards. The active process boards are connected to the other process boards and the node boards through the M-bus. Node control and monitoring At this time, the active board transmits and receives data through one serial port of the CPU 20. The standby board always enables another serial port and enables data coming from the active state into A and B port redundancy. Receives and selects only one port from the CPLD and transmits it to the CPU 20. In this case, the control and monitoring of the redundant node of the process board is performed so that the CPU 20 directly accesses the node in the board to transmit and receive data through the M bus, and manages the counterpart board and the node boards in the active board. do.

As such, the process board provides a path for direct packet communication as well as control of the node, thereby improving the function of the system by forming the process board as well as the superstructure communication.

As described above, the present invention adds a node to a process board managing a node in a communication system so that direct packet exchange of the process board can be performed quickly, and provides a node having a duplication port to reduce the load of node board duplication, It has a great effect on improving the board density, and also has the advantage of further improving the usability of the high-speed packet switching bus in the process board.

Claims (2)

In the redundant process board for managing a plurality of node boards in the communication system, CPU for controlling the overall operation to manage the plurality of node boards, D-BUS driver for transmitting data through D-BUS, Comprising a CPLD and an FPGA, decodes the chip select signal of each node in the CPLD, generates a synchronization signal for the bus turn of the node in the FPGA, provides a master clock of the node bus turn, and is received on the D-BUS Logic module that monitors redundant data and transmits fault information to CPLD; A node module which connects an address of the CPU and allocates a data bus of a predetermined bit, and is connected to an FPGA of the logic module to communicate at high speed on a D bus between nodes; An IPC communication driver connected to the node module to convert data received through a communication port into parallel data and convert data received through a data bus into serial data; Process board that manages multiple node boards, comprising M-BUS drivers that control and monitor each node through M-BUS. The method of claim 1, The node module is a process board for managing a plurality of node boards, characterized in that consisting of four node boards.