KR20000043250A - Method for forming fine pattern of semiconductor device - Google Patents

Method for forming fine pattern of semiconductor device Download PDF

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Publication number
KR20000043250A
KR20000043250A KR1019980059600A KR19980059600A KR20000043250A KR 20000043250 A KR20000043250 A KR 20000043250A KR 1019980059600 A KR1019980059600 A KR 1019980059600A KR 19980059600 A KR19980059600 A KR 19980059600A KR 20000043250 A KR20000043250 A KR 20000043250A
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pattern
semiconductor device
pec
forming
density
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KR1019980059600A
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Korean (ko)
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허철
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김영환
현대전자산업 주식회사
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Priority to KR1019980059600A priority Critical patent/KR20000043250A/en
Publication of KR20000043250A publication Critical patent/KR20000043250A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3174—Particle-beam lithography, e.g. electron beam lithography
    • H01J37/3175—Projection methods, i.e. transfer substantially complete pattern to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/30—Electron or ion beam tubes for processing objects
    • H01J2237/317—Processing objects on a microscale
    • H01J2237/3175—Lithography
    • H01J2237/31761—Patterning strategy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/30—Electron or ion beam tubes for processing objects
    • H01J2237/317—Processing objects on a microscale
    • H01J2237/3175—Lithography
    • H01J2237/31769—Proximity effect correction

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  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE: A method for forming a fine pattern of a semiconductor device is to decrease non-uniformity of critical dimension(CD) at a region where the pattern density is low, thereby enhancing the fabrication yield. CONSTITUTION: A method for forming a fine pattern of a semiconductor device comprises the steps of: providing a semiconductor substrate having a photoresist film coated thereon; inserting a virtual PFC(Proximity effect correction) pattern(10) which is not patterned practically but is contained in a dose correction input data at a cell block edge region where the pattern density is relatively low; calculating a correction dose using the inserted virtual PFC pattern; and exposing the coated photoresist film to light with the calculated correction dose. The PFC pattern comprises a line and space pattern.

Description

반도체 소자의 미세패턴 형성방법Method of forming fine pattern of semiconductor device

본 발명은 반도체 소자의 미세패턴 형성방법에 관한 것으로, 특히 패턴 밀도(Pattrern Density)가 낮은 지역에 패턴 형성에 영향을 미치지 않는 크기의 가상 패턴(vertual pattern)을 삽입함에 의해 패턴 밀도차이에 따른 임계크기(Critical Demension; 이하 'CD' 라 함)의 불균일성를 개선하여 반도체 소자의의 제조공정 수율 및 원가절감을 기할 수 있는 반도체 소자의 미세패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a micropattern of a semiconductor device, and in particular, by inserting a vertical pattern having a size that does not affect pattern formation in a region having low pattern density, a threshold according to a pattern density difference The present invention relates to a method of forming a fine pattern of a semiconductor device capable of reducing manufacturing process yield and cost reduction of a semiconductor device by improving non-uniformity of size (hereinafter, referred to as 'CD').

종래의 전자-빔을 이용한 리소그라피 공정에서 PEC(Proximity Effect Correction)을 하는 방법중, 도즈 수정(Dose Correction) 방법은 패턴 밀도에 따라 미리 정해진 도즈 비율로 노광하는 방식을 사용하고 있다.Among the methods for performing PEC (Proximity Effect Correction) in a lithography process using a conventional electron-beam, the dose correction method uses a method of exposing at a predetermined dose ratio according to the pattern density.

그러나 상기의 방법은 2∼3개 정도의 패턴 밀도의 도즈 비율을 기준으로 다른 종류의 패턴 밀도의 도즈 비율을 외삽(extrapolarization)하여 도즈를 수정한다.However, the above method corrects the dose by extrapolating the dose ratios of different types of pattern densities based on the dose ratios of about 2 to 3 pattern densities.

예를 들면, 보통 3개의 패턴 밀도, 즉 20%, 50%, 80% 되는 패턴밀도의 도즈 비율을 기준으로 다른 종류의 패턴 밀도, 예컨데 10%나 5% 정도 되는 패턴밀도의 도즈 비율을 외삽하여 수정된 도즈량을 산출하고, 이를 기준으로 노광을 한다.For example, based on the dose ratios of three pattern densities, that is, 20%, 50%, and 80%, extrapolation of the different types of pattern densities, for example, the pattern rate of about 10% or 5%, The corrected dose is calculated, and exposure is performed based on this.

그러나 상기의 경우 패턴 밀도가 지나치게 낮은 지역, 예를 들면 셀 블록 에지(Cell Block Edge)에 있는 패턴은 미-노광(Under-Expose)됨으로써 균일한 패턴의 CD를 얻기 어려운 문제점이 있다.However, in the above case, a pattern in an area where the pattern density is too low, for example, a cell block edge, is under-exposed, thereby making it difficult to obtain a CD having a uniform pattern.

따라서 본 발명은 상기한 종래의 문제점을 해결하기 위하여 패턴 밀도가 상대적으로 낮은 지역에 실제는 패터닝되지 않지만 도즈 수정 입력 데이터에는 포함되는 가상의 PEC 패턴을 적용함으로써 적정 도즈가 되도록 수정된 상태에서 노광을 실시함으로 패턴의 CD 가 균일하도록 하는 반도체 소자의 미세패턴 형성방법을 제공함에 그 목적이 있다.Therefore, in order to solve the above-mentioned problems, the present invention applies exposure in a state where the pattern is modified to obtain an appropriate dose by applying a virtual PEC pattern that is not actually patterned in the region having a relatively low pattern density but included in the dose correction input data. It is an object of the present invention to provide a method for forming a fine pattern of a semiconductor device, by which the CD of the pattern is uniform.

도 1 은 일반적인 라인 & 스페이스 패턴의 위치에 따른 패턴 밀도를 도시한 도면1 is a diagram showing a pattern density according to the position of a general line & space pattern

도 2 는 본 발명의 방법에 따라 패턴 밀도가 낮은 지역에 가상 PEC 패턴을 삽입한 상태를 도시한 도면2 is a view illustrating a state in which a virtual PEC pattern is inserted in a region having a low pattern density according to the method of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1,7 : 라인(Line) 3,9 : 스페이스(Space)1,7: Line 3,9: Space

5 : 라인 & 스페이스 패턴5: Line & Space Pattern

10 : 가상 PEC 패턴10: virtual PEC pattern

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 미세패턴 형성방법은,Method for forming a fine pattern of a semiconductor device according to the present invention for achieving the above object,

반도체 소자의 전자-빔 리소그라피 공정에 있어서, 패턴의 밀도가 상대적으로 낮은 지역에 실제로는 패터닝되지 않지만 도즈 수정 입력 데이터에는 포함되는 가상의 PEC 패턴을 삽입하여 적정 도즈로 수정한 상태에서 노광을 실시함에 의해 형성되는 균일한 CD의 패턴을 형성하게 하는 것을 특징으로 한다.In the electron-beam lithography process of semiconductor devices, exposure is performed in a state where the pattern density is relatively low but the pattern is corrected to an appropriate dose by inserting a virtual PEC pattern included in the dose correction input data. It is characterized by forming a uniform CD pattern formed by.

이하 첨부된 도면을 참조하여 본 발명의 미세패턴 형성방법의 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of a method for forming a micropattern of the present invention.

도 1 은 일반적인 라인 & 스페이스 패턴의 위치에 따른 패턴 밀도를 도시한 도면이다.1 is a diagram illustrating a pattern density according to the position of a general line & space pattern.

상기 도면에서 원형으로 표시한 각 영역내에서의 패턴 밀도를 계산해 보면, 가운데 영역(27)은 50%, 사방 측면 중앙부(19,21,23,25) 영역에서는 25%, 그리고 각 모서리 영역(11,13,15,17)은 12.5% 가 된다.When calculating the pattern density in each area indicated by the circle in the figure, the center area 27 is 50%, the area at the central side portions 19, 21, 23, 25 is 25%, and each corner area 11 (13,15,17) is 12.5%

그러나 좀 더 자세히 각 원형영역 안으로 들어가면, 셀 븍록(Cell Block)의 최외곽 라인은 밀도를 계산하는 창(window)에 따라 25%보다 더 작아질 수 있다.But in more detail, within each circular region, the outermost line of the cell block can be smaller than 25%, depending on the window for calculating the density.

도 2 는 본 발명의 방법에 따라 패턴 밀도가 낮은 지역에 가상 PEC 패턴을 삽입한 상태를 도시한 도면이다.2 is a view illustrating a state in which a virtual PEC pattern is inserted into a region having a low pattern density according to the method of the present invention.

즉 상기 도 2 에 도시된 바와 같이, 상기 가상 PEC 패턴(10)을 삽입하여 패턴의 밀도가 상대적으로 낮은 지역인 셀 블록 에지 라인이나 이와 유사한 밀도를 갖는 패턴의 CD 균일성을 확보하는 것이다. 즉, 상기 PEC 패턴(10)의 삽입으로 셀 블록 에지 라인의 밀도를 셀 블록 중앙부와 동일하게 조정하거나 또는 셀 블록의 외곽의 모든 부분들이 서로 동일하도록 맞추는 것이다.That is, as shown in FIG. 2, the virtual PEC pattern 10 is inserted to secure CD uniformity of a cell block edge line or a pattern having a similar density, where the density of the pattern is relatively low. That is, the insertion of the PEC pattern 10 adjusts the density of the cell block edge line to be the same as the center of the cell block, or to match all parts of the outer edge of the cell block to be the same.

한편, 상기 도면에서 패턴 밀도를 맞추기 위해서 삽입하는 PEC 패턴(10)은 보정하려는 패턴(5)(도시된 예에서는 라인(1) & 스페이스(3))과 동일한 모양의 패턴으로 하였는데, 그 크기는 실제 웨이퍼상에서 패터닝되지 않을 정도의 미세패턴으로 선택을 한다.Meanwhile, in the drawing, the PEC pattern 10 inserted in order to match the pattern density has a pattern having the same shape as the pattern 5 to be corrected (line 1 & space 3 in the illustrated example). The selection is made with a fine pattern that is not patterned on the actual wafer.

아울러, 상기 PEC 패턴(10)은 보정하려는 패턴과 다른 모양의 패턴으로 형성할 수도 있는데, 이 경우 상기 PEC 패턴(10)은 셀 블록이 라인 & 스페이스 패턴인 경우, 독립 패턴이나 콘택홀 어래이 형태의 패턴으로 하는 것이다.In addition, the PEC pattern 10 may be formed in a pattern having a shape different from that of the pattern to be corrected. In this case, the PEC pattern 10 may have an independent pattern or a contact hole array form when the cell block is a line & space pattern. It's a pattern.

예를 들면, 장비의 최소 그리드(Minimum grid)가 0.01㎛인 경우, 입력 데이터의 넓이 크기(width size)를 0.01㎛으로 하면 밀도 계산에는 첨가되어 패턴 밀도를 셀 블록 영역과 중앙영역을 거의 유사하게 맞출 수 있다. 그러나 해상 한계(Lesolution Limit) 미만의 패턴이기 때문에 실제 웨이퍼상에는 패턴이 없으므로 소자의 특성에 전혀 영향을 주지 않게 된다.For example, if the minimum grid of the equipment is 0.01 μm, the width size of the input data is 0.01 μm, which is added to the density calculation to make the pattern density almost similar to the cell block area and the center area. Can be adjusted. However, since the pattern is less than the resolution limit, there is no pattern on the actual wafer, which does not affect the device characteristics at all.

한편, 상기한 본 발명의 실시예와는 달리, 패턴의 밀도가 낮은 지역에 가상의 PEC 패턴을 삽입하듯이, 지나치게 패턴 밀도가 높은 지역, 예를 들면 패턴 밀도가 90%, 95% 에 이르는 지역에는 역으로 노광 영역의 일부를 삭제함으로써 패턴 밀도를 낮추게 할 수도 있다.On the other hand, unlike the embodiment of the present invention described above, as if the virtual PEC pattern is inserted into the region of low density of the pattern, the region of too high pattern density, for example, the region where the pattern density is 90%, 95% Conversely, the pattern density can be lowered by deleting part of the exposure area.

이상 상술한 바와 같이, 본 발명에 따른 반도체 소자의 미세패턴 형성방법은, 패턴 밀도가 상대적으로 낮은 지역에 실제는 패터닝되지 않지만 도즈 수정 입력 데이터에는 포함되는 가상의 PEC 패턴을 삽입함에 의해, 적정 도즈가 되도록 수정된 상태에서 노광을 실시함으로 패턴 밀도 차이로 미-노광되는 지역에 적정 도즈로 노광되게 하여 형성되는 패턴의 CD 균일성을 확보할 수 있는 장점이 있다.As described above, in the method for forming a micropattern of the semiconductor device according to the present invention, an appropriate dose is obtained by inserting a virtual PEC pattern that is not actually patterned in the region where the pattern density is relatively low but is included in the dose correction input data. The exposure is performed in a modified state so that the CD uniformity of the formed pattern is ensured by exposing to an appropriate dose in an unexposed area due to a difference in pattern density.

Claims (6)

반도체 소자의 전자-빔 리소그라피 공정에 있어서, 패턴의 밀도가 상대적으로 낮은 지역에 실제로는 패터닝되지 않지만 도즈 수정 입력 데이터에는 포함되는 가상의 PEC 패턴을 삽입하여 적정 도즈로 수정한 상태에서 노광을 실시함에 의해 형성되는 균일한 CD의 패턴을 형성하게 하는 반도체 소자의 미세패턴 형성방법.In the electron-beam lithography process of semiconductor devices, exposure is performed in a state where the pattern density is relatively low but the pattern is corrected to an appropriate dose by inserting a virtual PEC pattern included in the dose correction input data. A method of forming a fine pattern of a semiconductor device which makes it possible to form a uniform pattern of CD formed by. 제 1 항에 있어서The method of claim 1 상기 PEC 패턴은 보정하려는 패턴과 동일한 모양의 패턴으로 형성하는 것을 특징으로 하는 반도체 소자의 미세패턴 형성방법.The method of forming a fine pattern of a semiconductor device, characterized in that the PEC pattern is formed in a pattern having the same shape as the pattern to be corrected. 제 1 항 또는 제 2 항에 있어서The method according to claim 1 or 2 상기 PEC 패턴은 라인 & 스페이스 패턴인 것을 특징으로 하는 반도체 소자의 미세패턴 형성방법.The method of forming a fine pattern of a semiconductor device, characterized in that the PEC pattern is a line & space pattern. 제 1 항에 있어서The method of claim 1 상기 PEC 패턴의 삽입으로 셀 블록 에지 라인의 밀도를 셀 블록 중앙부와 동일하게 조정하거나 또는 셀 블록의 외곽의 모든 부분들이 서로 동일하게 맞추는 것을 특징으로 하는 반도체 소자의 미세패턴 형성방법.Inserting the PEC pattern adjusts the density of the cell block edge line to be equal to the center of the cell block, or all parts of the outer periphery of the cell block are equally aligned with each other. 제 1 항에 있어서The method of claim 1 상기 PEC 패턴은 보정하려는 패턴과 다른 모양의 패턴으로 형성하는 것을 특징으로 하는 반도체 소자의 미세패턴 형성방법.The method of forming a fine pattern of a semiconductor device, characterized in that the PEC pattern is formed in a pattern different from the pattern to be corrected. 제 1 항 또는 제 5 항에 있어서The method according to claim 1 or 5 상기 PEC 패턴은 셀 블록이 라인 & 스페이스 패턴인 경우, 독립 패턴이나 콘택홀 어래이 형태의 패턴으로 하는 것을 특징으로 하는 반도체 소자의 미세패턴 형성방법.The method of forming a fine pattern of a semiconductor device, characterized in that the PEC pattern is an independent pattern or a contact hole array pattern when the cell block is a line & space pattern.
KR1019980059600A 1998-12-28 1998-12-28 Method for forming fine pattern of semiconductor device KR20000043250A (en)

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