KR20000041452A - Fabrication method of image sensor having pinned photodiode - Google Patents
Fabrication method of image sensor having pinned photodiode Download PDFInfo
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- 238000005468 ion implantation Methods 0.000 claims description 50
- 125000006850 spacer group Chemical group 0.000 claims description 9
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- 239000010410 layer Substances 0.000 description 46
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- 239000010703 silicon Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
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- 208000013469 light sensitivity Diseases 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
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- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
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Abstract
Description
본 발명은 이미지센서(Image sensor)의 핀드 포토다이오드(Photodiode) 제조방법에 관한 것으로, 특히 씨모스(CMOS) 공정에 의해 제조되는 이미지센서(이하 간단히 "CMOS 이미지센서"라 칭함)의 포토다이오드 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a pinned photodiode of an image sensor, and more particularly, to a photodiode of an image sensor (hereinafter, simply referred to as a "CMOS image sensor") manufactured by a CMOS process. It is about a method.
잘 알려진 바와 같이, 핀드 포토다이오드(Pinned Photodiode)는 CCD(charge coupled device) 이미지센서 또는 CMOS 이미지센서에서 외부로부터의 빛을 감지하여 광전하를 생성 및 집적하는 소자로 사용되며, 기판 내부에서 매립된 PNP(또는 NPN) 접합 구조를 갖고 있어 베리드포토다이오드(Buried Photodiode)라 불리우기도 한다.As is well known, the pinned photodiode is used as a device for generating and accumulating photocharges by sensing light from the outside in a charge coupled device (CCD) image sensor or a CMOS image sensor. It has a PNP (or NPN) junction structure and is also called a buried photodiode.
이러한, 핀드 포토다이오드는 소스/드레인 PN 접합(Junction) 구조나 모스캐패시터 구조 등 다른 구조의 포토다이오드에 비해 여러 가지 장점을 갖고 있으며, 그 중 하나가 공핍층의 깊이를 증가시킬 수 있어 입사된 광자(Photon)를 전자(Electron)로 바꾸어 주는 능력이 우수하다는 것이다(High Quantum Efficiency). 즉, PNP 접합 구조의 핀드 포토다이오드는 N영역이 완전공핍되면서 N영역을 개재하고 있는 두 개의 P영역으로 공핍층이 형성되므로 그 만큼 공핍층 깊이를 증가시켜 광전하생성효율(Quantum Efficiency)을 증가시킬 수 있다. 또한 이에 의해 광감도(Light Sensitivity)가 매우 우수하다.Such a pinned photodiode has various advantages over other photodiodes such as a source / drain PN junction structure or a MOS capacitor structure, and one of them can increase the depth of the depletion layer and thus incident photons. The ability to convert Photon to Electron is excellent (High Quantum Efficiency). In other words, the pinned photodiode of the PNP junction structure has a depletion layer formed by two P regions intervening the N region while the N region is completely depleted, thereby increasing the depth of the depletion layer, thereby increasing the quantum efficiency. You can. In addition, the light sensitivity is very excellent.
도1a에는 통상의 포토다이오드가 도시되어 있다. 도1a를 참조하면, 이미지센서는 고농도의 P+실리콘기판(1) 위에 저농도의 P-실리콘에피층(2)을 키운 에피택셜 웨이퍼를 통상 사용한다. 이러한 P-실리콘에피층(2)에 소자간의 전기적인 절연을 위하여 필드절연막(3)이 형성되고, 게이트산화막(4)과 게이트전극(5)이 형성된다. 이어서, 핀드 포토다이오드를 형성하기 위한 일련의 이온주입 공정이 진행되고, 감지노드(8) 및 그 밖의 트랜지스터들의 소스/드레인 형성을 위한 일련의 이온주입들이 진행된다. 포토다이오드는 P-에피층(2)에 이온주입되어 형성된 N-이온주입층(7)과 피닝층(pinning layer)인 P0이온주입층(6)으로 이루어진다. 이때 5V 또는 3.3V 이하의 전원전압을 사용하는 CMOS 이미지센서에 적용된 핀드 포토다이오드는 전원전압 이하(예컨대 1.2V 내지 2.8V)에서 두 개의 P영역(P-에피층과 P-이온주입층)이 서로 등전위를 가져야만 N영역이 안정적으로 완전공핍되고, 이에 의해 광전하생성효율을 증가시킬 수 있다. 따라서, 이를 위해 N-이온주입층(7)은 필드절연막(3)의 에지에 자신의 에지가 완전히 정렬되어 있지 않고 일부분이 떨어져 형성되게 된다. 이를 도1b를 참조하여 더욱 자세히 설명한다.1A shows a typical photodiode. Referring to FIG. 1A, an image sensor typically uses an epitaxial wafer in which a low concentration P-silicon epi layer 2 is grown on a high concentration P + silicon substrate 1. In the P-silicon epitaxial layer 2, a field insulating film 3 is formed to electrically insulate between devices, and a gate oxide film 4 and a gate electrode 5 are formed. Subsequently, a series of ion implantation processes are performed to form a pinned photodiode, and a series of ion implantation is performed for source / drain formation of the sensing node 8 and other transistors. The photodiode is composed of an N - ion implantation layer 7 formed by ion implantation into the P- epi layer 2 and a P 0 ion implantation layer 6 which is a pinning layer. At this time, the pinned photodiode applied to a CMOS image sensor using a power supply voltage of 5 V or 3.3 V or less has two P regions (P-epi layer and P - ion implantation layer) at a power supply voltage below 1.2V to 2.8V. Only when they have an equipotential to each other, the N region can be stably depleted stably, thereby increasing the photocharge generating efficiency. Therefore, for this purpose, the N − ion implantation layer 7 is formed so that its edge is not completely aligned at the edge of the field insulating film 3 and is partially separated. This will be described in more detail with reference to FIG. 1B.
도1b는 N-이온주입층(7)과 P0이온주입층(6)을 각각 형성하고자 이온주입을 실시할 때 사용되는 마스크를 나타내는 평면도이다. 이를 참조하면, 통상 N-이온주입층(7) 형성을 위한 이온주입이 먼저 실시되는데 이때의 마스크(110)는 포토다이오드가 형성될 활성영역(100)을 노출시키되 일부 모서리(130)를 덮도록 형성된다. 그리고, P-이온주입층(105)을 형성하기 위한 이온주입이 실시되는데 이때의 마스크(120)는 활성영역(100)을 완전히 오픈시키도록 형성된다. 따라서, 도1a에 도시된 바와 같이 P-이온주입층(105)은 N-이온주입층(105)에 막히지 않고 그 하부의 P-에피층(101)과 전기적으로 충분히 연결되게 된다.FIG. 1B is a plan view showing a mask used when ion implantation is performed to form an N − ion implantation layer 7 and a P 0 ion implantation layer 6, respectively. Referring to this, in general, ion implantation for forming the N − ion implantation layer 7 is performed first. The mask 110 exposes the active region 100 in which the photodiode is to be formed, but covers some edges 130. Is formed. In addition, ion implantation is performed to form the P − ion implantation layer 105. In this case, the mask 120 is formed to completely open the active region 100. Therefore, as shown in FIG. 1A, the P − ion implantation layer 105 is not sufficiently blocked by the N − ion implantation layer 105, and is sufficiently electrically connected to the P- epi layer 101 below.
그러나, 상기한 바와 같은 종래기술에서, 해상도와 밀접한 관계가 있는 포토다이오우드 부분(6,7)은 필드산화막(3)과 트랜스퍼트랜지스터의 게이트전극(5) 사이에서 노출된 P-실리콘에피층(2) 내에 불순물 이온주입에 의하여 형성되어 있기 때문에, 집적도를 떨어뜨리지 않으면서 포토다이오우드의 단위 면적을 증대시킨다는 것은 불가능하였다. 이와 같이 포토다이오우드의 단위 면적을 디자인 룰 이상으로 증대시킬 수 없기 때문에, CMOS 이미지센서의 디자인 룰이 0.35㎛ 이하가 되었을 때에는 광신호(photo signal)가 작아지고 이로 인하여 잡음(noise)이 많아져서, 결국 이미지 센서로서의 기능이 저하되는 치명적인 문제점이 있었다.However, in the prior art as described above, the photodiode portions 6 and 7 which are closely related to the resolution have the P-silicon epitaxial layer 2 exposed between the field oxide film 3 and the gate electrode 5 of the transfer transistor. Since it is formed by impurity ion implantation in the cavities, it was not possible to increase the unit area of the photodiode without reducing the degree of integration. Since the unit area of the photodiode cannot be increased above the design rule, when the design rule of the CMOS image sensor is 0.35 μm or less, the photo signal becomes small, thereby increasing the noise. As a result, there was a fatal problem that the function as the image sensor is degraded.
또한, 종래에는 핀드 포토다이오드의 N-이온주입층(7)과 P0이온주입층(6)을 각각 형성한 다음, 감지노드 및 소스/드레인 형성을 위한 일련의 이온주입들이 진행되고, 또한 소스/드레인 이온주입된 도펀트들의 확산을 위한 열공정이 진행되므로 인해서, P0이온주입층(6)의 도펀트들도 역시 확산되어 트랜스퍼트랜지스터의 채널 지역에 전위장벽을 형성하게 되는 문제점이 있다. 트랜스트랜지스터의 채널지역에 형성되는 전위장벽은 광전하가 감지노드로 전달되는 것을 억제하여, 광전달효율을 떨어뜨리게 된다. 이 역시 이미지센서의 기능을 저하시키는 요인으로 작용하게 된다.In addition, conventionally, after forming the N - ion implantation layer 7 and the P 0 ion implantation layer 6 of the pinned photodiode, respectively, a series of ion implantation for the sensing node and the source / drain formation are performed. Due to the thermal process for diffusion of the dopants implanted / drained, dopants of the P 0 ion implantation layer 6 also diffuse, forming a potential barrier in the channel region of the transfer transistor. The potential barrier formed in the channel region of the transtransistor suppresses the transfer of photocharges to the sensing node, thereby reducing the light transmission efficiency. This also acts as a factor degrading the function of the image sensor.
본 발명은 상기 문제점을 해결하기 위하여 안출된 것으로써, 핀드 포토다이오드를 갖는 이미지센서를 제조함에 있어, 제한된 면적하에서보다 넓은 단위 면적을 갖는 핀드 포토다이오드를 형성하여 고집적 이미지센서의 광감도를 향상시키기 위한 이미지센서 제조방법을 제공하는데 목적이 있다.The present invention has been made to solve the above problems, in manufacturing an image sensor having a pinned photodiode, to form a pinned photodiode having a wider unit area than a limited area to improve the light sensitivity of the highly integrated image sensor An object of the present invention is to provide a method for manufacturing an image sensor.
본 발명의 다른 목적은 핀드 포토다이오드를 갖는 이미지센서를 제조함에 있어, 핀드 포토다이오드의 피닝층(pinning layer) 형성을 위한 이온주입을 되도록 후속 열공정 이후에 형성하므로써 트랜스트랜지스터의 채널지역에 형성되는 전위장벽을 억제하는 이미지센서 제조방법을 제공하는데 그 목적이 있다.It is another object of the present invention to manufacture an image sensor having a pinned photodiode, which is formed in a channel region of a transtransistor by being formed after a subsequent thermal process such that ion implantation for forming a pinning layer of the pinned photodiode is formed. It is an object of the present invention to provide a method for manufacturing an image sensor that suppresses a potential barrier.
도1a는 통상의 핀드 포토다이오드 구조를 나타내는 단면도,1A is a cross-sectional view showing a conventional pinned photodiode structure;
도1b는 핀드 포토다이오드 형성을 위한 각 이온주입마스크 형상을 나타내는 평면도,1B is a plan view showing the shape of each ion implantation mask for forming a pinned photodiode;
도2a 내지 도2e는 본 발명의 일실시예에 따른 이미지센서 제조 공정을 나타내는 단면도.2A to 2E are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘기판 12 : P-실리콘에피층11 silicon substrate 12 P-silicon epilayer
13 : 필드산화막 14 : 게이트산화막13 field oxide film 14 gate oxide film
15 : 게이트전극 16 : N-이온주입층15 gate electrode 16 N - ion implantation layer
18 : 산화막스페이서 19 : 감지노드18: oxide spacer 19: detection node
20 : 마스크패턴 21 : P0이온주입층20: mask pattern 21: P 0 ion implantation layer
상기 목적을 달성하기 위한 본 발명은, 단위면적이 증대된 핀드 포토다이오드를 형성하기 위한 이미지센서 제조방법에 있어서, 제1도전형의 반도체층을 준비하는 제1단계; 소자분리를 위한 필드절연막을 형성하고 상기 반도체층 상에 CMOS 소자의 게이트전극을 형성하는 제2단계; 상기 핀드 포토다이오드가 형성될 영역의 상기 반도체층 내에 제2도전형의 제1이온주입층을 형성하는 제3단계; 상기 제1이온주입층 상부와 상기 필드절연막의 에지가 노출된 마스크패턴을 형성하는 제4단계; 상기 마스크패턴을 식각장벽으로하여 상기 필드절연막의 에지를 식각하는 제5단계; 및 상기 마스크패턴을 이온주입장벽으로하여 상기 반도체층 표면 하부에 제2도전형의 제2이온주입층을 형성하는 제6단계를 포함하여 이루어짐을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing an image sensor for forming a pinned photodiode having an increased unit area, the method comprising: preparing a first conductive semiconductor layer; Forming a field insulating film for device isolation and forming a gate electrode of a CMOS device on the semiconductor layer; A third step of forming a first ion implantation layer of a second conductivity type in the semiconductor layer in a region where the pinned photodiode is to be formed; A fourth step of forming a mask pattern in which an upper portion of the first ion implantation layer and an edge of the field insulating layer are exposed; Etching the edge of the field insulating layer using the mask pattern as an etch barrier; And a sixth step of forming a second ion implantation layer of a second conductivity type under the surface of the semiconductor layer using the mask pattern as an ion implantation barrier.
이와 같이, 본 발명은 필드절연막의 에지를 피닝층인 제2이온주입층을 형성하기 전에 식각해내므로써 핀드 포토다이오드의 단위면적을 증대시키는데 그 특징을 갖는다.As described above, the present invention is characterized by increasing the unit area of the pinned photodiode by etching the edge of the field insulating film before forming the second ion implantation layer as the pinning layer.
또한 본 발명은 상기 제3단계 후, 상기 CMOS 소자의 소스/드레인을 형성하고, 상기 제4단계 이후를 수행하는 것을 특징으로 하는바, 이에 의해 트랜스퍼트랜지스터의 채널에 전위장벽이 형성되는 것을 예방할 수 있다.In addition, the present invention is characterized in that the source / drain of the CMOS device is formed after the third step, and after the fourth step, the potential barrier is prevented from being formed in the channel of the transfer transistor. have.
또한 본 발명은 상기 게이트전극의 측벽에 절연막스페이서를 형성하고, 상기 마스크패턴이 상기 게이트전극을 덮으면서 상기 절연막스페이서의 일부를 노출시키도록 형성함을 특징으로하며, 이에 의해 역시 트랜스퍼트랜지스터의 채널에 전위장벽이 형성되는 것을 예방할 수 있다.In addition, the present invention is characterized in that the insulating film spacer is formed on the sidewall of the gate electrode, and the mask pattern is formed so as to expose a portion of the insulating film spacer while covering the gate electrode, thereby also to the channel of the transfer transistor The potential barrier can be prevented from forming.
또한, 본 발명은 상기 절연막스페이서의 일부를 노출시키도록 마스크패턴을 형성하기 때문에 제2이온주입층의 에지가 게이트전극 일측에 얼라인되지 않아 광전달효율이 떨어질 수 있는바, 이를 방지하기 위하여, 상기 제6단계 후, 상기 게이트전극의 일측에지에 상기 제2이온주입층의 에지가 얼라인되도록 상기 제2이온주입층의 불순물을 확산시키는 제8단계를 더 포함하여 이루어진 것을 특징으로 한다.In addition, in the present invention, since the mask pattern is formed to expose a portion of the insulating film spacer, the edge of the second ion implantation layer may not be aligned on one side of the gate electrode, thereby reducing the light transmission efficiency. And after the sixth step, an eighth step of diffusing impurities of the second ion implantation layer to align the edges of the second ion implantation layer to one edge of the gate electrode.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
먼저, 도2a에 도시된 바와 같이, 약 15 내지 25 Ωcm의 비저항을 갖는 P-실리콘에피층(12)이 성장된 실리콘기판(11)을 준비한다. 공지의 방법으로 붕소 또는 BF2이온주입에 의한 소정의 채널스톱 영역을 갖는 필드산화막(13)을 LOCOS(local oxidation of silicon) 방식으로 형성하고, 게이트산화막(14) 및 게이트전극(15)을 형성한다. 게이트전극(15)의 상부에는 게이트전극 패터닝시 난방사방지를 위한 무반사코팅층이 형성될 수 있으며, 도면에 도시된 게이트전극(15)은 트랜스퍼트랜지스터의 게이트전극이며, 그 외에도 본 발명에서는 언급하지 않았지만, 리셋 게이트 및 드라이브 게이트, 셀렉트 게이트 등이 형성된다. 게이트전극(15)용 도전막으로는 도핑된 폴리실리콘막 또는 여러 종류의 실리사이드막(예를 들면, 텅스텐 실리사이드, 티타늄 실리사이드, 탄탈륨 실리사이드, 몰리브데늄 실리사이드 등) 중에서 하나 또는 복합막을 사용할 수 있다.First, as shown in FIG. 2A, a silicon substrate 11 having a P-silicon epitaxial layer 12 having a specific resistance of about 15 to 25 Ωcm is prepared. A field oxide film 13 having a predetermined channel stop region by boron or BF 2 ion implantation is formed by a known method in a local oxidation of silicon (LOCOS) manner to form a gate oxide film 14 and a gate electrode 15. do. An anti-reflective coating layer may be formed on the gate electrode 15 to prevent heating radiation during patterning of the gate electrode. The gate electrode 15 shown in the drawing may be a gate electrode of a transfer transistor. Reset gates, drive gates, select gates, and the like are formed. As the conductive film for the gate electrode 15, one of a doped polysilicon film or various kinds of silicide films (for example, tungsten silicide, titanium silicide, tantalum silicide, molybdenum silicide, etc.) may be used.
그 다음에, 도2b에 도시된 바와 같이, 이온주입마스크를 형성한 다음 포토다이오우드가 형성될 영역에 P(인) 불순물을 약 140 내지 180 KeV 범위의 에너지 및 1.5E12 내지 2.0E12 범위의 도즈(dose) 조건으로 이온주입하여 N-이온주입층(16)을 형성한다.Then, as shown in Fig. 2B, after forming the ion implantation mask, the P (phosphorus) impurity is formed in the region where the photodiode is to be formed, and the energy in the range of about 140 to 180 KeV and the dose ion implantation under a dose) condition to form an N − ion implantation layer 16.
이어서, CMOS 트랜지스터들의 소스/드레인 형성을 위한 일련의 이온주입을 실시하는 바, 먼저 저농도 이온주입을 실시하고 게이트전극(15)의 측벽에 산화막스페이서(18)를 형성한 다음, 고농도 이온주입을 실시한다. 트랜스퍼트랜지스터의 감지노드(19)에는 고농도 이온주입만이 진행되도록 하여 트랜스퍼트랜지스터의 게이트전극(15)과 감지노드(19) 간의 오버랩 커패시턴스를 감소시킨다.Subsequently, a series of ion implantation is performed for source / drain formation of the CMOS transistors. First, a low concentration ion implantation is performed, an oxide film spacer 18 is formed on the sidewall of the gate electrode 15, and then a high concentration ion implantation is performed. do. Only a high concentration of ion implantation proceeds to the sensing node 19 of the transfer transistor, thereby reducing the overlap capacitance between the gate electrode 15 and the sensing node 19 of the transfer transistor.
그 다음에, 도2c에 도시된 바와 같이, 포토다이오우드가 형성될 활성영역이 노출되도록 마스크패턴(20)을 형성한다. 이때, 마스크패턴은 필드산화막(13)의 버즈비크 부위가 완전히 노출되도록 하고, 포토다이오우드 영역에 접한 산화막스페이서(18)의 일측부가 노출되도록 한다.Next, as shown in FIG. 2C, the mask pattern 20 is formed to expose the active region where the photodiode is to be formed. In this case, the mask pattern allows the Buzzbeek portion of the field oxide film 13 to be completely exposed, and one side of the oxide spacer 18 in contact with the photodiode region is exposed.
이어서, 도2d에 도시된 바와 같이, 비등방성 식각법으로 노출된 필드산화막(13) 및 산화막스페이서(18)를 식각함으로써, 포토다이오우드 영역이 확대되도록 한 다음에, BF2불순물을 약 15 내지 30 KeV 범위의 에너지 및 1. 5E12 내지 3.5E12 범위의 도즈(dose) 조건으로 이온주입하여 P0이온주입층(21)을 형성한다.Subsequently, as shown in FIG. 2D, by etching the field oxide film 13 and the oxide film spacer 18 exposed by anisotropic etching, the photodiode region is enlarged, and then BF 2 impurities are about 15 to 30. the KeV energy range and 1. ion implantation with a dose (dose) condition of 5E12 to 3.5E12 range to form the P 0 ion implanted layer 21.
계속해서, 도2e에 도시된 바와 같이, 상기 마스크패턴(20)을 제거한 다음, 약 900℃에서 20분 동안 질소 분위기에 열처리함으로써, 상기 P0이온주입층(21)이 게이트 전극(15)과 중첩(overlap)되도록 한다.Subsequently, as shown in FIG. 2E, the mask pattern 20 is removed, and then heat-treated in a nitrogen atmosphere at about 900 ° C. for 20 minutes, whereby the P 0 ion implantation layer 21 is connected to the gate electrode 15. Let it overlap.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
이상에서와 같이, 본 실시예에 의하면, 소자 격리 산화막의 버즈비크를 제거함으로써, 포토다이오우드의 단위 면적을 증대시킴으로써, CMOS 이미지센서의 해상도를 향상케 하는 이점이 있으며, 소오스/드레인 전극을 형성한 이후에 P0 불순물층을 형성함으로써 상대적으로 얕은 접합을 형성할 수 있는 또 다른 이점이 있다.As described above, according to the present embodiment, there is an advantage in that the resolution of the CMOS image sensor is improved by removing the Buzzbee of the element isolation oxide film and increasing the unit area of the photodiode, thereby forming source / drain electrodes. Thereafter, there is another advantage of forming a relatively shallow junction by forming a P0 impurity layer.
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