KR20000040326A - Cascode structure low noise amplifier circuit - Google Patents

Abstract

PURPOSE: A low noise amplifier circuit of a cascode structure of which a minimum noise figure is more reduced by setting transistors of a cascode structure amplifier to allow the transistors to have area rates different from one another is provided. CONSTITUTION: A cascode structure low noise amplifier circuit includes a first transistor(T1) and a second transistor(T2) which are connected with the first transistor(T1) in a cascode structure. The high-frequency signal of which frequency is 1/5-1/10 of an unit current gain frequency is inputted to the cascode structure low noise amplifier circuit. The cascode structure low noise amplifier circuit has an area rate between the emitter areas(Aera_CB and Aera_CE) of the first and second transistors(T1 and T2) as follows: Aera_CB = Aera_CE * Multi(0 < Multi <1 or Multi = 1). According to the cascode structure low noise amplifier circuit, by setting the areas of the first and second transistors to be different from each other, a gain characteristic of cascode structure low noise amplifier circuit is improved.

Description

Low-noise amplifier circuit with cascode structure

The present invention relates to an amplifier composed of a transistor, and more particularly to an amplifier composed of a cascode structure.

In general, a low-noise amplifier (LNA) in a wireless communication system is the most important block among the building blocks. Since the block signal received at the antenna and provided from the antenna is input to the low noise amplifier, the building block is used to determine the noise figure and the input voltage standing-wave rate (VSWR) of the entire system.

In addition, the low noise amplifier amplifies the size of the block signal while including only the minimum noise of the signal received from the antenna. In implementing the low noise amplifier, there is a method using only one transistor and a method using two transistors.

1 is a view showing a conventional low noise amplifier composed of one transistor. In the figure, the low noise amplifier is a transistor T10, parasitic inductors L10, L11 and L12 parasitic respectively at the emitter stage, the base stage and the collector stage of the transistor T10, and the base stage and the output stage which are input stages. It consists of the bias capacitors C10 and C11 provided in the collector stage, respectively.

2 is a diagram illustrating a low noise amplifier having a general cascode structure. In the figure, the low noise amplifier includes parasitic inductors L1 and L2 that are parasitic to the cascode-connected transistors T1 and T2, the base terminal of the second transistor T2 and the collector terminal of the first transistor T1, respectively. ) And bias capacitors C1 and C2 provided at the base terminal of the second transistor T2 as an input terminal and the collector terminal of the first transistor T1 as an output terminal, respectively. In the figure, reference numeral V _B denotes a bias voltage of the base.

Here, the sizes of the first and second transistors T1 and T2, that is, the size or area of the emitter stage, are configured to be the same size. Meanwhile, a low noise amplifier cascaded with two transistors shown in FIG. 2 is generally applied to a wireless communication system, and is particularly used when integrating a low noise amplifier onto a Si or GaAs substrate using integrated circuit technology.

On the other hand, when the low noise amplifier of the cascode structure is compared with the low noise amplifier of the other structure, the gain is considerably high and the input / output isolation characteristic is excellent while consuming the same power. This effect is based on A Comparative Study on the Various Monolithic Low Noise Amplifier Circuit Topologies for RF and Microwave Applications, by Beom Kyu Ko and Kwyro, published August 1996, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.31, NO.8. Lee and A New Simultaneous Noise and Input Power Matching Technique for Monolithic LNA's Using Cascode Feedback, by Beom Kyu Ko and Kwyro Lee, published in September 1997, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL.45, NO.9. It is.

That is, the input / output isolation characteristic of the cascode structure is that a small input signal is inputted from the base terminal of the second transistor T2, which is an input terminal, and a large output signal amplified from the collector terminal of the first transistor T1, which is an output terminal, is output. If the output signal is input back to the input terminal via the bias capacitor C2 of the collector stage, the signal is reduced at the collector stage of the second transistor T2, so that the output signal from the output stage is the second input terminal. The base end of the transistor T2 is not affected, resulting in excellent input / output isolation characteristics.

However, the low noise amplifier of the cascode structure using the two transistors has a problem that the minimum noise figure (NFmin) is increased by about 0.1 to 0.2 dB compared to the low noise amplifier using one transistor.

Accordingly, the present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a low-noise amplifier circuit having a cascode structure in which the area ratio of each transistor is set differently in the cascode structure amplifier to further lower the minimum noise figure of the amplifier. There is this.

1 is a view showing a conventional low noise amplifier composed of one transistor;

2 is a diagram illustrating a low noise amplifier having a general cascode structure;

3 is a graph showing a minimum noise figure [NFmin] for a multi-value in the low noise amplifier circuit of the cascode structure of FIG. 2 to which the present invention is applied;

4 is a view showing a low noise amplifying circuit of a cascode structure according to the present invention to which a parasitic inductor by a package lead frame is added;

FIG. 5 is a graph showing a minimum noise figure [NFmin] for a multi-value when the parasitic inductance is 0.4 nH in the low noise amplifier circuit of the cascode structure shown in FIG. 4;

FIG. 6 is a graph showing a minimum noise figure [NFmin] for a multi-value when the parasitic inductance is 0.8 nH in the low noise amplifier circuit of the cascode structure shown in FIG. 4;

FIG. 7 is a graph showing a minimum noise figure [NFmin] with respect to a multi-value when the parasitic inductance is 1.2 nH in the low noise amplifier circuit of the cascode structure shown in FIG. 4.

* Description of the symbols for the main parts of the drawings *

T1 to T4: transistors L1 to L5: inductors

C1 to C4: Capacitor

In the low noise amplifier circuit of the cascode structure according to the present invention for achieving the above object, a high frequency input signal in the range of 1/5 to 1/10 of a single current gain frequency is input and the first and second transistors are cascoded In the low noise amplifier, the area ratio between the area Aera_CB of the emitter terminal of the first transistor and the area Aera_CE of the emitter terminal of the second transistor is defined as the relationship of Aera_CB = Aera_CE × Multi (0 <Multi ≤ 1). It is characterized by.

According to the present invention configured as described above, the area ratio between the area of the emitter terminal of the first transistor and the area of the emitter terminal of the second transistor is set differently so that 0.2 to 0.4 dB lower than the minimum noise figure of the low voltage amplifier of the general cascode structure. Noise figure can be obtained.

Hereinafter, a low noise amplifier circuit having a cascode structure according to the present invention will be described in detail with reference to the accompanying drawings.

Meanwhile, the low noise amplifier of the general cascode structure has a minimum noise figure (NFmin) of 0.1 to 0.2 dB higher than the low noise amplifier composed of one transistor shown in FIG. A low noise amplifier circuit is provided.

Since the circuit configuration of the low noise amplifier of the cascode structure shown in FIG. 2 is the same as the circuit configuration of the present invention, a detailed description thereof will be omitted.

First, although the size of the transistors T1 and T2 of the low noise amplifier of the general cascode structure, that is, the size or the area of the emitter stage are the same, the area of the transistor in the low noise amplifier circuit of the cascode structure according to the present invention is Each will be configured differently.

2 is applied as a low noise amplifying circuit having a cascode structure according to the present invention, and a description thereof is as follows.

First, assuming that the emitter end area of the first transistor T1 is Aera_CB and the emitter end area of the second transistor T2 is Aera_CE, the relationship Aera_CB = Aera_CE × Multi is established. Here, the multi is in a range of 0 &lt; Multi &lt;

The minimum noise figure NFmin means the lowest noise figure that the low noise amplifier can output, and the lower the figure, the better the performance.

1/5 to _{the; (unity current gain frequency f T} ) Then, the cascode structure, a low noise amplifier circuit according to the present invention includes a single current-gain frequency described by way of example a high-frequency signal to be inputted from the input terminal of 2GHz, but not limited to The frequency may be in the range of 1/10. Here, the single current gain frequency f _T means the maximum frequency when the current gain is one.

Subsequently, while changing the multi-value, look at the change in the minimum noise index (NFmin) of the low noise amplifier circuit of the cascode structure according to the present invention.

FIG. 3 is a graph showing a minimum noise figure [NFmin] with respect to a multi-value in the low noise amplifier circuit of the cascode structure of FIG. 2 to which the present invention is applied. As shown, the minimum noise figure m2 when the input frequency is 2 GHz and the multi-value is 1.0 (typical case) is 1.785743, and the minimum noise figure m1 when the multi-value is 0.6 is 1.781254. As a result, it can be seen that the minimum noise figure does not improve even when the multi-value is changed in the above case.

On the other hand, when the low noise amplifier having the cascode structure shown in FIG. 2 is manufactured using semiconductor integrated technology, parasitic inductors due to package lead frames are generated.

Accordingly, FIG. 4 is a diagram illustrating a low noise amplifier circuit having a cascode structure according to the present invention to which a parasitic inductor by a package lead frame is added. In the figure, the low noise amplifier includes parasitic inductors L3 and L4, each of which is parasitic to the cascode-connected transistors T3 and T4, the base end of the fourth transistor T4 and the collector end of the third transistor T3, respectively. ), The bias capacitors C3 and C4 respectively provided at the base terminal of the fourth transistor T4, which is an input terminal, and the collector terminal of the third transistor T3, which is an output terminal, and the emitter terminal of the fourth transistor T4. It consists of the parasitic inductor L5 by the package lead frame shown. In the figure, reference numeral V _B1 denotes a bias voltage of the base.

Here, the inductance of the parasitic inductor L5 due to the package lead frame is about 0.4 to 2.0 nH, which has a great influence on the high frequency amplifier of 1 GHz or more.

FIG. 5 is a graph showing the minimum noise figure [NFmin] with respect to the multi-value when the parasitic inductance is 0.4 nH in the low noise amplifier circuit of the cascode structure shown in FIG. The graph is a graph simulated with the inductance of the parasitic inductor by the package lead frame, for example, about 0.4 nH. As shown in this graph, the minimum noise figure m1 when the multi-value is 1.0 at an input frequency of 2 GHz is 1.992949, and the minimum noise figure m2 when the multi-value is 0.4 is 1.882616. As shown in the graph, when the multi-value decreases from 1 to 0.6, the minimum noise figure decreases by 0.1 dB.

FIG. 6 is a graph showing a minimum noise figure [NFmin] with respect to a multi-value when the parasitic inductance is 0.8 nH in the low noise amplifier circuit of the cascode structure shown in FIG. 4. The graph is a graph simulated with the inductance of the parasitic inductor by the package lead frame, for example, about 0.8 nH. As shown in this graph, the minimum noise figure m2 when the multi-value is 1.0 at an input frequency of 2 GHz is 2.314413, and the minimum noise figure m1 when the multi-value is 0.3 is 2.055181. As shown in the graph, when the multi-value decreases from 1 to 0.3, the minimum noise figure is reduced by 0.25 dB.

FIG. 7 is a graph showing a minimum noise figure [NFmin] with respect to a multi-value when the parasitic inductance is 1.2 nH in the low noise amplifier circuit of the cascode structure shown in FIG. 4. The graph simulates the inductance of the parasitic inductor by the package lead frame, for example, about 1.2 nH. As shown in this graph, the minimum noise figure m1 when the multi-value is 1.0 at an input frequency of 2 GHz is 2.634802, and the minimum noise figure m2 when the multi-value is 0.3 is 2.253899. As shown in the graph, when the multi-value decreases from 1 to 0.3, the minimum noise figure is reduced by 0.4 dB.

That is, in the cascode structure low noise amplifier circuit having parasitic inductance of about 0.8 to 1.2 nH, the area (Area_CB) of the emitter terminal of the first transistor is 0.3 to 0.4 compared to the area of the emitter terminal of the second transistor. By designing as small as twice, the minimum noise figure can be reduced by 0.2 to 0.4 dB.

On the other hand, the present invention is not limited to the above-described specific embodiments and can be carried out by variously modified and modified within the scope and spirit of the present application.

In the low noise amplifier circuit of the cascode structure according to the present invention, the area ratio between the area of the emitter terminal of the first transistor and the area of the emitter terminal of the second transistor is set differently so that the characteristics of the low noise amplifier of the general cascode structure, In other words, it consumes the same power, has a high gain, excellent input / output isolation characteristics, and a noise figure of 0.2 to 0.4 dB lower than that of a low voltage amplifier having a general cascode structure.

Claims (7)

A low noise amplifier having a high frequency input signal in a range of 1/5 to 1/10 of a single current gain frequency and having cascoded first and second transistors, The area ratio between the area Aera_CB of the emitter terminal of the first transistor and the area Aera_CE of the emitter terminal of the second transistor is defined by the relationship of Aera_CB = Aera_CE × Multi (0 <Multi ≤ 1). Low noise amplifier circuit with cascode structure. The method of claim 1, The area of the emitter stage of the first and second transistors is a low noise amplifier circuit of the cascode structure characterized in that the width and length are changed. The method of claim 1, The low noise of the cascode structure is set to 0.4 when the inductance of the parasitic inductor caused by the package lead frame generated in the integrated circuit fabrication at the emitter of the second transistor is 0.4 nH. Amplification circuit. The method of claim 3, wherein And a multi-value is set to 0.3 when the inductance of the parasitic inductor is 0.8nH or 1.2nH. The method of claim 1, The area ratio of the emitter stage of the first and second transistors is applied to the transistor of the hybrid type or integrated circuit type low noise amplifier circuit characterized in that the cascode structure. The method according to claim 1 or 5, And the first and second transistors are bipolar transistors, field effect transistors (FETs), and high electron mobility transistors (HEMTs). The method of claim 1, And the area Aera_CB of the emitter terminal of the first transistor is set to be 0.3 to 0.4 times smaller than the area Aera_CE of the emitter terminal of the second transistor.