KR20000038413A - Bga device and manufacturing method thereof - Google Patents

Bga device and manufacturing method thereof Download PDF

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Publication number
KR20000038413A
KR20000038413A KR1019980053410A KR19980053410A KR20000038413A KR 20000038413 A KR20000038413 A KR 20000038413A KR 1019980053410 A KR1019980053410 A KR 1019980053410A KR 19980053410 A KR19980053410 A KR 19980053410A KR 20000038413 A KR20000038413 A KR 20000038413A
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South Korea
Prior art keywords
wafer
chip pad
chip
pads
support plate
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KR1019980053410A
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Korean (ko)
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유재봉
오선주
김희석
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윤종용
삼성전자 주식회사
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Priority to KR1019980053410A priority Critical patent/KR20000038413A/en
Publication of KR20000038413A publication Critical patent/KR20000038413A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Abstract

PURPOSE: A ball grid array(BGA) package is provided to decrease a thickness of the package, to simplify a manufacture process, and to improve heat dissipation. CONSTITUTION: A plurality of BGA packages are made on a wafer(21). The wafer(21) includes a plurality of semiconductor devices formed therein and a plurality of chip pads(23) formed thereon. A back of the wafer(21) is lapped by a grinder to thin the wafer(21). Next, while a circuit substrate(27) is adhered to a front of the wafer(21) by an adhesive(29), a backing plate(31) is adhered to the back of the wafer(21) by another adhesive(33). The circuit substrate(27) includes contact pads thereon, each of which is correspondingly faced and joined to each chip pad(23). Moreover, the backing plate(31) as a heat-dissipating medium includes a plurality of slits corresponding to scribe lines of the wafer(21). A plurality of solder balls(37) are then mounted on ball pads of the circuit substrate(27), the ball pads being respectively connected with the contact pads. The wafer(21) and the circuit substrate(27) are finally cut along the slits of the backing plate(31), so that the individual BGA packages are obtained.

Description

ＢＧＡ소자와 그 제조방법(Slim ball grid array device and manufacturing method thereof)Slim ball grid array device and manufacturing method

본 발명은 BGA IC소자에 관한 것이다. 보다 구체적으로 본 발명은 웨이퍼 전체로부터 시작하여 BGA 소자를 제작하고 수지몰딩공정이 생략된 BGA소자 제조방법과 이렇게 제조된 BGA소자에 관한 것이다.The present invention relates to a BGA IC device. More specifically, the present invention relates to a BGA device manufacturing method which manufactures a BGA device starting from the entire wafer and omits the resin molding process, and a BGA device manufactured as described above.

반도체 소자는 집적도가 증가하면서 점점 더 많은 수의 입출력 핀을 요구하기 때문에 소자의 크기를 소형화하는 것이 중요하다. 그러나 소형의 반도체 소자가 많은 입출력 핀을 가지게 되면 반도체 패키지의 리드 피치가 너무 작아져서 패키지의 리드가 외부의 충격에 약해지고, 전기적인 기생변수로 인한 칩의 성능 저하도 발생하며, 패키지의 취급에 세심한 주의가 필요하다는 문제점이 생긴다. 볼그리드어레이(Ball Grid Array; 이하 'BGA')패키지는 핀그리드어레이(PGA; Pin Grid Array)에서 리드의 길이가 길기 때문에 발생할 수 있는 유도성 성분에 의한 부정적 요소를 배제하면서 입출력 핀의 효율성이라는 장점을 취할 수 있는 새로운 형태의 패키지로서 많은 수의 리드가 필요한 소자에 적합하며, 이와 관련된 많은 기술들이 예컨대, 미국특허 제5,355,283호에 소개되어 있다.Since semiconductor devices require an increasing number of input / output pins as the degree of integration increases, it is important to miniaturize the size of the device. However, when a small semiconductor device has many input / output pins, the lead pitch of the semiconductor package is too small, and thus the package lead is weak to external shock, and the performance of the chip is reduced due to electrical parasitic variables. There is a problem that requires attention. The ball grid array (BGA) package is known as the efficiency of input / output pins, excluding negative factors caused by inductive components that can occur due to the long lead length in the pin grid array (PGA). A new type of package that can take advantage is suitable for devices that require a large number of leads, and many related techniques are described, for example, in US Pat. No. 5,355,283.

제1도는 종래의 BGA 패키지를 보여준다. 웨이퍼 프로세서에 의해 원하는 회로 소자가 형성된 반도체칩(2)을 회로기판(1)에 장착한다. 반도체칩(2)은 본딩와이어(3)에 의해 회로기판(1)과 전기적으로 연결된다. 밀봉수지, 예컨대 에폭시몰딩컴파운드(EMC, epoxy molding compound)(4)는 반도체칩과 와이어 등을 외부 환경으로부터 보호하기 위한 것이다.1 shows a conventional BGA package. The semiconductor chip 2 on which the desired circuit elements are formed by the wafer processor is mounted on the circuit board 1. The semiconductor chip 2 is electrically connected to the circuit board 1 by the bonding wire 3. Sealing resins such as epoxy molding compound (EMC) 4 are for protecting semiconductor chips and wires from the external environment.

회로기판(1)의 밑면에는 복수개의 솔더볼(5; solder ball)이 붙어 있다. 도면상에는 나타나 있지 않지만, 솔더볼(5)과 반도체칩(2)은 기판에 형성된 배선패턴에 의해 전기적으로 연결되어 있어서 외부의 전기신호가 반도체칩(2)으로 들어가거나 칩(2)에서 나온 데이터가 솔더볼(5)을 통해 외부로 출력될 수 있다. 특히 솔더볼(5)을 전원 전압단자나 접지 단자로 사용하면, 전기적 연결 거리가 짧기 때문에 인덕턴스와 저항을 줄일 수 있다. 솔더볼(5)은 또한 반도체칩(2)에서 발생한 열을 외부로 방출하는 역할도 한다.A plurality of solder balls 5 are attached to the bottom surface of the circuit board 1. Although not shown in the drawing, the solder ball 5 and the semiconductor chip 2 are electrically connected to each other by a wiring pattern formed on a substrate, so that an external electric signal enters the semiconductor chip 2 or data from the chip 2 is lost. The solder ball 5 may be output to the outside. In particular, when the solder ball 5 is used as a power supply voltage terminal or a ground terminal, the inductance and resistance can be reduced because the electrical connection distance is short. The solder ball 5 also serves to discharge heat generated in the semiconductor chip 2 to the outside.

이와 같이, BGA패키지 IC는 평면적 측면에서의 소형화 기술인데, 근래의 반도체 기술은 제품의 다기능화와 멀티미디어 환경 등에 따라 계속 얇아지고 있는 추세에 있다. 얇은 두께뿐만 아니라, 입출력핀 수의 증가와 높은 효율의 방열성이 요구되고 있다.As described above, the BGA package IC is a miniaturization technology in terms of planarity. In recent years, the semiconductor technology is becoming thinner according to the multifunctionality of the product and the multimedia environment. In addition to the thin thickness, an increase in the number of input / output pins and high heat dissipation are required.

따라서, 본 발명의 목적은 종래의 BGA 패키지 제조공정을 개선하여 종래의 BGA패키지보다 더 얇게 제작할 수 있으면서 제조공정을 간소화하고 높은 방열효과를 내는 BGA패키지를 제공하는 것이다.Accordingly, an object of the present invention is to improve the conventional BGA package manufacturing process to provide a thinner than the conventional BGA package while simplifying the manufacturing process and providing a high heat dissipation effect BGA package.

도1은 일반적인 BGA 소자의 종단면도이다.1 is a longitudinal cross-sectional view of a typical BGA device.

도2a~2e는 본 발명에 따른 BGA 소자의 제조방법을 나타내는 종단면도이다.2A to 2E are longitudinal cross-sectional views showing a method for manufacturing a BGA device according to the present invention.

도3은 본 발명에 따른 BGA 소자를 나타내는 종단면도이다.3 is a longitudinal sectional view showing a BGA device according to the present invention.

＜도면의 주요 부호에 대한 설명＞<Description of Major Symbols in Drawing>

회로기판(1) 반도체칩(2)Circuit Board (1) Semiconductor Chip (2)

본딩와이어(3) 밀봉수지(4)Bonding Wire (3) Sealing Resin (4)

솔더볼(5) 웨이퍼(21)Solder Balls (5) Wafers (21)

칩패드(23) 웨이퍼 뒷면(25)Chip Pad (23) Wafer Back (25)

회로기판(27) 접착제(29)Circuit Boards (27) Adhesives (29)

지지판(31) 접착제(33)Support Plate (31) Adhesive (33)

절단선(35) 솔더볼(37)Cutting Line (35) Solder Ball (37)

이하, 도2a~2f를 참조하여 본 발명에 따른 BGA패키지 제조방법에 대해 설명한다.Hereinafter, a method for manufacturing a BGA package according to the present invention will be described with reference to FIGS. 2A to 2F.

도2a는 웨이퍼(21)상에 소정의 기능을 하는 다수의 반도체소자를 형성하고 다수의 칩패드(23)를 일면에 형성하는 웨이퍼가공 단계와, 칩패드(23)가 형성되지 않은 웨이퍼 뒷면(25)을 연마하는 단계를 나타낸다.FIG. 2A illustrates a wafer processing step of forming a plurality of semiconductor devices having predetermined functions on the wafer 21 and forming a plurality of chip pads 23 on one surface, and a back surface of the wafer on which the chip pads 23 are not formed. 25) polishing step.

반도체소자는 확산공정이나 이온주입공정, 각종 막증착 공정 등을 통하여 웨이퍼에 형성되는데, 하나의 웨이퍼에 수백개 이상의 동일한 반도체소자가 한번에 형성된다. 형성된 반도체소자의 외부연결은 웨이퍼표면으로 노출된 칩패드(또는 칩패드, 본딩패드라고도 한다)에 의해 이루어진다. 본 발명의 BGA패키지 제조는 이렇게 하나의 웨이퍼 전체로부터 시작된다. 종래의 BGA패키지에서는 웨이퍼로부터 각 단위 소자를 분리한 다음에 패키지공정을 진행하였다.A semiconductor device is formed on a wafer through a diffusion process, an ion implantation process, various film deposition processes, and the like, and several hundred or more identical semiconductor devices are formed on one wafer at a time. The external connection of the formed semiconductor device is made by chip pads (or chip pads, also referred to as bonding pads) exposed to the wafer surface. The BGA package fabrication of the present invention thus begins with one wafer as a whole. In the conventional BGA package, the unit process was performed after separating each unit device from the wafer.

웨이퍼(21)의 두께를 최소화하기 위하여 웨이퍼의 뒷면(25), 즉 칩패드가 없고 아무런 회로가 형성되어 있지 않은 면을 연마한다. 연마하는 정도는 웨이퍼의 휨이나 강도를 보장할 수 있는 선에서 두께를 최소화하도록 결정된다. 연마는 연마기(grinder)를 써서 물리적으로 할 수도 있고, 약품을 써서 화학적으로 할 수도 있다.In order to minimize the thickness of the wafer 21, the back surface 25 of the wafer, that is, the surface without the chip pad and no circuit is formed, is polished. The degree of polishing is determined to minimize the thickness at a line that can ensure the warpage or strength of the wafer. Polishing can be done physically with a grinder or chemically with a chemical.

도2b는 웨이퍼 뒷면을 연마한 후에 웨이퍼의 앞면, 즉 칩패드(23)가 형성된 면에 회로기판(27)을 접착하는 단계를 나타낸다. 회로기판(27)과 웨이퍼(21)는 접착제(29)에 의해 부착된다. 접착제(29)는 반도체 제조공정에 일반적으로 사용되는 은에폭시 등을 이용할 수 있다.2B shows the step of adhering the circuit board 27 to the front surface of the wafer, that is, the surface on which the chip pad 23 is formed, after polishing the back surface of the wafer. The circuit board 27 and the wafer 21 are attached by the adhesive 29. The adhesive 29 can use silver epoxy etc. which are generally used for a semiconductor manufacturing process.

회로기판(27)은 웨이퍼(21)를 지지하는 역할을 하는 것과 동시에, 웨이퍼(21)에 무질서하게 형성된 칩패드(23)를 BGA 패키지 규격에 맞는 솔더볼(도2d의 37)과 연결하여 전자기기의 PCB에 실장시키도록 하는 역할을 한다.The circuit board 27 supports the wafer 21 and at the same time, connects the chip pad 23 formed at random on the wafer 21 with a solder ball (37 in FIG. 2D) that meets the BGA package standard. It serves to mount on PCB.

위와 같은 역할을 하기 위해서 회로기판(27)은 일정 정도 이상의 강도가 요구된다. 또한, 웨이퍼(21)의 칩패드(23)와 접속되는 패드(미도시)와 외부단자가 부착되는 패드(미도시)와 이들 패드를 연결하는 배선패턴(미도시)이 형성된다. 따라서, 회로기판은 강도가 높고 전기절연성이 우수한 글라스, FR-4, BT수지 등으로 만들어지는데, 웨이퍼의 칩패드에 맞게 배선패턴이 구성된다. 회로기판(27)의 윗면에는 웨이퍼의 칩패드(23)와 접속되는 패드(미도시)가 형성되고 회로기판(27)의 아래면에는 솔더볼(도2d의 37)이 접속되는 패드(미도시)가 형성된다. 윗면 패드와 아래면 패드끼리는 금속배선 패턴으로 연결되는데, 윗면과 아래면을 관통하는 스루홀(또는 비아홀)에 의해 연결된다. 이러한 회로기판(PCB) 기술은 전기전자 분야에서 널리 알려진 주지 관용기술이다. 회로기판(27)과 칩패드(23)를 접속하는 방법에는 범프를 사용하는 방법(bumping)과 직접 칩을 부착하는 방법(DCA: direct chip attachment)이 있다.In order to play such a role, the circuit board 27 requires a certain degree or more of strength. In addition, pads (not shown) connected to the chip pads 23 of the wafer 21, pads (not shown) to which external terminals are attached, and wiring patterns (not shown) connecting these pads are formed. Therefore, the circuit board is made of glass, FR-4, BT resin, etc., which has high strength and excellent electrical insulation, and a wiring pattern is formed in accordance with the chip pad of the wafer. A pad (not shown) connected to the chip pad 23 of the wafer is formed on the upper surface of the circuit board 27, and a pad (not shown) 37 is connected to a solder ball (37 in FIG. 2D) on the lower surface of the circuit board 27. Is formed. The upper pad and the lower pad are connected by a metal wiring pattern, and are connected by through holes (or via holes) passing through the upper and lower surfaces. This circuit board (PCB) technology is a well known common technique in the field of electrical and electronics. A method of connecting the circuit board 27 and the chip pad 23 includes a bumping method and a direct chip attachment method (DCA).

이와 같이, 본 발명에서는 종래의 BGA 패키지 소자와는 달리 웨이퍼 전체를 회로기판과 접착하고, 단자와 칩패드를 가는 금속선으로 연결하는 와이어본딩 공정이 생략되기 때문에 생산비용이 절감되고 생산성을 향상시킬 수 있다.As described above, in the present invention, unlike the conventional BGA package device, since the wire bonding process of adhering the entire wafer to the circuit board and connecting the terminal and the chip pad with a thin metal wire is omitted, production cost can be reduced and productivity can be improved. have.

도2c는 칩패드가 형성되지 않은 웨이퍼 뒷면(25)에, 즉 회로기판(27)이 접착된 반대면에 지지판(31)을 접착하는 단계를 나타낸다. 지지판(31)은 접착제(33)에 의해 접착된다. 이 때의 접착제 역시 일반적으로 사용되는 은에폭시 등을 사용할 수 있다.2C shows the step of adhering the support plate 31 to the back side of the wafer 25 on which the chip pad is not formed, i.e., the opposite side to which the circuit board 27 is bonded. The support plate 31 is bonded by the adhesive 33. The adhesive at this time can also use silver epoxy etc. which are generally used.

사실, 웨이퍼 뒷면(25)을 그대로 놓아둘 수도 있으나, 본 단계는 근래에 전자기기가 복잡, 다기능화하고 고집적화됨에 따라 열방출 효과를 극대화하기 위하여 지지판(31)으로서 금속제의 방열판을 접착하거나 방열제(heat slug)를 도포하기 위한 단계이다. 열방출이 그리 크지 않은 소자일 때에는 지지판(31)으로서 글라스기판을 부착하여 웨이퍼 뒷면(25)의 손상을 방지할 수도 있다. 따라서, 본 단계에서의 지지판(31)에는 도2b에 나타낸 회로기판(27)과는 달리 회로패턴이 형성되어 있지 않다.In fact, the back side of the wafer 25 may be left as it is, but in this step, as the electronic devices are complicated, multifunctional, and highly integrated, in order to maximize the heat dissipation effect, a heat sink made of a metal or a heat sink is supported as the support plate 31. (heat slug) step. In the case of a device in which heat dissipation is not so large, a glass substrate may be attached as the support plate 31 to prevent damage to the back surface 25 of the wafer. Therefore, unlike the circuit board 27 shown in Fig. 2B, the support plate 31 at this stage is not provided with a circuit pattern.

도2c의 지지판(31)에는 중간중간에 분리된 지점(도면부호 35)이 있다. 이 곳은 나중에 완성된 패키지를 절단하여 분리하기 위한 경계선으로서 절단선(35, scribe line)을 나타내는 것이다.The supporting plate 31 of FIG. 2C has a point (35) separated in the middle. This place represents the scribe line 35 as a boundary for later cutting and separating the finished package.

도2d는 위와 같이 조립된 반제품의 회로기판(27) 하면에 솔더볼(37)을 부착하는 단계를 나타낸다. 위에서 회로기판(27)의 하면에는 배선패턴을 통해 칩패드와 연결된 솔더볼용 패드가 형성되어 있다고 하였다. 바로 이 솔더볼용 패드에 외부단자를 부착한 상태가 도2d에 나타나 있는 것이다.Figure 2d shows the step of attaching the solder ball 37 to the lower surface of the semi-finished circuit board 27 assembled as described above. It is said that the lower surface of the circuit board 27 has pads for solder balls connected to the chip pads through wiring patterns. The external terminal is attached to this pad for solder balls is shown in Figure 2d.

웨이퍼의 칩패드(23)는 설계에 따라 무작위 위치에 형성되지만, 반도체소자가 패키지되어 상품화될 때에는 국제규격으로 정해진 치수에 맞게 솔더볼 위치가 정해져야 한다. 이렇게 솔더볼(37)을 외부단자로서 사용하는 패키지를 BGA패키지라 한다. IC 수요자는 이 솔더볼의 간격과 배열에 맞게 자기 제품의 PCB를 설계하여 이 IC를 실장하는 것이다.The chip pad 23 of the wafer is formed at a random position according to the design, but when the semiconductor device is packaged and commercialized, the solder ball position should be determined according to the dimensions defined by the international standard. The package using the solder ball 37 as an external terminal is referred to as a BGA package. IC consumers will design their own PCBs to fit the solder ball spacing and alignment to mount the IC.

솔더볼(37)은 회로기판(27)의 솔더볼용 패드(미도시)에 플럭스를 바른 다음에 설비를 이용하여 솔더볼을 부착하는 방법과, 분사식으로 솔더볼을 부착하는 방법이 있다.The solder balls 37 may be formed by applying flux to a solder ball pad (not shown) of the circuit board 27 and then attaching the solder balls using a facility, and spraying the solder balls by spraying.

도2e는 위와 같이 하여 조립된 소자를 각 단위 소자로 절단하여 분리하는 단계를 나타낸다. 종래의 BGA패키지와 달리 본 발명은 웨이퍼(21) 전체에 한꺼번에 회로기판(27)과 방열판(31)을 부착하여 제조된다고 하였다. 따라서 웨이퍼에 형성된 반도체소자를 각 단위 소자로 절단할 필요가 있다. 절단은 도2c에서 설명한 절단선(35)에 따라 이루어지는데, 일반적으로 회전하는 다이아몬드 칼날로써 절단된다. 절단선(35)의 위치는 패키지의 신뢰성과 칩패드를 보호하기 위하여 가장 외곽에 있는 칩패드에서 3~5mm 정도 이상 떨어진 곳이 바람직하나, 이는 패키지의 최종 크기와 절충해야 할 것이다.2E illustrates a step of cutting and separating the devices assembled as described above into respective unit devices. Unlike the conventional BGA package, the present invention is manufactured by attaching the circuit board 27 and the heat sink 31 at the same time to the entire wafer 21. Therefore, it is necessary to cut the semiconductor elements formed on the wafer into respective unit elements. The cutting is made according to the cutting line 35 described in Fig. 2C, which is generally cut by a rotating diamond blade. The position of the cutting line 35 is preferably 3 to 5 mm or more away from the outermost chip pad in order to protect the reliability of the package and the chip pad, but this should be compromised with the final size of the package.

도3은 위와 같은 방법에 의하여 완성된 BGA패키지 소자의 종단면도를 나타낸다. 칩패드(23)가 형성된 웨이퍼(21) 면에 접착제(29)를 통해 회로기판(27)이 접착되어 있고, 회로기판(27)의 하면에는 솔더볼(37)이 부착되어 있으며 칩패드(23)가 형성되지 않은 웨이퍼 뒷면에 접착제(33)를 통해 지지판(31)이 접착되어 있음을 알 수 있다.3 is a longitudinal cross-sectional view of a BGA package device completed by the above method. The circuit board 27 is adhered to the surface of the wafer 21 on which the chip pad 23 is formed through the adhesive 29, and the solder ball 37 is attached to the bottom surface of the circuit board 27, and the chip pad 23 is attached to the chip pad 23. It can be seen that the support plate 31 is bonded to the back of the wafer on which the adhesive is not formed.

이상에서와 같이, 본 발명에 따르면 종래의 BGA패키지 소자와는 달리 웨이퍼 전체를 한꺼번에 이용하여 조립을 하고 최종적으로 절단 분리하고, 수지에 의한 몰딩 공정이 생략되기 때문에 생산공정이 단순화되고 생산비용이 절감된다. 또한, 웨이퍼에 접착되는 방열판이 직접 패키지 몸체 구실을 하기 때문에 소자의 열방출효과를 극대화할 수 있다. 또, 몰딩 수지 성형몸체가 없기 때문에 종래의 BGA보다 얇은 BGA 소자를 실현할 수 있다.As described above, according to the present invention, unlike the conventional BGA package device, the entire wafer is assembled at one time and finally separated and separated, and a molding process by resin is omitted, thereby simplifying the production process and reducing the production cost. do. In addition, since the heat sink bonded to the wafer directly serves as the package body, the heat dissipation effect of the device can be maximized. In addition, since there is no molded resin molded body, a BGA element thinner than a conventional BGA can be realized.

Claims (5)

웨이퍼상에 소정의 기능을 하는 다수의 반도체소자를 형성하고 다수의 칩패드를 일면에 형성하는 웨이퍼가공 단계,A wafer processing step of forming a plurality of semiconductor devices having a predetermined function on the wafer and forming a plurality of chip pads on one surface; 칩패드가 형성되지 않은 웨이퍼면을 연마하는 단계,Polishing the wafer surface on which the chip pad is not formed, 웨이퍼내에 형성된 반도체소자의 칩패드와 접속되는 칩패드 접속부와, 솔더볼이 접속되는 솔더볼 접속부와, 칩패드 접속부와 솔더볼 접속부를 연결하는 배선패턴이 형성된 회로기판을 칩패드가 형성된 웨이퍼면에 접착하는 단계,Bonding a chip pad connection portion connected to a chip pad of a semiconductor element formed in the wafer, a solder ball connection portion to which solder balls are connected, and a circuit board having a wiring pattern connecting the chip pad connection portion and the solder ball connection portion to the wafer surface on which the chip pad is formed; , 칩패드가 형성되지 않은 웨이퍼면에 지지판을 접착하는 단계,Adhering a support plate to a wafer surface on which a chip pad is not formed; 상기 회로기판에 솔더볼을 부착하는 단계,Attaching a solder ball to the circuit board; 솔더볼이 부착된 웨이퍼를 각 단위 소자별로 절단하는 단계를 포함하는 BGA소자 제조방법.BGA device manufacturing method comprising the step of cutting the solder ball is attached to each unit device. 제1항에 있어서, 상기 지지판은 금속 방열판 또는 방열제(heat slug) 또는 글라스기판인 것을 특징으로 하는 BGA소자 제조방법.The method of claim 1, wherein the support plate is a metal heat sink, a heat slug or a glass substrate. 제1항 또는 제2항에 있어서, 상기 지지판에는 웨이퍼에 형성된 다수의 반도체소자를 각 단위 소자별로 절단하기 위한 경계선이 형성되어 있는 것을 특징으로 하는 BGA소자 제조방법.The method of claim 1 or 2, wherein the support plate is provided with a boundary line for cutting a plurality of semiconductor devices formed on a wafer for each unit device. 소정의 기능을 하는 다수의 반도체소자가 형성되고 일면에 다수의 칩패드가 형성된 웨이퍼,A wafer in which a plurality of semiconductor devices having a predetermined function are formed and a plurality of chip pads are formed on one surface thereof; 칩패드가 형성된 웨이퍼면에 접착된, 웨이퍼내에 형성된 반도체소자의 칩패드와 접속되어 솔더볼로 도출하도록 배선패턴과 솔더볼용 패드가 형성되어 있는 회로기판,A circuit board which is connected to the chip pad of the semiconductor element formed in the wafer, which is bonded to the surface of the wafer on which the chip pad is formed, and which has wiring patterns and pads for solder ball formed thereon to lead to solder balls; 웨이퍼에 접착된 지지판의 반대면에 부착되어 반도체소자의 칩패드를 통해 소자의 기능선을 외부로 도출하는 솔더볼,Solder balls attached to the opposite side of the support plate adhered to the wafer to draw the functional line of the device to the outside through the chip pad of the semiconductor device, 칩패드가 형성되지 않은 연마된 웨이퍼면에 접착된 지지판을 포함하는 BGA소자.A BGA device comprising a support plate adhered to a polished wafer surface on which a chip pad is not formed. 제4항에 있어서, 상기 지지판은 방열판 또는 방열제(heat slug) 또는 글라스기판인 것을 특징으로 하는 BGA 소자.The BGA device according to claim 4, wherein the support plate is a heat sink or a heat slug or a glass substrate.
KR1019980053410A 1998-12-07 1998-12-07 Bga device and manufacturing method thereof KR20000038413A (en)

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