KR20000033944A - Gs-bus dual interface structure - Google Patents

Abstract

PURPOSE: A GS-bus dual interface structure is provided to support a communication line between processors in a distributed control system of a switching system, specially to inform a receiving data line status of a standby side by checking data train of an active and standby side at an IPC communication. CONSTITUTION: A GS-bus dual interface structure includes a standby bus test logic for testing an error occurrence of the standby bus by comparing a transmission data, input into a transceiver, with a standby bus data loop-backed. The standby bus test logic comprises standby bus data comparison detectors(25,26,27) and a standby bus error status register(28). The standby bus data comparison detectors(25,26,27) compares the data bit train of the transmission data with the looped-back standby bus data bit train. The standby bus error status register(28) receives the error detection result from the standby bus data comparison detectors(25,26,27), and sends the result to a CPU(10).

Description

GS bus redundancy interface structure

The present invention relates to a GS-Bus having a function of providing a communication path between processors in a distributed control system in an exchange, and more particularly, to a redundant interface structure of a GS bus capable of testing a standby bus.

In general, communication between the processors is possible through a pattern on the backboard or IPC communication using a GS bus cable. At this time, the GS bus is configured with redundancy.

The GS bus is composed of signals such as FRS, ASTCLK, ASTOUT, BRCLK, DATA, and TKAST. Each signal is defined as follows.

FRS: When provided from the bus master, the initial value of the local counter is loaded as a reference signal for assigning bus occupancy opportunities of each processor in a predetermined order.

ASTCLK: Provided by the bus master, this clock is used to synchronize the bus arbitration logic of each processor with the local counter clock.

TKST: When the bus occupancy signal (ASSERT) is released, it is driven by the processor with the data to be transferred to the bus in the next processor so that the bus can be occupied. This signal is a bidirectional signal. When this signal is activated, the local counters of each processor stop counting up, and when the occupied signal on the bus is released, the processor that drives this signal drives the bus occupied signal. At the same time, it gives the next processor the opportunity to occupy the bus.

ASSERT: A bi-directional signal indicates bus occupancy. The processor occupies the bus.

BRCLK: It is driven by a processor that transmits data as a clock for serial data transmission as a bidirectional signal.

DATA: Serial data synchronized to BRCLK transmitted to the bus as a bidirectional signal.

IALARM: When a cable is disconnected on the GS bus, this signal goes high, causing all processors to switch to the normal bus.

OALARM: In the daisy chain type GS bus connection, output is low from the first processor. If the middle processor is bypassed, the last processor loops OALARM and IALARM. looping).

COFFIN: Cable hernia alarm signal to recognize cable hernia by section when daisy-chained GS bus cable is connected.

COFFOUT: Always at ground (GND) level and daisy chained to the next processor's COFFIN by cable.

In the bus arbitration method of GS-Bus, the processors that are accommodated in the bus by the round robin method have the equal bus use opportunity, but the following conditions are used in the bus occupied state to minimize the overhead for bus arbitration. Minimize bus turnaround time by prescribing a bus license to the bus and letting the reserved processor occupy the bus once the bus is released.

It is operated with the structure of redundancy in redundancy in IPC communication between processors. That is, the processor for transmitting data gives the same information to the A / B bus and the receiving side selects one of the two signals. The condition of the signal selection is determined by the signal of the software selector under the control of the software through reporting by the software signal error detection logic and software judgment.

1 shows a CPU 10, a GS bus interface 20, and a redundant GS bus unit 30 as a conventional IPC interface structure.

When the CPU transmits or receives data to another processor, the CPU loads data to or receives data from the redundant GS bus unit 30 through the GS bus interface unit 20. When there is data to be transmitted to another processor, it is loaded on the GS bus 30 through buffers on the active side and standby side in accordance with the reference synchronization signal. However, in the case of receiving data, the bus is selected through the GS bus interface unit 20 between the CPU and the transceiver to receive the selected received data.

The GS bus interface unit 20 selects an active bus from GS bus A and GS bus B based on the bus arbitration unit 21 in charge of bus arbitration and the active bus selection signal of the CPU 10. CPU bus 10 detects the clock signal of the bus on the active part side among the GS bus A and the GS bus B, and stores the error detection state of the GS bus and the CPU 10 to store the error detection state of the GS bus. It is composed of a register unit 24 for knowing whether an error occurs in the GS bus.

In the conventional GS bus interface structure configured as described above, an error of the active bus is detected among the GS bus A and the GS bus B, and the state is stored in the register (Reg (0-6)) 24. The CPU 10 periodically reads data of the register 24 to determine whether an error exists in the GS bus and performs error recovery accordingly.

However, the selection of IPC data received in the structure of the redundant GS bus as described above is determined by the selection signal by software. Therefore, if an error occurs in the data due to the characteristics of the GS bus operating in the same structure as the exchanger, it can be recovered only through various complicated processes. In other words, each block must verify the route of the GS bus. Therefore, in the conventional structure, there is a structural problem in which the state of the standby side Rx data line on the GS bus cannot be known.

Accordingly, the present invention has been made to solve the above-mentioned problem, GS bus redundancy interface structure to check the status of the receiving data line of the standby side by checking the data streams of the active and standby side of the redundant structure during IPC communication To provide that purpose.

In the GS bus redundancy interface structure according to the present invention for achieving the above object, in the GS bus redundancy interface structure providing an inter-processor communication (IPC) path, the transmission data input to the transceiver and the standby bus data returned by looping back Compared with the standby bus test logic to test whether the standby bus error occurs, the standby bus test logic compares the bit stream of the transmit data input to the transceiver with the loopback standby bus data bit stream. And a standby bus data comparison detection unit for detecting an error of the standby bus, and a standby bus error status register for receiving an error detection result of the standby bus from the standby bus error detection unit and informing the CPU. Toxing

1 is a structural diagram of a conventional IPC interface;

2 is an IPC interface structure diagram according to the present invention;

3 is a circuit diagram of a comparison detection unit added to GS bus interface logic;

4 is a data bit stream comparison detection timing diagram in a comparison detection unit.

Explanation of symbols on the main parts of the drawings

10: CPU 20: JS Bus Interface

21: bus arbitration unit 22: selector

23 GS bus error detection unit 24: register unit

25, 26, 27, (100): first, second, third data bit stream comparison detection unit

28: status register 30: GS bus unit

31: GS Bus A 32: GS Bus B

101: first exclusive or gate 102: first deflect flop

103: first end gate 104: first NOR gate

105: second deflip flop 106: or gate

107: second and gate 108: third diflip pop

109: fourth def flip-flop 110: the second exclusive or gate

111: third and gate 112: second NOR gate

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 further includes an IPC loopback test comparison unit to be added for error detection of a standby bus to the structure of the conventional GS interface shown in FIG. 1.

Each processor has its own loopback function in the GS bus, which is redundant with an active bus and a standby bus. That is, since it can receive (RXD) the data Tx transmitted by itself, the CPU transmits the data through the GS interface.

As shown, the GS bus interface unit 20 selects an active bus from GS bus A and GS bus B based on the bus arbitration unit 21 responsible for bus arbitration and the active bus selection signals of the CPU 10. The CPU bus error detection unit 23 and the GS bus error detection state are detected by detecting the clock signal of the bus on the AC-side bus from among the selector 22 and the GS bus A and the GS bus B. 10) compares the register unit 24 for detecting whether an error occurs in the GS bus with the transmission data transmitted from the CPU 10 to the transceiver and the received data received from the standby bus by looping back to detect an error. From the first, second, and third data bitstream comparison detection units 25, 26, 27, and the transmission data transmitted from the CPU 10 and the standby bus Consists of the new stores the comparison result of the IPC loopback data status register (Reg 7) (28).

In the GS interface structure, the first, second, and third data bitstream comparison detection units 25 which detect an error by comparing the transmission data transmitted from the CPU 10 to the transceiver and the received data received from the standby bus are looped back. 26 and 27, and a status register (Reg 7) 28 for storing a comparison result of the transmission data transmitted from the CPU 10 and the IPC loopback data received from the standby bus.

The operation state of the GS bus interface structure further including the first, second, and third bitstream comparison detection units 25, 26, 27 and the state register 28 as described above is as follows.

Data of the active bus selected as the active side bus among the GS bus A and the GS bus B by the selector 22 is received by the CPU 10. The GS error detection unit 23 detects whether an error occurs in the active bus, while the data bitstream of the GS bus selected as the standby bus in the selector 22 is compared with the first, second, and third. Transmitting data Tx inputted from the CPU 10 to the transceiver by the detectors 25, 26, and 27 and received data Rx looped back to the data detection comparators 25, 26, and 27 are used. Compared with each other, if a bit stream of different data occurs, it is treated as an error and stored in the status register 28. At this time, the value of the stored register is cleared after the CPU 10 reads it. Therefore, the processor performs verification in the first comparison detector, the second comparison detector, and the third comparison detector through the IPC loopback test.

3 shows a detailed circuit diagram of the first, second, and third comparison detectors added to the GS bus interface logic. Since the configuration of each comparison detection unit is the same, one will be described and the member number 100 is used for convenience.

The comparison detection unit 100 is configured to detect an error by comparing the data bit stream.

As shown, a first exclusive or gate 101 for performing an exclusive or operation on the transmit data TXD and the IPC loopback received data RXD input to the transceiver, and the first exclusive or gate ( A first deflip-flop 102 for receiving the output signal of the signal 101 as a D input terminal and latching the output signal based on the data transfer clock BRCLK; and an output of the first deflip-flop 102; A second deflip flop 105 for outputting a high signal based on the data transmission clock BRCLK and an or gate 106 for ORing the output signal and the READ signal of the second deflip flop 105 are provided. . A first AND gate 103 for ending an AST signal and a RESET signal is connected to the reset terminal of the first flip-flop 102 through the first NOR gate 104. The reset terminal of the second flip-flop 105 is connected with a second AND gate 107 for ending the D_READ signal and the RESET signal. In order to output the D_READ signal, the READ signal is received as the D input terminal and the third deflip-flop 108 which latches based on the data transmission clock BRCLK and the third deflip-flop 108 receive the data and transmit the data. A second deflected flop 109 latching based on a clock BRCLK, and a second exclusive or gate 110 which exclusively outputs the output of the fourth deflected flop 109 and the READ signal; A third AND gate 111 for ending the output of the second exclusive or gate 110 and the READ signal and a second NOR gate 112 for inverting the output of the third AND gate 111 are provided.

In FIG. 3, the data transfer clock BRCLK is a clock for serial data transmission as a bidirectional signal, a READ signal is a read clock for reading the status register 28 from the CPU 10, and a D_READ signal is a delayed signal of the READ signal. to be. The AST signal represents a data valid period as a bus occupancy signal, TXD represents transmission data of a GS bus, RXD represents received data of a GS bus, and OUT represents a comparatively detected error occurrence bit.

4 shows a comparison detection timing diagram of a data bit stream.

In the timing diagram, D_XOR is an output signal of the first deflip-flop 102, COMPARE is an output signal of the second deflip-flop 105, and OUT is an output signal of the or gate 106.

The CPU is activated when the READ signal, which is a CPU register enable signal, is a LOW signal, and reads the output of the OR gate 106 to recognize whether an error has occurred.

When the AST signal is low and the RESET signal is low, the first deflip-flop is activated to latch and output the input signal of the D input terminal. When the RXD data bit 121 that is different from the bit of the TXD data is input, the output of the first exclusive or gate 101 outputs high and the first deflip-flop at the next falling edge of the data transfer clock BRCLK. An output signal of 102 outputs a high 122. At the next falling edge, since the output of the first exclusive or gate 101 is low, the first deflip-flop 102 outputs a low again. On the other hand, the output of the second deflip-flop 105 is kept low, and is set when the output signal of the first deflip-flop 102 becomes high 122 to output the high signal 123. While the output signal of the second deflip 105 maintains the high signal, the READ signal of the CPU 10 becomes low 124 to be activated to read the error detection result of the data bit (125). The second de-flip 105 maintains a high signal and is reset when the D_READ signal goes high (126) and outputs a low signal 127 again with a slight delay. As a result, the OUT signal, which is the output signal of the OR gate 106, outputs a low signal again. As a result, the high state of the output signal of the OR gate 106 means that the transmission data TXD and the reception data RXD of the GS bus have different bit strings. In this case, the CPU 10 recognizes that an error has occurred in the standby GS bus.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common knowledge in the art that various substitutions, conversions, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those who have

According to the present invention, it is possible to increase the reliability in terms of hardware and reduce the overhead in terms of software by examining data streams on the active and standby sides of a redundant structure during high-speed IPC communication. Will be.

Claims (2)

In the bus bus redundancy interface structure that provides a communication path between processors, GS bus redundancy interface structure further comprising a standby bus test logic for testing whether the standby bus error occurs by comparing the transmission data input to the transceiver with the standby bus data returned to the loopback. The method of claim 1, wherein the standby bus test logic, A standby bus data comparison detector for detecting an error of the standby bus by comparing a bit string of the transmission data input to the transceiver with a looped back standby bus data bit string; And a standby bus error status register configured to receive an error detection result of the standby bus from the standby bus error detection unit and notify the CPU of the standby bus error detection unit.