KR20000032791A - Lcd for displaying 16/9 screen and method therefor - Google Patents

Lcd for displaying 16/9 screen and method therefor Download PDF

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Publication number
KR20000032791A
KR20000032791A KR1019980049386A KR19980049386A KR20000032791A KR 20000032791 A KR20000032791 A KR 20000032791A KR 1019980049386 A KR1019980049386 A KR 1019980049386A KR 19980049386 A KR19980049386 A KR 19980049386A KR 20000032791 A KR20000032791 A KR 20000032791A
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South Korea
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signal
data
timing controller
driver
gate
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KR1019980049386A
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Korean (ko)
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나근식
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윤종용
삼성전자 주식회사
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Priority to KR1019980049386A priority Critical patent/KR20000032791A/en
Publication of KR20000032791A publication Critical patent/KR20000032791A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/02—Graphics controller able to handle multiple formats, e.g. input or output formats

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE: An LCD for displaying 16/9 screen and a method therefor are provided to easily display 16/9 data in a 4/3 screen without deformation of data. CONSTITUTION: An LCD for displaying 16/9 screen comprises a timing controller(3), a gate driver(2), a source driver(1), and a panel(4). The timing controller receives data and synchronous signal and controls timing for displaying the data. The gate driver(2) takes the TFTs of a panel(4) sequentially ON in accordance with the control signals of the timing controller(3). The source driver(1) outputs the voltages corresponding to respective data in accordance with the load signals from the timing controller. The panel(4) receives the output voltage of the data driver in accordance with the gate drive signals of the gate driver to display information.

Description

16:9화면을 디스플레이 하는 액정표시장치 및 방법Liquid crystal display and method for displaying 16: 9 screen

이 발명은 액정 표시 장치(LCD: Liquid Crystal Display)에 관한 것으로, 특히, 4:3화면으로 16:9 화면을 구현하는 액정표시장치 및 방법에 관한 것이다.The present invention relates to a liquid crystal display (LCD), and more particularly, to a liquid crystal display and a method for realizing a 16: 9 screen with a 4: 3 screen.

박막 트랜지스터 액정 표시 장치는 게이트선을 통하여 주사신호를 인가하여 각 화소의 트랜지스터를 동작시켜 각 행의 화소에 차례로 데이터 신호를 입력하고, 각 화소에 유지 축전기를 두어 박막 트랜지스터가 오프 상태일 때에도 데이터 전압을 오랫동안 유지한다.A thin film transistor liquid crystal display device applies a scan signal through a gate line to operate transistors of each pixel to input data signals to pixels in each row in turn, and a storage capacitor is provided to each pixel so that the data voltage is maintained even when the thin film transistor is turned off. Keep it for a long time.

능동 행렬(active matrix)형 액정표시장치에서 각 화소의 액정을 구동하기 위해서는 박막 트랜지스터를 주기적으로 온/오프시켜야 하는데, 박막 트랜지스터를 온/오프시키기 위해서는 통상적으로 +20V이상, -5V이하의 게이트 전압을 박막 트랜지스터의 게이트에 인가해 준다.In an active matrix liquid crystal display, thin film transistors must be turned on and off periodically to drive the liquid crystal of each pixel. Gate voltages of + 20V and below -5V are generally required to turn on and off thin film transistors. Is applied to the gate of the thin film transistor.

종래의 음극선관(CRT:cathod ray tube) 표시장치는 4:3화면으로 16:9화면을 구현하기 위하여 수직 동기 신호의 상하측의 표시시간을 블랭킹(blanking)처리를 하였다. 이렇게 함으로써 종래에는 4:3 화면을 16:9화면처럼 보이게 하였다.In the conventional cathode ray tube (CRT) display device, a blanking process is performed on the upper and lower display times of a vertical synchronization signal in order to realize a 16: 9 screen with a 4: 3 screen. In this way, the 4: 3 screen is conventionally made to look like a 16: 9 screen.

그러나, 종래의 4:3 화면으로 16:9화면을 표시하는 방법은 상하측의 표시시간을 블랭킹처리하기 때문에 데이터의 왜곡이 우려되는 단점이 있다.However, the conventional method of displaying a 16: 9 screen on a 4: 3 screen has a disadvantage in that data distortion is concerned because the display time of the upper and lower sides is blanked.

본 발명이 이루고자 하는 기술적 과제는 종래의 단점을 해결하고자 하는 것으로, 데이터의 왜곡없이 4:3화면에서 16:9데이터를 하드웨어적으로 간단히 표시하도록 하는 액정표시장치 및 방법을 제공하고자 하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to solve a conventional disadvantage, and to provide a liquid crystal display and a method for easily displaying 16: 9 data on a 4: 3 screen in hardware without distortion of the data.

도1은 이 발명의 실시예에 따른 액정표시장치의 블록 구성도.1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

도2는 도1의 각 신호 파형도.FIG. 2 is a signal waveform diagram of FIG. 1; FIG.

도3은 이 발명의 실시예에 따른 액정표시장치의 패널의 예시도.3 is an exemplary view of a panel of a liquid crystal display device according to an embodiment of the present invention.

도4는 이 발명의 실시예에 따른 16:9화면을 디스플레이 하는 방법의 흐름도.4 is a flowchart of a method for displaying a 16: 9 screen according to an embodiment of the present invention.

본 발명에서는 이러한 기술적 과제를 달성하기 위하여, 타이밍 컨트롤러는 외부의 16:9 포맷 데이터를 입력받아, 수평 동기 신호의 일정구간 동안만 디스플레이를 하도록 제어한다. 게이트 드라이버는 타이밍 컨트롤러로부터의 제어신호에 따라 액정 표시 장치 패널의 박막 트랜지스터를 라인별로 차례로 온 시키는 게이트 구동신호를 출력한다. 데이터 드라이버는 타이밍 컨트롤러로부터 입력되는 데이터를 시프트 레지스터내에 저장했다가 데이터를 출력하도록 명령하는 타이밍 컨트롤러로부터의 로드 신호에 따라 각각의 데이터에 해당하는 전압을 출력한다. 패널은 게이트 드라이버의 게이트 구동신호에 따라 상기 데이터 드라이버의 출력전압을 인가 받음으로써 정보를 표시한다. 이렇게 함으로써, 데이터의 왜곡없이 16:9 데이터를 4:3화면에 표시하게 된다.In the present invention, in order to achieve the technical problem, the timing controller receives external 16: 9 format data and controls the display to display only for a certain period of the horizontal synchronization signal. The gate driver outputs a gate driving signal that sequentially turns on the thin film transistor of the liquid crystal display panel line by line according to a control signal from the timing controller. The data driver stores the data input from the timing controller in the shift register and outputs a voltage corresponding to each data according to the load signal from the timing controller instructing the data output. The panel displays information by receiving the output voltage of the data driver according to the gate driving signal of the gate driver. By doing so, 16: 9 data is displayed on a 4: 3 screen without distortion of the data.

이 발명의 실시예에 대하여 첨부한 도면을 참조로 하여 설명하면 다음과 같다.Embodiments of the present invention will be described below with reference to the accompanying drawings.

도1은 이 발명의 실시예에 따른 액정 표시 장치 구동장치의 블록도이고,1 is a block diagram of a liquid crystal display driving device according to an embodiment of the present invention;

도2는 도1의 각부 파형도이다.FIG. 2 is a waveform diagram of each part of FIG. 1.

도1에서 보는 바와 같이, 외부의 데이터 및 동기신호를 입력받아 데이터를 디스플레이 하도록 타이밍을 제어하는 타이밍 컨트롤러(3)의 출력신호는 게이트 드라이버(2) 및 소스 드라이버(1)로 입력된다.As shown in Fig. 1, the output signal of the timing controller 3 which controls the timing to receive the external data and the synchronization signal and display the data is input to the gate driver 2 and the source driver 1.

게이트 드라이버(2)는 타이밍 컨트롤러로부터 스타트 펄스 수직 신호(STV)를 받으면, 이벤트 인에이블 신호(EEN) 및 게이트 클럭 신호(CPV)에 따라 액정 표시 장치 패널(4)의 박막 트랜지스터를 라인별로 차례로 온 시키기 위해 게이트 구동 신호를 출력한다.When the gate driver 2 receives the start pulse vertical signal STV from the timing controller, the gate driver 2 sequentially turns on the thin film transistors of the liquid crystal display panel 4 line by line according to the event enable signal EEN and the gate clock signal CPV. Outputs a gate drive signal.

소스 드라이버(1)는 타이밍 컨트롤러(3)로부터 입력되는 데이터를 시프트 레지스터내에 저장했다가 데이터를 액정표시장치 패널(4)에 내릴 것을 명령하는 로드 신호(LP)의 제어에 따라 각각의 데이터에 해당하는 전압을 액정 표시 장치 패널(4)에 출력한다.The source driver 1 stores the data input from the timing controller 3 in the shift register and corresponds to the respective data according to the control of the load signal LP which instructs the liquid crystal display panel 4 to lower the data. The voltage to be output is output to the liquid crystal display panel 4.

다음, 이 발명의 실시예의 동작에 대하여 도1 내지 도4를 참조로 하여 설명하기로 한다.Next, the operation of the embodiment of the present invention will be described with reference to Figs.

먼저, 사용자에 의해 전원이 인가되면, 컴퓨터 등의 그래픽 컨트롤러로부터 타이밍 컨트롤러(3)로 적녹청(RGB) 데이터, 수평 동기 신호(HS), 수직 동기신호(VS), 데이터 인에이블 신호(DE) 및 메인 클럭 신호(MCLK)가 입력된다(S1).First, when power is applied by the user, the red and green (RGB) data, the horizontal synchronizing signal HS, the vertical synchronizing signal VS, and the data enable signal DE are transmitted from a graphic controller such as a computer to the timing controller 3. And the main clock signal MCLK is input (S1).

그러면, 타이밍 컨트롤러(3)는 입력된 데이터의 포맷을 판별하고(S2), 16:9 포맷이면 이벤트 인에이블 신호(EEN)를 발생시키는데, 이때, 데이터의 이벤트 인에이블 신호(EEN)는 도2에 도시된 바와 같이, UXGA(ultra extnded graphic array)에서 수직동기신호를 기준으로 하여 그 사이에서 각각 150H를 더미(dummy)처리한 것이다. 즉, 도3과 같이, 수평동기신호의 150번째 클럭 뒤에 시작신호(START EEN)가 뜨고, 다음번째 수직동기신호(VS)를 기준으로 수평동기신호(HS)의 150번째 클럭 앞에서 끝을 알리는 신호(END EEN)가 뜬다(S3). 이렇게 되면, 이벤트 인에이블 신호 사이(START EEN∼END EEN) 사이에서만 게이트 구동신호가 패널(4)에 인가된다.Then, the timing controller 3 determines the format of the input data (S2), and generates an event enable signal (EEN) when the format is 16: 9. In this case, the event enable signal (EEN) of the data is shown in FIG. As shown in FIG. 2, each 150H is dummyly processed based on a vertical synchronization signal in an UXGA (ultra extnded graphic array). That is, as shown in FIG. 3, the start signal START EEN appears after the 150th clock of the horizontal synchronization signal, and the signal notifies the end of the 150th clock of the horizontal synchronization signal HS based on the next vertical synchronization signal VS. (END EEN) is displayed (S3). In this case, the gate driving signal is applied to the panel 4 only between the event enable signals (START EEN to END EEN).

한편, 타이밍 컨트롤러(3)는 그래픽 컨트롤러로부터 입력받은 신호들을 이용하여, 게이트 클럭 신호(CPV: clock pulse vertical) 및 게이트 구동신호의 시작을 알리는 스타트 펄스 수직 신호(STV: start pulse vertical)를 생성하여 게이트 드라이버(2)로 출력한다.Meanwhile, the timing controller 3 generates a gate clock signal (CPV: clock pulse vertical) and a start pulse vertical signal (STV: start pulse vertical) indicating the start of the gate driving signal by using the signals input from the graphic controller. Output to the gate driver 2.

또한, 소스 클럭 신호(HCLK: horizontal clock), 스타트 펄스 수평신호(STH: start horizontal signal), 로드 신호(LP: load signal)를 생성하여 적녹청(R, G, B) 데이터와 같이 소스 드라이버(2)로 출력한다.In addition, the source clock signal (HCLK: horizontal clock), start pulse horizontal signal (STH: start horizontal signal), and load signal (LP) to generate a source driver (R, G, B) data, such as 2)

다음, 게이트 드라이버(2)는 스타트 펄스 수직 신호(STV)를 받으면, 게이트 클럭 신호(CPV)에 따라 패널(4)의 박막 트랜지스터를 라인별로 차례로 온 시키기 위한 게이트 구동 신호를 출력하는데, 이벤트 인에이블 신호의 시작과 끝 구간에서만 게이트 구동신호를 패널(4)로 인가한다(S4).Next, when the gate driver 2 receives the start pulse vertical signal STV, the gate driver 2 outputs a gate driving signal for sequentially turning on the thin film transistors of the panel 4 line by line according to the gate clock signal CPV. Event enable The gate driving signal is applied to the panel 4 only at the beginning and the end of the signal (S4).

그러면, 액정표시장치 패널(4)은 도3과 같이, 게이트 구동신호가 인가되는 구간에서만 소스 드라이버(1)에서 출력되는 데이터에 해당하는 전압을 화면에 표시하게 된다(S5). 이렇게 함으로써 4:3화면에서 16:9화면을 구현할 수 있다.Then, as shown in FIG. 3, the liquid crystal display panel 4 displays the voltage corresponding to the data output from the source driver 1 only on the screen to which the gate driving signal is applied (S5). In this way, a 16: 9 screen can be realized in a 4: 3 screen.

한편, 4:3포맷의 데이터는 기존과 같이, 액정표시장치 패널(4)의 전영역에 데이터를 표시하게 된다.On the other hand, the 4: 3 format data displays data in the entire area of the liquid crystal display panel 4 as before.

따라서, 본 발명은 데이터의 왜곡이 없이, 도3에 도시된 바와 같이, 이벤트 인에이블 신호가 인가되면, 패널의 상하측 부분에서 수팽동기신호의 150클럭에 해당하는 부분의 게이트 드라이버 회로의 부분이 없어진 것과 같은 효과를 낸다. 이렇게 함으로써 패널의 화질을 향상할 수가 있다.Accordingly, in the present invention, when the event enable signal is applied as shown in FIG. 3 without distortion of the data, a portion of the gate driver circuit in a portion corresponding to 150 clocks of the water swell signal in the upper and lower portions of the panel is removed. It has the same effect as missing. In this way, the image quality of the panel can be improved.

이상에서와 같이, 이 발명의 실시예에서, 인터폴레이션(interpolation)과 같은 신호처리없이 16:9 포맷의 데이터를 표시할 수 있는, 16:9화면을 디스플레이 하는 액정표시장치 및 방법을 제공할 수 있다.As described above, in the embodiment of the present invention, it is possible to provide a liquid crystal display device and method for displaying a 16: 9 screen, which can display data in 16: 9 format without signal processing such as interpolation. .

Claims (4)

외부의 16:9 포맷 데이터를 입력받아, 수평 동기 신호의 일정구간 동안만 디스플레이를 하도록 제어하는 타이밍 컨트롤러;A timing controller which receives external 16: 9 format data and controls the display to display only during a certain period of the horizontal synchronization signal; 상기 타이밍 컨트롤러로부터의 제어신호에 따라 액정 표시 장치 패널의 박막 트랜지스터를 라인별로 차례로 온 시키는 게이트 구동신호를 출력하는 게이트 드라이버;A gate driver for outputting a gate driving signal for sequentially turning on the thin film transistor of the liquid crystal display panel line by line according to the control signal from the timing controller; 상기 타이밍 컨트롤러로부터 입력되는 데이터를 시프트 레지스터내에 저장했다가 데이터를 출력하도록 명령하는 상기 타이밍 컨트롤러로부터의 로드 신호에 따라 각각의 데이터에 해당하는 전압을 출력하는 소스 드라이버;A source driver for storing data input from the timing controller in a shift register and outputting a voltage corresponding to each data according to a load signal from the timing controller instructing to output the data; 상기 게이트 드라이버의 게이트 구동신호에 따라 상기 데이터 드라이버의 출력전압을 인가 받음으로써 정보를 표시하는 패널A panel displaying information by receiving an output voltage of the data driver according to a gate driving signal of the gate driver. 을 포함하는 액정 표시 장치.Liquid crystal display comprising a. 제1항에서,In claim 1, 상기한 타이밍 컨트롤러는,The timing controller described above 수직동기신호를 기준으로 하여 수직동기신호의 사이에서 각각 수평동기신호의 150개의 클럭에 해당하는 길이에는 데이터를 인가하지 않도록 이벤트 인에이블 신호를 출력하는 것을 특징으로 하는 액정표시장치.And an event enable signal is output so that data is not applied to a length corresponding to 150 clocks of the horizontal synchronization signal, respectively, based on the vertical synchronization signal. 제2항에서,In claim 2, 상기한 게이트 드라이버는 상기 이벤트 인에이블 신호의 시작과 끝 구간에서만 게이트 구동 신호를 출력하는 것을 특징으로 하는 액정표시장치.And the gate driver outputs the gate driving signal only at the beginning and the end of the event enable signal. 입력신호의 형태가 16:9포맷인지를 판단하는 단계와;Determining whether a form of an input signal is in a 16: 9 format; 입력신호의 포맷이 16:9포맷이면, 이벤트 인에이블 신호를 발생하여 수직동기신호를 기준으로 수팽동기신호의 상하측 일정부분을 제외하고 게이트 구동신호를 출력하는 단계와;If the format of the input signal is 16: 9, generating an event enable signal and outputting a gate driving signal excluding the upper and lower predetermined portions of the male synchronous signal based on the vertical synchronous signal; 상기 게이트 구동신호에 따라 데이터에 해당하는 전압을 표시하는 단계를 포함하는 16:9화면을 디스플레이 하는 방법.And displaying a voltage corresponding to data according to the gate driving signal.
KR1019980049386A 1998-11-18 1998-11-18 Lcd for displaying 16/9 screen and method therefor KR20000032791A (en)

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