KR20000027501A - Method for manufacturing lower side leading type package - Google Patents

Method for manufacturing lower side leading type package Download PDF

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Publication number
KR20000027501A
KR20000027501A KR1019980045446A KR19980045446A KR20000027501A KR 20000027501 A KR20000027501 A KR 20000027501A KR 1019980045446 A KR1019980045446 A KR 1019980045446A KR 19980045446 A KR19980045446 A KR 19980045446A KR 20000027501 A KR20000027501 A KR 20000027501A
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KR
South Korea
Prior art keywords
lead
mixture
gold
nickel
solder ball
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KR1019980045446A
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Korean (ko)
Inventor
박상욱
김재면
김지연
Original Assignee
김영환
현대전자산업 주식회사
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Priority to KR1019980045446A priority Critical patent/KR20000027501A/en
Publication of KR20000027501A publication Critical patent/KR20000027501A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE: A method of manufacturing lower side leading type package is provided to prevent the bonding material from being smeared into the outer lead when molding by attaching the insulation tape to the outer lead before molding. CONSTITUTION: A system comprises a semiconductor chip(1), a lead frame(2), a bonding material(3), a metal wire(4), a packaging material(5), a solder ball, a tape(20), an inner lead(21), and an outer lead(22). The semiconductor chip(1) is adhered to the inner lead(21) of the lead frame using the bonding material. The semiconductor chip and the inner wire is connected with the metal wire(4). The insulating tape(20) is attached to the bottom of the outer lead of the lead frame. After molding with the packaging material(5), the outer lead is exposed by cutting or etching the insulating tape and the outer lead is mounted on the substrate.

Description

저면 리드형 패키지 제조 방법How to Make a Bottom Lead Package

본 발명은 저면 리드형 패키지의 제조 방법에 관한 것으로서, 보다 구체적으로는 리드 프레임의 아우터 리드가 저면으로 노출된 구조의 패키지를 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a bottom lead type package, and more particularly, to a method of manufacturing a package having a structure in which an outer lead of a lead frame is exposed to a bottom face.

패키지의 경박화를 실현하기 위해 리드 프레임상에 직접 반도체 칩이 탑재되고, 리드 프레임의 아우터 리드가 저면으로 노출된 구조의 저면 리드형 패키지에 대한 연구가 최근에 활발히 진행되고 있다.In order to realize thinning of the package, research has been actively conducted on the bottom lead type package having a structure in which a semiconductor chip is directly mounted on the lead frame and the outer lead of the lead frame is exposed to the bottom.

이러한 저면 리드형 패키지의 두 가지 예가 도 1 및 도 2에 도시되어 있다.Two examples of such bottom leaded packages are shown in FIGS. 1 and 2.

도 1에 도시된 패키지는 저면 리드형 패키지중에서 엘오씨(LOC) 타입으로서, 도시된 바와 같이, 리드 프레임(2)상에 접착 테이프(3)를 매개로 반도체 칩(1)이 부착되어 있고, 리드 프레임(2)의 인너 리드(21)와 반도체 칩(1)의 패드가 금속 와이어(4)로 연결되어서, 전체가 봉지제(5)로 몰딩된 구조이다. 특히, 기판에 실장되는 리드 프레임(2)의 아우터 리드(22)는 봉지제(5)의 저면으로 노출된 구조이다.The package shown in FIG. 1 is an LOC type in the bottom lead type package, and as illustrated, the semiconductor chip 1 is attached to the lead frame 2 via an adhesive tape 3. The inner lead 21 of the lead frame 2 and the pad of the semiconductor chip 1 are connected by the metal wire 4, and the whole is molded with the encapsulant 5. In particular, the outer lead 22 of the lead frame 2 mounted on the substrate has a structure exposed to the bottom surface of the encapsulant 5.

한편, 도 2에 도시된 패키지는 볼 그리드 어레이 타입으로서, 리드 프레임(7)의 밑면이 부분 식각되어 아우터 리드(72)가 형성되고, 이 아우터 리드(72)가 봉지제(5) 저면으로 노출된 구조로서, 아우터 리드(72)에는 기판에 실장되는 솔더 볼(6)이 부착된 구조이다.On the other hand, the package shown in Figure 2 is a ball grid array type, the bottom surface of the lead frame 7 is partially etched to form an outer lead 72, the outer lead 72 is exposed to the bottom surface of the encapsulant (5) The outer lead 72 has a structure in which a solder ball 6 mounted on a substrate is attached to the outer lead 72.

그런데, 봉지제(5)로 몰딩하기 위해서, 전체를 금형의 캐비티내에 위치시킨 다음, 봉지제(5)를 캐비티내로 플로우시키므로써, 몰딩하도록 되어 있는데, 이러한 몰딩 공정에서 종래의 패키지 제조 방법은 다음과 같은 문제점을 갖고 있다.By the way, in order to mold with the encapsulant 5, the whole is placed in the cavity of the mold and then the encapsulant 5 is flowed into the cavity, thereby molding. In such a molding process, a conventional package manufacturing method is as follows. It has the same problem.

종래의 아우터 리드(22,72)는 노출된 상태로 있기 때문에, 리드 프레임의 각 아우터 리드(22,72)와 금형의 캐비티 표면 사이로 봉지제(5)가 스며들어가서, 아우터 리드(22,72)의 밑면에 도포된다. 따라서, 기판에 직접 실장되어도 전기적 접속이 안되고, 솔더 볼(6)과도 전기적으로 연결되지 않게 되는 문제점이 자주 발생되었다.Since the conventional outer leads 22 and 72 are exposed, the encapsulant 5 penetrates between the outer leads 22 and 72 of the lead frame and the cavity surface of the mold, and thus the outer leads 22 and 72. It is applied to the underside of. Therefore, even when directly mounted on the substrate, there is often a problem that the electrical connection is not possible, and also the electrical connection with the solder ball (6).

따라서, 본 발명은 상기와 같은 문제점을 해소하기 위해 안출된 것으로서, 아우터 리드와 금형의 표면 사이로 봉지제가 스며들어가지 못하도록 하여, 기판 또는 솔더 볼과의 전기적 접속이 확실해지는 저면 리드형 패키지의 제조 방법을 제공하는데 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and prevents the encapsulant from penetrating between the outer lead and the surface of the mold, thereby ensuring the electrical connection with the substrate or the solder ball, the manufacturing method of the bottom lead type package. The purpose is to provide.

도 1은 종래의 LOC 타입의 저면 리드형 패키지를 나타낸 단면도1 is a cross-sectional view showing a bottom lead type package of a conventional LOC type.

도 2는 종래의 BGA 타입의 저면 리드형 패키지를 나타낸 단면도Figure 2 is a cross-sectional view showing a bottom lead type package of a conventional BGA type

도 3 및 도 4는 본 발명의 실시예 1에 따라 LOC 타입의 패키지에 본 발명을 적용한 것을 나타낸 단면도3 and 4 are cross-sectional views showing the application of the present invention to a LOC type package according to Embodiment 1 of the present invention.

도 5 내지 도 9 및 도 14는 본 발명의 실시예 2에 따라 BGA 타입의 패키지에 본 발명을 적용하여 제조하는 과정을 순차적으로 나타낸 단면도5 to 9 and 14 are cross-sectional views sequentially showing a process of applying the present invention to the package of the BGA type according to the second embodiment of the present invention

도 10 내지 도 12는 본 발명의 실시예 3에 따라 BGA 타입의 패키지에 본 발명을 적용하여 제조하는 과정을 순차적으로 나타낸 단면도10 to 12 are cross-sectional views sequentially showing a manufacturing process by applying the present invention to a package of the BGA type according to the third embodiment of the present invention

도 13은 본 발명의 실시예 4에 따른 형상의 테이프를 이용해서 패키지를 제조하는 과정을 나타낸 단면도13 is a cross-sectional view showing a process of manufacturing a package using a tape of the shape according to the fourth embodiment of the present invention

- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-

1 - 반도체 칩 2 - 리드 프레임1-semiconductor chip 2-lead frame

3 - 접착제 4 - 금속 와이어3-glue 4-metal wire

5 - 봉지제 6 - 솔더 볼5-encapsulant 6-solder balls

20,30,60,80 - 테이프 21 - 인너 리드20,30,60,80-Tape 21-Inner Lead

22 - 아우터 리드22-outer lead

상기와 같은 목적을 달성하기 위한 본 발명에 따른 패키지 제조 방법은 다음과 같은 단계로 이루어진다.Package manufacturing method according to the present invention for achieving the above object consists of the following steps.

먼저, 엘오씨 타입의 패키지는, 반도체 칩을 리드 프레임의 인너 리드상에 접착제로 부착하고, 인너 리드를 금속 와이어로 반도체 칩의 패드에 연결한다. 리드 프레임의 아우터 리드 밑면에로 봉지제가 침투하는 것을 방지하기 위해서, 아우터 리드 밑면에 절연 테이프를 부착하고, 전체가 봉지제로 몰딩한 후, 절연 테이프를 제거하면 아우터 리드가 봉지제에서 노출된다.First, in the package of an OC type, the semiconductor chip is attached to the inner lead of the lead frame with an adhesive, and the inner lead is connected to the pad of the semiconductor chip with a metal wire. In order to prevent the encapsulant from penetrating into the outer lead bottom of the lead frame, an insulating tape is attached to the bottom of the outer lead, the whole is molded with an encapsulant, and then the insulating tape is removed to expose the outer lead from the encapsulant.

볼 그리드 어레이 패키지는, 솔더 볼이 부착되는 랜드를 리드 프레임의 밑면에 형성하고, 이 랜드 주위에 절연 테이프를 부착한다. 리드 프레임의 인너 리드상에 반도체 칩을 접착제로 부착하고, 반도체 칩의 패드와 인너 리드를 금속 와이어로 연결한다. 전체가 봉지제로 몰딩하고, 솔더 볼이 랜드에 부착한다.The ball grid array package forms a land on which the solder ball is attached to the bottom of the lead frame, and attaches insulating tape around the land. The semiconductor chip is attached to the inner lead of the lead frame with an adhesive, and the pad and the inner lead of the semiconductor chip are connected with a metal wire. The whole is molded with encapsulant, and the solder balls adhere to the lands.

상기된 본 발명의 구성에 의하면, 봉지제로 몰딩하기 전에, 각 아우터 리드의 밑면, 또는 그 주위를 둘러싸게 절연 테이프를 부착하게 되므로써, 봉지제가 아우터 리드와 금형의 표면 사이로 스며들어갈 수가 없게 된다.According to the above-described configuration of the present invention, the insulating tape is attached to the underside of each outer lead or around the periphery of the outer lead before molding, so that the sealing agent cannot penetrate between the outer lead and the surface of the mold.

이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

<실시예 1><Example 1>

도 3 및 도 4는 본 발명의 실시예 1에 따라 LOC 타입의 패키지는 나타낸 단면도이다.3 and 4 are cross-sectional views showing packages of the LOC type according to the first embodiment of the present invention.

도 3에 도시된 바와 같이, 리드 프레임(2)의 인너 리드(21)상에 접착제(3)를 매개로 반도체 칩(1)을 부착한다. 반도체 칩(1)의 패드와 인너 리드(21)를 금속 와이어(4)로 연결한다.As shown in FIG. 3, the semiconductor chip 1 is attached onto the inner lead 21 of the lead frame 2 via the adhesive 3. The pad of the semiconductor chip 1 and the inner lead 21 are connected by a metal wire 4.

그런 다음, 리드 프레임(2)의 아우터 리드(22) 밑면에 절연 테이프(20)를 부착한다. 이러한 상태에서 전체를 금형의 캐비티내에 안치시켜서 봉지제(5)로 몰딩하게 되는데, 절연 테이프(20)가 금형의 표면에 밀착되기 때문에, 아우터 리드(22)와 금형의 표면 사이로 봉지제(5)가 스며들어가지 않게 된다. 절연 테이프(20)는 폴리이미드(polyimide) 계열의 폴리머로서, 그 두께는 10 내지 100㎛인 것이 바람직하다.Then, the insulating tape 20 is attached to the bottom surface of the outer lead 22 of the lead frame 2. In this state, the whole is placed in the cavity of the mold and molded into the encapsulant 5. Since the insulating tape 20 is in close contact with the surface of the mold, the encapsulant 5 is interposed between the outer lead 22 and the surface of the mold. Will not seep. The insulating tape 20 is a polyimide-based polymer, and the thickness thereof is preferably 10 to 100 µm.

봉지제(5)로 몰딩한 후에, 도 4와 같이 절연 테이프(20)를 식각하거나 또는 떼어내서 아우터 리드(22)를 노출시킨 다음, 아우터 리드(22)를 기판에 실장한다. 이때, 아우터 리드(22)의 솔더링시 접착력 강화를 위해서, 주석(Sn)과 납(Pb)의 혼합물, 팔라듐(Pd)와 니켈(Ni) 및 금(Au)의 혼합물, 구리(Cu)와 니켈 및 금의 혼합물, 구리와 니켈과 금 및 크롬의 혼합물, 구리와 니켈과 금과 코발트(Co)의 혼합물, 구리와 니켈과 금 및 티타늄질화물(Tin)의 혼합물, 구리와 니켈과 크롬과 금 및 티타늄질화막의 혼합물, 또는 구리와 니켈과 코발트와 금 및 티타늄질화막의 혼합물 중 하나를 아우터 리드(22)에 코팅하는 것이 바람직하고, 코팅 두께는 50 내지 300㎛ 정도인 것이 바람직하다.After molding with the encapsulant 5, the outer lead 22 is exposed by etching or removing the insulating tape 20 as shown in FIG. 4, and then the outer lead 22 is mounted on a substrate. At this time, in order to enhance the adhesive strength when soldering the outer lead 22, a mixture of tin (Sn) and lead (Pb), a mixture of palladium (Pd) and nickel (Ni) and gold (Au), copper (Cu) and nickel And mixtures of gold, mixtures of copper and nickel and gold and chromium, mixtures of copper and nickel and gold and cobalt (Co), mixtures of copper and nickel and gold and titanium nitride (Tin), copper and nickel, chromium and gold and It is preferable to coat the outer lead 22 with a mixture of a titanium nitride film or a mixture of copper, nickel, cobalt, gold and a titanium nitride film, and the coating thickness is preferably about 50 to 300 m.

여기서, 절연 테이프(20) 대신에 ACF(Anisotropic Conductive Film) 또는 ACA(Anisotropic Conductive Adhesive)과 같은 이방성 전도재를 사용하면, 몰딩 후에도 이방성 전도재를 통해 도통이 가능하므로, 떼어낼 필요가 없다.Here, if anisotropic conductive material such as anisotropic conductive film (ACF) or anisotropic conductive adhesive (ACA) is used instead of the insulating tape 20, conduction is possible through the anisotropic conductive material even after molding, so that it does not need to be removed.

또한, 반도체 칩(1)과 리드 프레임(2)의 인너 리드(21)를 부착시키는 접착제(3) 대신에 상기 이방성 전도재를 사용하면, 금속 와이어(4)로 와이어 본딩 공정을 할 필요도 없어지게 된다.In addition, when the anisotropic conductive material is used instead of the adhesive 3 for attaching the semiconductor chip 1 and the inner lead 21 of the lead frame 2, there is no need for a wire bonding step with the metal wire 4. You lose.

<실시예 2><Example 2>

본 실시예 2는 볼 그리드 어레이 타입의 패키지에 본 발명을 적용한 것으로서, 우선 도 5와 같이, 리드 프레임(7)의 인너 리드(71)상에 접착제(3)를 부착하고, 와이어 본딩할 부분과 솔더 볼이 부착될 부분인 랜드(31)를 제외한 리드 프레임(7)의 전체 밑면에 열경화성 수지인 절연 테이프(30)를 도포한다. 절연 테이프(30)는 도 13에 도시된 바와 같이, 볼 랜드(31) 주위를 둘러싸는 링 형상인 것이 바람직하다.In the second embodiment, the present invention is applied to a ball grid array type package. First, as shown in FIG. 5, the adhesive 3 is attached onto the inner lead 71 of the lead frame 7, and the portion to be wire-bonded and The insulating tape 30, which is a thermosetting resin, is applied to the entire bottom surface of the lead frame 7 except for the lands 31, to which the solder balls are to be attached. It is preferable that the insulating tape 30 has a ring shape surrounding the ball land 31, as shown in FIG. 13.

그런 다음, 접착제(3)상에 반도체 칩(1)을 탑재하고, 반도체 칩(1)과 인너 리드(71)를 금속 와이어(4)로 연결시키면 도 6와 같이 된다. 이때, 접착제(3) 대신에 도 7에 도시된 바와 같이, 이방성 전도재(40)를 사용하면, 이방성 전도재(40)를 통해 패드(11)와 인너 리드(71)가 연결되므로, 와이어 본딩 공정을 할 필요가 없어지게 된다.Then, the semiconductor chip 1 is mounted on the adhesive 3, and the semiconductor chip 1 and the inner lead 71 are connected with the metal wire 4, as shown in FIG. In this case, as shown in FIG. 7 instead of the adhesive 3, when the anisotropic conductive material 40 is used, the pad 11 and the inner lead 71 are connected through the anisotropic conductive material 40, so that wire bonding is performed. There is no need to do the process.

이어서, 도 8와 같이 전체를 금형(50)의 캐비티내에 위치시킨다. 이때는, 절연 테이프(30)가 캐비티의 저면에 밀착된다. 따라서, 봉지제(5)를 캐비티내로 플로우시킬 때, 봉지제(5)가 랜드(31)내로 스며들어가지 못하게 된다.Subsequently, the whole is located in the cavity of the metal mold | die 50 as shown in FIG. At this time, the insulating tape 30 is in close contact with the bottom of the cavity. Therefore, when the encapsulant 5 is flowed into the cavity, the encapsulant 5 cannot penetrate into the land 31.

최종적으로, 도 9와 같이, 각 랜드(31)에 솔더 볼(6)을 부착하면, 본 실시예 2에 따른 패키지가 완성된다.Finally, as shown in FIG. 9, when the solder balls 6 are attached to each land 31, the package according to the second embodiment is completed.

<실시예 3><Example 3>

위 실시예 2에서는 랜드를 제외한 리드 프레임(7) 전체에 절연 테이프(30)를 도포하였으나, 본 실시예 3에서는 랜드에 절연 테이프를 적용한 것이다.In the second embodiment, the insulating tape 30 is applied to the entire lead frame 7 except the land. In the third embodiment, the insulating tape is applied to the land.

즉, 도 10에 도시된 바와 같이, 절연 테이프(60)를 랜드(61) 부위에만 부착한다. 봉지제(5)로 몰딩한 후, 도 11과 같이 절연 테이프(60)를 떼어내면 랜드(61)가 노출되고, 이어서 도 12와 같이 각 랜드(61)에 솔더 볼(6)을 부착한다.That is, as shown in FIG. 10, the insulating tape 60 is attached only to the land 61. After molding with the encapsulant 5, the land 61 is exposed by removing the insulating tape 60 as shown in FIG. 11, and then solder balls 6 are attached to each land 61 as shown in FIG. 12.

여기서, 절연 테이프(60) 대신에 상기 이방성 전도재를 사용하면, 테이프 제거 공정을 하지 않아도 된다.If the anisotropic conductive material is used instead of the insulating tape 60, the tape removing step may not be performed.

한편, 실시예 2 및 3에서 노출된 볼 랜드에, 실시예 1과 같이 50 내지 300㎛ 정도의 두께로, 주석(Sn)과 납(Pb)의 혼합물, 팔라듐(Pd)와 니켈(Ni) 및 금(Au)의 혼합물, 구리(Cu)와 니켈 및 금의 혼합물, 구리와 니켈과 금 및 크롬의 혼합물, 구리와 니켈과 금과 코발트(Co)의 혼합물, 구리와 니켈과 금 및 티타늄질화물(Tin)의 혼합물, 구리와 니켈과 크롬과 금 및 티타늄질화막의 혼합물, 또는 구리와 니켈과 코발트와 금 및 티타늄질화막의 혼합물 중 하나를 아우터 리드(22)에 코팅하여, 솔더 볼(6)과의 접착력을 강화시키는 것이 바람직하다.On the other hand, in the ball land exposed in Examples 2 and 3, in the same thickness as in Example 1, a mixture of tin (Sn) and lead (Pb), palladium (Pd), nickel (Ni) and A mixture of gold (Au), a mixture of copper (Cu) and nickel and gold, a mixture of copper, nickel, gold and chromium, a mixture of copper, nickel, gold and cobalt (Co), copper, nickel, gold and titanium nitride ( Tin), a mixture of copper, nickel, chromium, gold, and titanium nitride, or a mixture of copper, nickel, cobalt, gold, and titanium nitride, is coated on the outer lead 22, and the solder balls 6 It is desirable to enhance the adhesion.

이상에서 설명한 바와 같이, 기판에 실장되거나 솔더 볼에 접촉되는 리드 프레임의 아우터 리드에 몰딩 전에 절연 테이프가 부착되므로써, 몰딩시 봉지제가 아우터 리드내로 스며드는 것이 방지된다. 따라서, 기판 또는 솔더 볼과 리드 프레임간의 전기적 접속이 확실해진다.As described above, the insulating tape is adhered to the outer lead of the lead frame mounted on the substrate or in contact with the solder balls before molding, thereby preventing the encapsulant from seeping into the outer lead during molding. Thus, the electrical connection between the substrate or the solder ball and the lead frame is assured.

이상에서는 본 발명에 의한 패키지를 실시하기 위한 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.In the above has been shown and described with respect to a preferred embodiment for carrying out the package according to the present invention, the present invention is not limited to the above embodiment, the invention without departing from the spirit of the invention claimed in the claims below Anyone with ordinary knowledge in this field will be able to implement various changes.

Claims (11)

반도체 칩의 밑면에 배치된 패드에 리드 프레임의 인너 리드를 전기적으로 연결한 후, 상기 리드 프레임의 아우터 리드가 저면으로 노출되도록 봉지제로 몰딩하여 이루어지는 저면 리드형 패키지 제조 방법에 있어서,In the method of manufacturing a bottom lead type package of the bottom lead type package formed by electrically connecting the inner lead of the lead frame to a pad disposed on the bottom surface of the semiconductor chip, and molding the outer lead of the lead frame with an encapsulant to expose the bottom lead. 상기 몰딩 공정 전에, 상기 봉지제가 아우터 리드 밑면으로 스며들지 못하도록, 상기 아우터 리드 밑면에 절연 테이프를 부착하고, 상기 몰딩 공정 후에, 상기 테이프를 제거하여 기판에 실장되는 아우터 리드를 노출시키는 공정을 추가로 포함하는 것을 특징으로 하는 저면 리드형 패키지 제조 방법.Before the molding process, attaching an insulating tape to the bottom of the outer lead to prevent the encapsulant from seeping into the bottom of the outer lead, and after the molding process, removing the tape to expose the outer lead mounted on the substrate. A method of manufacturing a bottom lead-type package, comprising: 제 1 항에 있어서, 상기 노출된 아우터 리드에 50 내지 300㎛ 정도의 두께로, 주석과 납의 혼합물, 팔라듐와 니켈 및 금의 혼합물, 구리와 니켈 및 금의 혼합물, 구리와 니켈과 금 및 크롬의 혼합물, 구리와 니켈과 금과 코발트의 혼합물, 구리와 니켈과 금 및 티타늄질화물의 혼합물, 구리와 니켈과 크롬과 금 및 티타늄질화막의 혼합물, 또는 구리와 니켈과 코발트와 금 및 티타늄질화막의 혼합물 중 하나를 코팅하는 것을 특징으로 하는 저면 리드형 패키지 제조 방법.The method of claim 1, wherein the exposed outer lead has a thickness of about 50 to 300 µm, the mixture of tin and lead, the mixture of palladium, nickel and gold, the mixture of copper, nickel and gold, and the mixture of copper, nickel, gold and chromium. , A mixture of copper and nickel and gold and cobalt, a mixture of copper and nickel and gold and titanium nitride, a mixture of copper and nickel and chromium and gold and titanium nitride, or a mixture of copper and nickel, cobalt and gold and titanium nitride The bottom lead type package manufacturing method characterized in that the coating. 제 1 항에 있어서, 상기 절연 테이프는 폴리머이고, 그의 두께는 10 내지 100㎛인 것을 특징으로 하는 저면 리드형 패키지 제조 방법.The method of claim 1, wherein the insulating tape is a polymer, the thickness of which is 10 to 100 µm. 반도체 칩의 밑면에 리드 프레임의 인너 리드를 전기적으로 연결한 후, 상기 리드 프레임의 아우터 리드가 저면으로 노출되도록 봉지제로 몰딩하여 이루어지는 저면 리드형 패키지 제조 방법에 있어서,In the method of manufacturing a bottom lead type package formed by electrically connecting the inner lead of the lead frame to the bottom surface of the semiconductor chip, and molding with an encapsulant so that the outer lead of the lead frame is exposed to the bottom surface. 상기 몰딩 공정 전에, 봉지제가 상기 아우터 리드 밑면으로 스며들지 못하도록, 상기 아우터 리드 밑면에 기판에 직접 실장이 가능한 이방성 전도재를 부착하는 공정을 추가로 포함하는 것을 특징으로 하는 저면 리드형 패키지 제조 방법.And a step of attaching an anisotropic conductive material directly mountable to a substrate on the bottom of the outer lead so that an encapsulant does not penetrate the bottom of the outer lead before the molding process. 리드 프레임을 반도체 칩의 밑면에 배치된 패드에 전기적으로 연결하고, 상기 리드 프레임의 밑면에 형성된 솔더 볼 랜드가 노출되도록 전체를 봉지제로 몰딩한 후, 상기 솔더 볼 랜드에 기판에 실장되는 솔더 볼을 부착하여 이루어지는 저면 리드형 패키지 제조 방법에 있어서,The lead frame is electrically connected to the pad disposed on the bottom surface of the semiconductor chip, and the whole is molded with an encapsulant so that the solder ball land formed on the bottom surface of the lead frame is exposed, and then the solder ball mounted on the solder ball land is mounted on the substrate. In the method of manufacturing the bottom lead type package by attaching, 상기 몰딩 공정 전에, 상기 봉지제가 솔더 볼 랜드로 스며들지 못하도록, 상기 리드 프레임 밑면에 절연 테이프를 부착하는 공정을 추가로 포함하는 것을 특징으로 하는 저면 리드형 패키지 제조 방법.And attaching an insulating tape to the underside of the lead frame to prevent the encapsulant from penetrating into the solder ball lands before the molding process. 제 5 항에 있어서, 상기 절연 테이프는 솔더 볼 랜드를 제외한 부분에만 부착하는 것을 특징으로 하는 저면 리드형 패키지 제조 방법.The method of claim 5, wherein the insulating tape is attached only to a portion excluding solder ball lands. 제 6 항에 있어서, 상기 절연 테이프는 솔더 볼 랜드의 주위를 둘러싸는 링 형상인 것을 특징으로 하는 저면 리드형 패키지 제조 방법.7. The method of claim 6, wherein the insulating tape has a ring shape surrounding the solder ball land. 제 5 항에 있어서, 상기 절연 테이프는 솔더 볼 랜드에 부착하고, 상기 몰딩 공정 후에 제거하는 것을 특징으로 하는 저면 리드형 패키지 제조 방법.6. The method of claim 5, wherein the insulating tape is attached to a solder ball land and removed after the molding process. 제 5 항, 제 7 항 또는 제 8 항 중 어느 한 항에 있어서, 상기 노출된 솔더 볼 랜드에 50 내지 300㎛ 정도의 두께로, 주석과 납의 혼합물, 팔라듐와 니켈 및 금의 혼합물, 구리와 니켈 및 금의 혼합물, 구리와 니켈과 금 및 크롬의 혼합물, 구리와 니켈과 금과 코발트의 혼합물, 구리와 니켈과 금 및 티타늄질화물의 혼합물, 구리와 니켈과 크롬과 금 및 티타늄질화막의 혼합물, 또는 구리와 니켈과 코발트와 금 및 티타늄질화막의 혼합물 중 하나를 코팅하는 것을 특징으로 하는 저면 리드형 패키지 제조 방법.9. A method according to any one of claims 5, 7, or 8, wherein the exposed solder ball land has a thickness of about 50 to 300 mu m, a mixture of tin and lead, a mixture of palladium, nickel and gold, copper and nickel and A mixture of gold, a mixture of copper and nickel and gold and chromium, a mixture of copper and nickel and gold and cobalt, a mixture of copper and nickel and gold and titanium nitride, a mixture of copper and nickel, chromium and gold and titanium nitride, or copper And coating one of a mixture of nickel, cobalt, gold, and a titanium nitride film. 제 5 항, 제 7 항 또는 제 8 항 중 어느 한 항에 있어서, 상기 절연 테이프는 폴리머이고, 그의 두께는 10 내지 100㎛인 것을 특징으로 하는 저면 리드형 패키지 제조 방법.The method of manufacturing a bottom lid type package according to any one of claims 5, 7, or 8, wherein the insulating tape is a polymer, and its thickness is 10 to 100 µm. 리드 프레임을 반도체 칩의 밑면에 배치된 패드에 전기적으로 연결하고, 상기 리드 프레임의 밑면에 형성된 솔더 볼 랜드가 노출되도록 전체를 봉지제로 몰딩한 후, 상기 솔더 볼 랜드에 기판에 실장되는 솔더 볼을 부착하여 이루어지는 저면 리드형 패키지 제조 방법에 있어서,The lead frame is electrically connected to the pad disposed on the bottom surface of the semiconductor chip, and the whole is molded with an encapsulant so that the solder ball land formed on the bottom surface of the lead frame is exposed, and then the solder ball mounted on the solder ball land is mounted on the substrate. In the method of manufacturing the bottom lead type package by attaching, 상기 몰딩 공정 전에, 상기 봉지제가 솔더 볼 랜드로 스며들지 못하도록, 상기 솔더 볼 랜드에 기판에 직접 실장이 가능한 이방성 전도재를 부착하고, 상기 몰딩 공정 후에, 상기 이방성 전도재에 솔더 볼을 직접 부착하는 공정을 추가로 포함하는 것을 특징으로 하는 저면 리드형 패키지 제조 방법.Before the molding process, attaching an anisotropic conductive material that can be directly mounted on the substrate to the solder ball land, so that the encapsulant does not penetrate into the solder ball land, and after the molding process, the solder ball directly attached to the anisotropic conductive material A method of manufacturing a bottom lead type package, further comprising the step.
KR1019980045446A 1998-10-28 1998-10-28 Method for manufacturing lower side leading type package KR20000027501A (en)

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