KR20000027494A - Method of forming metal wire of semiconductor device - Google Patents
Method of forming metal wire of semiconductor device Download PDFInfo
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- KR20000027494A KR20000027494A KR1019980045439A KR19980045439A KR20000027494A KR 20000027494 A KR20000027494 A KR 20000027494A KR 1019980045439 A KR1019980045439 A KR 1019980045439A KR 19980045439 A KR19980045439 A KR 19980045439A KR 20000027494 A KR20000027494 A KR 20000027494A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 고집적 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming metal wiring of a highly integrated semiconductor device.
반도체 소자의 제조기술이 향상되면서 고집적화 및 고속화가 급격히 진행되고 있다. 이에 따라, 배선설계가 자유롭고 배선저항 및 전류용량 등의 설정을 용이하게 할 수 있는 배선기술에 관한 연구가 활발히 진행되고 있다.As the manufacturing technology of semiconductor devices improves, high integration and high speed are rapidly progressing. Accordingly, researches on wiring technology that can freely design wiring and facilitate setting of wiring resistance and current capacity, etc., have been actively conducted.
이러한, 다층 금속배선 공정 중 상층 금속배선과의 극심한 단차를 감소시키면서 기판 표면을 평탄화하기 위하여 금속층간의 평탄화막으로서 SOG(Spin-On- Glass)를 사용한다. 이러한 SOG는 산소, 수소 및 탄소의 결합으로 이루어진 유기화합물로서, 유동성이 크고, 실록산 또는 실리케이트와 알콜용제로 구성된 액상물질로서, 절연층의 보이드를 제거할 수 있는 장점이 있을 뿐만 아니라, 공정이 간단하고 가격이 저렴하다.In order to planarize the substrate surface while reducing the extreme step with the upper metal wiring during the multilayer metal wiring process, spin-on-glass (SOG) is used as the planarization film between the metal layers. SOG is an organic compound composed of a combination of oxygen, hydrogen, and carbon, and has a high fluidity, a liquid substance composed of siloxane or silicate and an alcohol solvent, and has the advantage of removing voids from the insulating layer and a simple process. And the price is low.
도 1은 층간절연막으로서 상기한 SOG를 이용한 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a method for forming a metal wiring of a semiconductor device using SOG as the interlayer insulating film.
도 1을 참조하면, 절연막(11)이 형성된 반도체 기판(10) 상에 도전마 패턴(12)을 형성한다. 그런 다음, 기판 전면에 SOG막(13)을 형성하고, 도전막 패턴(12)의 표면이 노출되도록 SOG막(13)을 식각한다. 기판 전면에 층간절연막으로서 PE(Plasma Enhanced)-TEOS 산화막(14)을 형성하고 화학기계연마(Chemical Mechanical Polishing; CMP)로 그의 표면을 평탄화시킨다. 그런 다음, PE-TEOS 산화막(14) 상에 포토리소그라피로 포토레지스트막 패턴(미도시)을 형성하고, 상기 포토레지스트막 패턴을 식각 마스크로하여 도전막 패턴(12)의 일부가 노출되도록 PE-TEOS 산화막(14)을 식각하여 비아홀(15)을 형성한다. 그런 다음, 공지된 방법으로 마스크 패턴을 제거하고, 도시되지는 않았지만 비아홀(15)에 매립되도록 금속층을 증착하고 패터닝하여 도전막 패턴(12)과 콘택하는 배선을 형성한다.Referring to FIG. 1, the conductive hemp pattern 12 is formed on the semiconductor substrate 10 on which the insulating film 11 is formed. Then, the SOG film 13 is formed on the entire surface of the substrate, and the SOG film 13 is etched to expose the surface of the conductive film pattern 12. A Plasma Enhanced (TE) -TEOS oxide film 14 is formed as an interlayer insulating film on the entire surface of the substrate, and its surface is planarized by chemical mechanical polishing (CMP). Then, a photoresist film pattern (not shown) is formed on the PE-TEOS oxide film 14 using photolithography, and the PE-TEOS is exposed to a portion of the conductive film pattern 12 by using the photoresist pattern as an etching mask. The TEOS oxide layer 14 is etched to form via holes 15. Then, the mask pattern is removed by a known method, and although not shown, a metal layer is deposited and patterned so as to be embedded in the via hole 15 to form a wiring contacting the conductive film pattern 12.
한편, 0.25㎛의 디자인 룰에 의한 고집적 반도체 소자의 제조에서는 오버랩 마진(overlap margin)이 0이 된다. 이에 따라, 비아홀 형성을 위한 식각시, 층간절연막이 손상을 받거나 식각시 마스크로서 사용되는 포토레지스트막의 제거시 층간절연막이 악영향을 받게 된다. 또한, 배선 간격이 미세해짐에 따라, 내부 캐패시턴스(intra-capacitance)가 증가된다. 이러한 내부 캐패시턴스를 감소시키기 위하여, 층간 절연막으로서 상기한 바와 같은 저유전 상수를 가지는 SOG막(13)을 사용하였으나, PE-TEOS 산화막(14) 보다 높은 SOG막(13)의 식각률에 의해 도 1에 도시된 바와 같이, 비아홀(15)이 정확하게 한정(define)되지 않는다. 또한, SOG막(13)의 디게싱(degassing)으로 인한 비아홀의 보우잉(bowing)이 발생되어, 결국 배선의 신뢰성이 저하된다.On the other hand, in the fabrication of highly integrated semiconductor devices based on a 0.25 μm design rule, the overlap margin is zero. As a result, when the via hole is etched, the interlayer insulating film is damaged or when the photoresist film used as a mask is removed, the interlayer insulating film is adversely affected. In addition, as the wiring spacing becomes smaller, the intra-capacitance is increased. In order to reduce such internal capacitance, an SOG film 13 having a low dielectric constant as described above was used as the interlayer insulating film, but the etching rate of the SOG film 13 higher than that of the PE-TEOS oxide film 14 is shown in FIG. As shown, the via holes 15 are not precisely defined. In addition, bowing of the via holes due to degassing of the SOG film 13 occurs, resulting in lower reliability of the wiring.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 내부 캐패시턴스를 감소시키면서 비아홀을 정확하게 한정할 수 있는 고집적 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a highly integrated semiconductor device capable of accurately defining a via hole while reducing an internal capacitance.
도 1은 종래의 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]
20 : 반도체 기판 21 : 절연막20 semiconductor substrate 21 insulating film
22 : 도전막 패턴 23 : SOG막22: conductive film pattern 23: SOG film
23a : 경화된 SOG막 24 : PE-TEOS 산화막23a: cured SOG film 24: PE-TEOS oxide film
25 : 비아홀25: Via Hole
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속배선 형성방법은 도전막 패턴이 형성된 반도체 기판 상에 SOG막을 형성하는 단계; 도전막 패턴의 표면이 노출되도록 SOG막을 식각하는 단계; SOG막의 표면을 경화시키는 단계; 기판 전면에 층간 절연막을 형성하는 단계; 및, 도전막 패턴의 일부가 노출되도록 절연막을 식각하여 비아홀을 형성하는 단계를 포함한다.Method of forming a metal wiring of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an SOG film on a semiconductor substrate on which a conductive film pattern is formed; Etching the SOG film to expose the surface of the conductive film pattern; Curing the surface of the SOG film; Forming an interlayer insulating film over the entire substrate; And forming a via hole by etching the insulating film so that a portion of the conductive film pattern is exposed.
본 실시예에서, 경화시키는 단계는 전자빔 경화 또는 산소 플라즈마 경화로 진행한다. 여기서, 전자빔 경화는 5 내지 10KeV의 전자 에너지와, 5 내지 10 mA의 이온도스로 진행하고, 산소 플라즈마 경화는 0.5 내지 1.5KW의 전력과 10 내지 50KeV의 이온에너지와, 1 내지 5㎃의 이온도스와, 0.5 내지 1Torr의 압력에서 진행하는 것을 특징으로 한다.In this embodiment, the curing step proceeds to electron beam curing or oxygen plasma curing. Here, electron beam curing proceeds with an electron energy of 5 to 10 KeV, an ion dose of 5 to 10 mA, and oxygen plasma curing is an electric power of 0.5 to 1.5 KW and ion energy of 10 to 50 KeV, and an ion dose of 1 to 5 kV. And, it characterized in that it proceeds at a pressure of 0.5 to 1 Torr.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.2A through 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 절연막(21)이 형성된 반도체 기판(20) 상에 도전막 패턴(22)을 형성하고, 기판 전면에 SOG막(23)을 형성한다. 그런 다음, 도 2b에 도시된 바와 같이, 도전막 패턴(22)의 표면이 노출되도록 SOG막(23)을 식각하고, SOG막(23)의 표면을 전자빔(electron beam) 경화 또는 산소(O2) 플라즈마 경화로 경화(curing)시킴으로써 경화된 SOG막(23a)을 형성한다. 여기서, 전자빔 경화는 5 내지 10KeV의 전자 에너지와, 5 내지 10 mA의 이온도스로 진행한다. 또한, 산소 플라즈마 경화는 0.5 내지 1.5KW의 전력과 10 내지 50KeV의 이온에너지와, 1 내지 5㎃의 이온도스와, 0.5 내지 1Torr의 압력에서 진행한다. 즉, 산소 플라즈마 중의 산소이온의 운동에너지에 의해 SOG막(23) 내부의 탄화수소(hydrocarbon) 결합이 깨짐으로써 SOG막(23)의 표면이 경화된다.Referring to FIG. 2A, the conductive film pattern 22 is formed on the semiconductor substrate 20 on which the insulating film 21 is formed, and the SOG film 23 is formed on the entire surface of the substrate. Then, as shown in FIG. 2B, the SOG film 23 is etched to expose the surface of the conductive film pattern 22, and the surface of the SOG film 23 is electron beam cured or oxygen (O 2). ) The cured SOG film 23a is formed by curing by plasma curing. Here, electron beam curing proceeds with electron energy of 5 to 10 KeV and ion dose of 5 to 10 mA. In addition, oxygen plasma curing proceeds at a power of 0.5 to 1.5 KW, an ion energy of 10 to 50 KeV, an ion dose of 1 to 5 kW, and a pressure of 0.5 to 1 Torr. That is, the hydrocarbon bond inside the SOG film 23 is broken by the kinetic energy of oxygen ions in the oxygen plasma, thereby hardening the surface of the SOG film 23.
도 2c를 참조하면, 도 2b의 구조 상에 층간절연막으로서 PE-TEOS 산화막(24)을 형성하고, CMP로 그의 표면을 평탄화시킨다. 그런 다음, PE-TEOS 산화막(24) 상에 포토리소그라피로 포토레지스트막 패턴(미도시)을 형성한다. 상기 포토레지스트막 패턴을 식각 마스크로 하여 도전막 패턴(12)의 일부가 노출되도록 PE-TEOS 산화막(24)을 식각하여 비아홀(25)을 형성한다. 이때, 경화된 SOG막(23a)은 경화되지 않은 SOG막(23)에 비해 식각률이 낮기 때문에, 비아홀(25)을 정확하게 한정하는 것이 용이해진다.Referring to FIG. 2C, a PE-TEOS oxide film 24 is formed as an interlayer insulating film on the structure of FIG. 2B, and its surface is planarized with CMP. Then, a photoresist film pattern (not shown) is formed on the PE-TEOS oxide film 24 by photolithography. The via-holes 25 are formed by etching the PE-TEOS oxide layer 24 so that a portion of the conductive layer pattern 12 is exposed using the photoresist layer pattern as an etching mask. At this time, since the etch rate of the cured SOG film 23a is lower than that of the uncured SOG film 23, it is easy to accurately define the via hole 25.
그런 다음, 공지된 방법으로 마스크 패턴을 제거하고, 도시되지는 않았지만, 비아홀(25)에 매립되도록 금속층을 증착하고 패터닝하여 도전막 패턴(22)과 콘택하는 배선을 형성한다.Then, the mask pattern is removed by a known method, and although not shown, a metal layer is deposited and patterned so as to be embedded in the via hole 25 to form a wiring contacting the conductive film pattern 22.
상기한 본 발명에 의하면, 저유전상수를 가지는 SOG막(23)의 표면을 전자빔 또는 산소 플라즈마를 이용하여 경화시킴으로써, PE-TEOS 산화막에 대한 식각률이 감소되어 정확한 비아홀의 한정이 용이해진다. 또한, 저유전상수를 가지는 SOG막에 의해 내부 캐패시턴스가 효과적으로 감소됨으로써, 결국 배선의 신뢰성이 향상된다.According to the present invention described above, by hardening the surface of the SOG film 23 having a low dielectric constant by using an electron beam or an oxygen plasma, the etching rate with respect to the PE-TEOS oxide film is reduced, so that it is easy to define accurate via holes. In addition, the internal capacitance is effectively reduced by the SOG film having a low dielectric constant, which in turn improves the reliability of the wiring.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
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| US10461027B2 (en) | 2018-02-07 | 2019-10-29 | Samsung Electronics Co., Ltd. | Semiconductor device including via plug and method of forming the same |
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| JPS6473729A (en) * | 1987-09-16 | 1989-03-20 | Matsushita Electric Ind Co Ltd | Formation of thin film |
-
1998
- 1998-10-28 KR KR10-1998-0045439A patent/KR100365424B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10461027B2 (en) | 2018-02-07 | 2019-10-29 | Samsung Electronics Co., Ltd. | Semiconductor device including via plug and method of forming the same |
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| Publication number | Publication date |
|---|---|
| KR100365424B1 (en) | 2003-03-31 |
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