KR20000027445A - Method of manufacturing gate of semiconductor device - Google Patents
Method of manufacturing gate of semiconductor device Download PDFInfo
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- KR20000027445A KR20000027445A KR1019980045376A KR19980045376A KR20000027445A KR 20000027445 A KR20000027445 A KR 20000027445A KR 1019980045376 A KR1019980045376 A KR 1019980045376A KR 19980045376 A KR19980045376 A KR 19980045376A KR 20000027445 A KR20000027445 A KR 20000027445A
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- gate
- insulating film
- side wall
- insulating layer
- wall insulating
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법 및 그 구조에 관한 것으로, 특히 반도체 장치의 게이트 제조 방법 및 그 구조에 관한 것이다.TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device and a structure thereof, and more particularly to a method for manufacturing a gate and a structure of a semiconductor device.
일반적으로 반도체 장치는, 다양한 도전층들과 상기 도전층 사이에 존재하며 상기 도전층들 사이에 존재하는 절연층 및 그 외 여러층으로 구성된다. 특히 상기 절연막은 도전층과 도전층 사이를 절연시키는 절연막으로서, 그리고 고립된 소자 영역을 다른 물질막으로부터 보호하기 위한 보호막으로서 기능할 뿐 아니라 그 외 다양한 용도에 사용되므로 반도체 장치를 제조함에 있어 매우 중요한 물질막중의 하나라고 할 수 있다. 특히 모오스(MOS:Metal Oxide Silicon) 소자의 LDD(Light Doper Drain) 구조를 형성하기 위해 통상적으로 게이트 전극 주변에 열산화막(thermal oxide) 또는 질화막을 이용하여 측벽절연막을 형성하게 되는데, 이러한 측벽절연막의 사이즈는 모오스 소자의 문턱전압, 포화전류 및 여러 가지 동작 특성을 결정짓게 되는 매우 중요한 파라미터로 작용한다.In general, a semiconductor device is composed of an insulating layer and various other layers present between various conductive layers and the conductive layer and between the conductive layers. In particular, the insulating film serves as an insulating film that insulates the conductive layer from the conductive layer, and serves as a protective film for protecting the isolated device region from other material films, and is used in various other applications. It can be said to be one of the material films. In particular, in order to form a light doper drain (LDD) structure of a MOS (Metal Oxide Silicon) device, a sidewall insulating film is typically formed around a gate electrode by using a thermal oxide film or a nitride film. Size is a very important parameter that determines the threshold voltage, saturation current and various operating characteristics of the MOSFET.
그러나 최근 반도체 장치가 고집적화됨에 따라, 디자인룰이 감소되고 있으며, 이에 따라 상기한 모오스 트랜지스터의 게이트 영역의 임계치수(Critical Dimension) 또한 감소되고 있다. 이처럼 게이트 영역의 임계치수가 감소하게 되면, 후속의 금속 콘택(metal contact) 또는 다이렉트 콘택(direct contact)을 형성하는 과정에서 게이트 영역과의 접촉면적이 감소되어 저항이 증가되는 결과를 낳게된다.However, as semiconductor devices have recently been highly integrated, design rules have decreased, and accordingly, the critical dimensions of the gate regions of the MOS transistors have also decreased. As such, when the critical dimension of the gate region is reduced, the contact area with the gate region is reduced in the process of forming a subsequent metal contact or direct contact, resulting in an increase in resistance.
도 1은 종래 방법에 따라 제조된 모오스 트랜지스터의 게이트 단면도이다.1 is a gate cross-sectional view of a MOS transistor manufactured according to a conventional method.
도면을 참조하면, 반도체 기판 100 상에 게이트 절연막 102 및 다결정 실리콘막으로 이루어진 게이트 전극 104이 형성되어 있다. 그리고, 상기 게이트 절연막 102및 게이트 전극 104 영역의 양 측벽에는 질화막(SiN)으로 이루어진 측벽절연막 106이 형성되어 있다. 상기와 같은 게이트 전극 104 상부에 후속의 공정에서 금속 콘택 또는 다이렉트 콘택을 형성하고자 할 경우에, 도면에 도시되어 있는 바와 같이 단지 "A"영역만이 접촉하게 되므로 저항이 증가하게 된다.Referring to the drawing, a gate electrode 104 made of a gate insulating film 102 and a polycrystalline silicon film is formed on a semiconductor substrate 100. The sidewall insulating layer 106 made of a nitride film SiN is formed on both sidewalls of the gate insulating layer 102 and the gate electrode 104. In the case where a metal contact or a direct contact is to be formed in a subsequent process on the gate electrode 104 as described above, as shown in the drawing, only the "A" region comes into contact, thereby increasing the resistance.
따라서 본 발명의 목적은, 게이트 전극과 콘택과의 접촉면적을 증가시킬 수 있는 측벽절연막 제조 방법 및 그 구조를 제공함에 있다.Accordingly, an object of the present invention is to provide a method and a structure for manufacturing a sidewall insulating film which can increase the contact area between the gate electrode and the contact.
상기 목적을 달성하기 위하여 본 발명은, 반도체 장치의 게이트 측벽절연막 제조 방법에 있어서: 반도체 기판의 소정 영역에 게이트 영역을 형성한 뒤, 상기 게이트 영역이 형성되어 있는 상기 반도체 기판 전면 상부에 측벽절연막 제조를 위한 절연막을 증착하는 단계와; 상기 게이트 영역의 최상부에서 일정 간격 떨어진 위치에서부터 반도체 기판에 이르는 측벽절연막이 형성되도록 상기 절연막에 에치백 공정을 실시하는 단계를 포함함을 특징으로 하는 방법을 제공한다.SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for manufacturing a gate sidewall insulating film of a semiconductor device, comprising: forming a gate region in a predetermined region of a semiconductor substrate, and then manufacturing a sidewall insulating film over an entire surface of the semiconductor substrate on which the gate region is formed. Depositing an insulating film for; And performing an etch back process on the insulating film to form a sidewall insulating film extending from a predetermined distance from the top of the gate region to the semiconductor substrate.
도 1은 종래 방법에 따라 제조된 모오스 트랜지스터의 게이트 단면도이다.1 is a gate cross-sectional view of a MOS transistor manufactured according to a conventional method.
도 2a 내지 도 2b는 본 발명의 제 1실시예에 따른 게이트 제조 방법을 설명하기 위한 단면도들이다.2A to 2B are cross-sectional views illustrating a gate manufacturing method according to a first embodiment of the present invention.
도 3은 본 발명의 제 2실시예에 따른 게이트 제조 방법을 설명하기 위한 단면도이다.3 is a cross-sectional view for describing a gate manufacturing method according to a second exemplary embodiment of the present invention.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2b는 본 발명의 제 1실시예에 따른 게이트 제조 방법을 설명하기 위한 단면도들이다.2A to 2B are cross-sectional views illustrating a gate manufacturing method according to a first embodiment of the present invention.
먼저, 도 2a를 참조하면, 기판 200 상에 산화막 및 다결정 실리콘을 차례로 형성한 후 패터닝하여 게이트 산화막 202 및 게이트 전극 204을 형성한다. 이때, 상기 게이트 전극 204 상부에는 예컨대, 티타늄(Ti), 코발트(Co) 또는 텅스텐(W)과 같은 고용융점(high melting point) 금속을 이용하여 실리사이드막을 더 형성할 수도 있다.First, referring to FIG. 2A, an oxide film and polycrystalline silicon are sequentially formed on a substrate 200 and then patterned to form a gate oxide film 202 and a gate electrode 204. In this case, a silicide layer may be further formed on the gate electrode 204 by using a high melting point metal such as titanium (Ti), cobalt (Co), or tungsten (W).
계속해서, 상기 게이트 산화막 202 및 게이트 전극 204이 형성되어 있는 반도체 기판 200 전면 상부에 질화막을 약 200∼300Å 두께로 형성한 뒤, 전면 에치백공정을 실시한다. 이때, 상기 질화막은 MERIE 타입의 식각장비내에서 식각하며, 식각에천트로서는 질화막과 산화막의 식각선택비가 약 2:1로 낮은 CF4와 O2로 이루어진 혼합가스를 이용하는 것이 바람직하다. 그 결과, 상기 게이트 전극 204의 최상부로부터 일정간격(C1,C2) 떨어진 영역에서 반도체 기판 200에 이르는 제1측벽절연막 206이 형성된다.Subsequently, a nitride film is formed on the upper surface of the semiconductor substrate 200 on which the gate oxide film 202 and the gate electrode 204 are formed to have a thickness of about 200 to 300 占 퐉, and then a front etch back process is performed. In this case, the nitride film is etched in a MERIE type etching equipment, and as the etching etchant, it is preferable to use a mixed gas composed of CF 4 and O 2 having a low etch selectivity between the nitride film and the oxide film at about 2: 1. As a result, a first side wall insulating film 206 extending from the top of the gate electrode 204 to the semiconductor substrate 200 in a region spaced a predetermined distance (C1, C2) is formed.
도 2b를 참조하면, 상기 반도체 기판 200에 상기 제1측벽절연막 206을 형성하기 위한 공정과 동일한 방법으로 제2측벽절연막 208을 형성한다. 그 결과, 상기 제1측벽절연막 206 상부에는 제2측벽절연막 208이 형성되어 전체적인 측벽절연막의 두께는 제1측벽절연막 206과 제2측벽절연막 208을 합한 두께가 되나, 전체적인 측벽절연막의 높이는 처음 형성된 제1측벽절연막 206의 높이와 동일하다. 그러므로, 후속의 공정에서 상기 게이트 전극 204의 상부에 금속 콘택 또는 다이렉트 콘택을 형성할 경우 전체적인 접촉면적은 모두 게이트 전극 상부(B)및 측벽절연막이 형성되지 않은 일부 측벽(C1,C2)이 되므로, 종래에 비해 접촉저항이 감소되는 장점이 있다.Referring to FIG. 2B, a second side wall insulating film 208 is formed on the semiconductor substrate 200 in the same manner as the process for forming the first side wall insulating film 206. As a result, a second side wall insulating film 208 is formed on the first side wall insulating film 206 so that the overall thickness of the side wall insulating film is the sum of the first side wall insulating film 206 and the second side wall insulating film 208, but the height of the entire side wall insulating film is first formed. It is equal to the height of the one side wall insulating film 206. Therefore, when the metal contact or the direct contact is formed on the gate electrode 204 in the subsequent process, the entire contact area becomes both the gate electrode B and the sidewalls C1 and C2 where the sidewall insulating film is not formed. Compared with the prior art, the contact resistance is reduced.
도 3은 본 발명의 제 2실시예에 따른 게이트 제조 방법을 설명하기 위한 단면도이다.3 is a cross-sectional view for describing a gate manufacturing method according to a second exemplary embodiment of the present invention.
도면을 참조하면, 반도체 기판 300 상부에 게이트 산화막 302 및 다결정 실리콘막으로 이루어진 게이트 전극 304을 형성한다. 이어서, 상기 반도체 기판 300에 질화막을 약 500∼600Å 두께로 증착한 뒤, 전면 에치백 공정을 실시한다. 이때, 상기 질화막은 상기 제1실시예에서와는 달리 TCP 타입의 식각장비내에서 식각하는 바람직하며, 또한 식각에천트로서는 질화막과 산화막의 식각선택비가 약 5:1의 높은 비율을 가지는 SF6, O2, CF4 및 HBr로 이루어진 혼합가스를 이용하는 것이 바람직하다. 그 결과, 상기 게이트 전극 204의 최상부로부터 일정간격(E1,E2) 떨어진 영역에서 반도체 기판 300에 이르는 측벽절연막 306이 형성된다.Referring to the drawing, a gate electrode 304 including a gate oxide film 302 and a polycrystalline silicon film is formed on the semiconductor substrate 300. Subsequently, a nitride film is deposited on the semiconductor substrate 300 to a thickness of about 500 to 600 GPa, and then a full etch back process is performed. In this case, unlike the first embodiment, the nitride film is preferably etched in a TCP type etching equipment, and as an etching etchant, SF6, O2, CF4 having an etch selectivity ratio of the nitride film and the oxide film having a high ratio of about 5: 1. And it is preferable to use a mixed gas consisting of HBr. As a result, a sidewall insulating film 306 extending from the top of the gate electrode 204 to the semiconductor substrate 300 in a region spaced a predetermined distance (E1, E2) is formed.
상기와 같은 방법으로 측벽절연막 306을 형성하게 되면, 후속의 공정에서 상기 게이트 전극 304의 상부에 금속 콘택 또는 다이렉트 콘택을 형성할 경우 전체적인 접촉면적은 게이트 전극 상부(D)및 측벽절연막이 형성되지 않은 일부 측벽(E1,E2)이 되므로 종래에 비해 접촉저항이 감소되는 장점이 있음은 물론, 상기 제1실시예에 비해 공정이 단순해지는 잇점을 가진다.When the sidewall insulating layer 306 is formed in the same manner as described above, when the metal contact or the direct contact is formed on the gate electrode 304 in a subsequent process, the overall contact area of the gate electrode D and the sidewall insulating layer is not formed. Since there are some sidewalls (E1, E2) there is an advantage that the contact resistance is reduced compared to the conventional, as well as the process is simpler than the first embodiment.
상술한 바와 같이 본 발명에 따르면, 반도체 장치의 게이트 영역 측벽에 측벽절연막을 형성함에 있어서, 상기 게이트 영역의 최상부로부터 일정간격 떨어진 위치에서부터 반도체 기판에 이르도록 측벽절연막을 형성한다. 그 결과, 후속의 공정에서 상기 게이트 영역에 콘택을 형성할 경우, 게이트 영역과 콘택의 접촉면적은 측벽절연막이 형성되지 않은 전체 면적이 되므로 게이트 영역과 콘택과의 접촉저항이 보다 감소되는 효과가 있다.As described above, according to the present invention, in forming the sidewall insulating film on the sidewall of the gate region of the semiconductor device, the sidewall insulating film is formed from the position spaced apart from the top of the gate region to the semiconductor substrate. As a result, when a contact is formed in the gate region in a subsequent step, the contact area between the gate region and the contact becomes the total area where the sidewall insulating film is not formed, thereby reducing the contact resistance between the gate region and the contact. .
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045376A KR20000027445A (en) | 1998-10-28 | 1998-10-28 | Method of manufacturing gate of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045376A KR20000027445A (en) | 1998-10-28 | 1998-10-28 | Method of manufacturing gate of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000027445A true KR20000027445A (en) | 2000-05-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980045376A KR20000027445A (en) | 1998-10-28 | 1998-10-28 | Method of manufacturing gate of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000027445A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100935770B1 (en) * | 2007-11-26 | 2010-01-06 | 주식회사 동부하이텍 | Semiconductor device and method of fabricating the same |
-
1998
- 1998-10-28 KR KR1019980045376A patent/KR20000027445A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100935770B1 (en) * | 2007-11-26 | 2010-01-06 | 주식회사 동부하이텍 | Semiconductor device and method of fabricating the same |
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