KR20000027094A - Method for defect analysis of semiconductor - Google Patents
Method for defect analysis of semiconductor Download PDFInfo
- Publication number
- KR20000027094A KR20000027094A KR1019980044928A KR19980044928A KR20000027094A KR 20000027094 A KR20000027094 A KR 20000027094A KR 1019980044928 A KR1019980044928 A KR 1019980044928A KR 19980044928 A KR19980044928 A KR 19980044928A KR 20000027094 A KR20000027094 A KR 20000027094A
- Authority
- KR
- South Korea
- Prior art keywords
- metal wiring
- protective film
- metal wire
- laser beam
- defective
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
Abstract
Description
본 발명은 반도체 소자의 제조공정에 있어서 금속배선의 불량분석 방법에 관한 것으로, 특히 금속배선 상의 보호막 특정 부위만을 레이저빔으로 선택적으로 식각하여 불량배선을 용이하게 분석할 수 있도록 한 반도체 소자의 불량분석 방법에 관한 것이다.The present invention relates to a defect analysis method of the metal wiring in the manufacturing process of the semiconductor device, in particular defect analysis of the semiconductor device to easily analyze the defective wiring by selectively etching only a specific portion of the protective film on the metal wiring with a laser beam. It is about a method.
일반적으로, 반도체 소자의 제조 공정에 있어서 발생되는 불량들은 틈(vacancy)들이 모여져 금속배선에 보이드를 형성하고 금속배선의 저항을 증가시켜 발생되는 저항증가에 의한 불량과 보호막의 막질이 없거나 과(over) 스트레스를 인가할 때 보이드와 힐록이 동시에 생성되어 발생되는 금속배선의 노출에 의한 불량 등이 있다.In general, defects generated in the manufacturing process of a semiconductor device are formed by voids forming voids in the metal wires and increasing resistance of the metal wires. ) When the stress is applied, voids and heel locks are generated at the same time.
이러한 불량들을 분석하는 불량분석 방법 중에서의 보호막 제거기술은 반응성 이온식각(reactive ion etching : RIE)법을 이용하여 반도체기판 또는 패키지 상의 보호막이나 몰드 컴파운드(mold compound)를 제거하였으며, 보호막 또는 몰드 컴파운드를 제거하는 과정에서 발생되는 오염방지를 위하여 패키지와 반도체기판을 따로 구별하여 사용하였다.Among the defect analysis methods for analyzing these defects, the protective film removing technology removes the protective film or mold compound on the semiconductor substrate or the package by using reactive ion etching (RIE), and removes the protective film or mold compound. In order to prevent contamination generated during the removal process, the package and the semiconductor substrate were separately used.
그러나, 반응성 이온식각법을 이용하여 금속배선 상의 보호막을 제거하는 기술에는 다음과 같은 문제점이 발생된다.However, the following problem arises in the technique of removing the protective film on the metallization using reactive ion etching.
첫째, RIE 챔버에 투입된 식각대상이 전체적으로 식각되므로 식각 대상의 특정 부분만이 선택적으로 식각될 수 없다.First, since the etching target injected into the RIE chamber is etched as a whole, only a specific portion of the etching target cannot be selectively etched.
둘째, 식각공정을 진행할 때의 식각 조건들, 예컨대 식각할 층의 두께와 밀도, 에천트(etchant)의 에너지 및 온도, 감광막의 접착성 및 웨이퍼 표면의 상태에 따라 식각비가 달라지게 되므로 정확한 식각공정이 진행될 수 없다.Second, since the etching ratio depends on the etching conditions during the etching process, for example, the thickness and density of the layer to be etched, the energy and temperature of the etchant, the adhesion of the photoresist film, and the state of the wafer surface, the etching process is accurate. This can't proceed.
세째, RIE 챔버 내부의 오염상태에 따라 식각 대상이 손상을 받으므로 불량분석할 시료를 손상시키게 된다.Third, since the etching target is damaged according to the contamination state inside the RIE chamber, the sample to be analyzed is damaged.
네째, 반도체칩의 패턴이 미세화되고 금속배선의 증가로 인하여 금속배선에 손상을 가하게 되어 금속배선의 불량분석이 어렵게 된다.Fourth, due to the miniaturization of the pattern of the semiconductor chip and the increase of the metal wiring, the metal wiring is damaged, making it difficult to analyze the defects of the metal wiring.
따라서, 상기와 같은 문제점들이 발생되어 금속배선의 불량분석 작업을 할 때 RIE 설비를 이용하지 않고 수작업으로 불량으로 예상되는 금속배선 부위의 보호막이나 몰드 컴파운드를 제거하고 주사형 전자현미경(SEM)을 이용하여 금속배선의 불량분석 작업을 진행함으로써 금속배선의 불량 상태를 보다 정밀하게 분석할 수 없었다.Therefore, when the above problems are generated and the defect analysis of the metal wiring is performed, the protective film or the mold compound of the metal wiring portion that is expected to be defective is manually removed without using the RIE facility and the scanning electron microscope (SEM) is used. As a result of the failure analysis of the metal wiring, it was not possible to analyze the defective state of the metal wiring more precisely.
상기한 문제점을 해결하기 위한 본 발명의 목적은 금속배선의 특정부위를 레이저빔으로 선택적으로 식각하여 불량으로 예상되는 금속배선의 특정부위를 종래 보다 정밀하게 분석하도록 한 반도체 소자의 불량분석 방법을 제공하는 데 있다.DISCLOSURE OF THE INVENTION An object of the present invention for solving the above problems is to provide a method for analyzing a defect of a semiconductor device, by selectively etching a specific portion of the metal wiring with a laser beam to analyze a specific portion of the metal wiring, which is expected to be defective, more precisely than before. There is.
도 1은 본 발명에 따른 반도체 소자의 불량분석 방법을 도시한 도면1 is a view showing a failure analysis method of a semiconductor device according to the present invention
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 반도체기판 12 : 금속배선10: semiconductor substrate 12: metal wiring
14 : 보호막 16 : 레이저총14: shield 16: laser gun
상기한 목적을 달성하기 위하여 본 발명에 따른 반도체 소자의 불량분석 방법은In order to achieve the above object, the failure analysis method of a semiconductor device according to the present invention
반도체기판 상에 형성되는 다층의 금속배선 중에 불량으로 예상되는 금속배선의 손상없이 상기 금속배선 상의 보호막을 레이저빔으로 선택적으로 식각하여 금속배선의 특정부위에 대한 불량 분석을 실시함을 특징으로 한다.In the multi-layered metal wiring formed on the semiconductor substrate, the protective film on the metal wiring is selectively etched with a laser beam without damaging the metal wiring, which is expected to be defective, to perform a defect analysis on a specific portion of the metal wiring.
상기와 같은 반도체 소자의 불량분석 방법에 따르면, 금속배선의 특정 부위에 대한 불량분석을 레이저빔을 이용한 선택적 식각공정에 의해 종래 보다 금속배선의 불량을 정밀하게 분석할 수 있다.According to the failure analysis method of the semiconductor device as described above, by the selective etching process using a laser beam failure analysis for a specific portion of the metal wiring can be analyzed more precisely than the defects of the metal wiring than conventional.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 불량분석 방법을 상세하게 설명하면 다음과 같다.Hereinafter, a failure analysis method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 반도체 소자의 불량분석 방법을 도시한 도면이다.1 is a view showing a failure analysis method of a semiconductor device according to the present invention.
먼저, 반도체기판(10) 상에 하부구조물(도시 안됨)로써, 예컨대 소자분리막과, 모스트랜지스터, 저장전극 및, 캐패시터 등을 형성한 다음 단위 소자를 보호하기 위하여 막질이 우수한 층간절연막(도시안됨)을 적층한다.First, as a substructure (not shown) on the semiconductor substrate 10, for example, an element isolation layer, a MOS transistor, a storage electrode, a capacitor, and the like are formed. Laminated.
이어서, 상기 층간절연막 상에 반도체칩의 용도에 따른 다층의 금속배선(12)을 형성한 다음 금속배선(12)의 전면을 감싸는 보호막(14) 또는 절연막(도시 안됨)을 형성한다.Subsequently, a multi-layered metal wiring 12 is formed on the interlayer insulating film, and then a protective film 14 or an insulating film (not shown) covering the entire surface of the metal wiring 12 is formed.
그 후, 도 1에 도시된 바와 같이 금속배선(12)의 불량상태를 분석하기 위하여 다층의 금속배선(12) 중에서 불량으로 예상되는 금속배선(12) 상의 보호막(14)을 레이저총(16)으로부터 발사된 레이저빔에 의해 선택적으로 식각하여 금속배선(12)의 특정부위에 대한 불량 분석을 실시한다.After that, as shown in FIG. 1, the protective film 14 on the metal wiring 12, which is expected to be defective among the multilayer metal wirings 12, is analyzed in order to analyze the failure state of the metal wiring 12. By selectively etching by the laser beam emitted from the laser beam to perform a defect analysis on a specific portion of the metal wiring (12).
이 때, 식각 대상의 특정 부위만을 제거할 수 있는 레이저의 특성을 이용하여 레이저의 파장과 출력을 조절함으로써 레이저빔에 의해 불량으로 예상되는 금속배선(12)에 전혀 손상을 가하지 않고 금속배선(12) 상의 보호막(14)을 선택적으로 식각할 수 있다.At this time, by adjusting the wavelength and the output of the laser by using the characteristics of the laser that can remove only a specific portion of the target to be etched, without any damage to the metal wiring 12 that is expected to be defective by the laser beam (12) The protective film 14 on the () can be selectively etched.
따라서, 종래에는 불량으로 예상되는 금속배선의 특정 부위에 대한 불량분석 작업은 거의 수작업에 의해 원시적으로 이루어졌지만 본 발명에서와 같이 레이저빔을 이용하여 금속배선의 불량 상태로 예상되는 부분을 상의 보호막을 선택적으로 식각함으로써 금속배선의 불량을 보다 정밀하게 분석할 수 있다.Therefore, in the past, the defect analysis on a specific part of the metal wiring which is supposed to be defective was almost done by hand, but as in the present invention, a protective film on the portion of the metal wiring which is expected to be in a bad state was used using a laser beam. By selectively etching, defects in the metal wiring can be analyzed more precisely.
이상에서와 같이 본 발명에 따르면, 금속배선의 특정 부위(불량으로 예상되는 배선부분)에 대한 불량분석을 위해 레이저빔을 이용한 식각공정에 의해 불량으로 예상되는 금속배선 상의 보호막을 선택적으로 식각함으로써 종래 불량으로 예상되는 금속배선 상의 보호막을 수작업으로 제거하여 금속배선의 불량 상태를 분석하는 방법 보다 금속배선의 손상없이 금속배선의 특정 부위에 대한 불량 상태를 정밀하게 분석할 수 있다.As described above, according to the present invention, by selectively etching the protective film on the metal wiring, which is expected to be defective by an etching process using a laser beam, for the failure analysis on a specific portion of the metal wiring (the wiring portion that is expected to be defective). It is possible to analyze the defect condition of a specific part of the metal wiring more precisely without damaging the metal wiring than the method of analyzing the defective state of the metal wiring by manually removing the protective film on the metal wiring expected to be defective.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980044928A KR20000027094A (en) | 1998-10-27 | 1998-10-27 | Method for defect analysis of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980044928A KR20000027094A (en) | 1998-10-27 | 1998-10-27 | Method for defect analysis of semiconductor |
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| Publication Number | Publication Date |
|---|---|
| KR20000027094A true KR20000027094A (en) | 2000-05-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980044928A KR20000027094A (en) | 1998-10-27 | 1998-10-27 | Method for defect analysis of semiconductor |
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| KR (1) | KR20000027094A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112614808A (en) * | 2020-12-17 | 2021-04-06 | 中国电子科技集团公司第十三研究所 | Etching method of thin film metal layer and etching structure of thin film metal layer |
-
1998
- 1998-10-27 KR KR1019980044928A patent/KR20000027094A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112614808A (en) * | 2020-12-17 | 2021-04-06 | 中国电子科技集团公司第十三研究所 | Etching method of thin film metal layer and etching structure of thin film metal layer |
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