KR20000026966A - Method for preventing oxidation of lower conductive layer generated from oxidation process of capacitor dielectric layer - Google Patents
Method for preventing oxidation of lower conductive layer generated from oxidation process of capacitor dielectric layer Download PDFInfo
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- KR20000026966A KR20000026966A KR1019980044735A KR19980044735A KR20000026966A KR 20000026966 A KR20000026966 A KR 20000026966A KR 1019980044735 A KR1019980044735 A KR 1019980044735A KR 19980044735 A KR19980044735 A KR 19980044735A KR 20000026966 A KR20000026966 A KR 20000026966A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 230000003647 oxidation Effects 0.000 title abstract description 22
- 238000007254 oxidation reaction Methods 0.000 title abstract description 22
- 239000003990 capacitor Substances 0.000 title abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 38
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 15
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 10
- 239000003989 dielectric material Substances 0.000 abstract description 8
- 239000005368 silicate glass Substances 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008961 swelling Effects 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 고집적 메모리 소자 제조 방법에 관한 것으로, 특히 Si3N4/Oxide(N/O)를 캐패시터 유전물질로 사용하는 고 직접 메모리 소자에 있어서 N/O막의 산화 공정에서 발생할 수 있는 실리콘 웨이퍼 하부 산화를 방지하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a highly integrated memory device, and particularly to a silicon wafer lower part that may occur in an oxidation process of an N / O film in a high direct memory device using Si 3 N 4 / Oxide (N / O) as a capacitor dielectric material. A method for preventing oxidation.
일반적으로, 소자의 집적도가 증가할수록, 캐패시터 저장 노드에 할당된 면적이 감소하게 된다. 결국, 소자동작에 충분한 충전용량을 확보하기 위하여는 첫째, 유전상수가 큰 물질 사용하거나, 저장 노드의 표면적을 증가시키거나, 셋째, 유전체의 두께를 감소시켜야 한다. 따라서 256M이상의 Si3N4/Oxide를 유전물질로 사용하는 고집적 메모리 소자에 있어서 충분한 충전용량을 확보하기 위하여 N/O의 질화막 즉, Si3N4의 두께를 감소시켜야 한다.In general, as the degree of integration of a device increases, the area allocated to the capacitor storage node decreases. As a result, in order to ensure sufficient charge capacity for device operation, first, a material having a high dielectric constant, or increasing the surface area of the storage node, or third, reducing the thickness of the dielectric. Therefore, in order to secure sufficient charge capacity in a highly integrated memory device using more than 256M of Si 3 N 4 / Oxide as a dielectric material, it is necessary to reduce the thickness of the nitride film of N / O, that is, Si 3 N 4 .
도 1은 폴리실리콘막과 폴리실리콘막 사이를 절연하는 층간절연막이 형성되는 메모리 소자의 일례를 도시한 것으로, 셀지역과 주변회로지역의 간단한 구조를 보여주고 있다. 또한, 도면에서 도면부호 1은 반도체 기판, 2는 게이트 전극, 3 및 5는 증간절연막, 4는 비트라인, 6은 전하저장노드를 각각 나타낸다.FIG. 1 illustrates an example of a memory device in which an interlayer insulating film is formed between the polysilicon film and the polysilicon film, and shows a simple structure of a cell region and a peripheral circuit region. In the drawings, reference numeral 1 denotes a semiconductor substrate, 2 a gate electrode, 3 and 5 an extra insulation film, 4 a bit line, and 6 a charge storage node.
도면에 도시된 바와 같이, 폴리실리콘막으로 이루어진 게이트 전극(2)과 비트라인(4) 각각을 상부 및 하부의 다른 폴리실리콘막과 절연을 시키기 위하여 PSG(phosphorous silicate glass), BPSG(borophosphorous silicate glass), MTO(middle temperature oxide) 또는 PE-TEOS(plasma enhanced tetraethylortho silicate glass)를 사용하고 있다.As shown in the figure, in order to insulate each of the gate electrode 2 and the bit line 4 made of a polysilicon film from other polysilicon films in the upper and lower portions thereof, phosphorous silicate glass (PSG) and borophosphorous silicate glass (BPSG) ), MTO (middle temperature oxide) or PE-TEOS (plasma enhanced tetraethylortho silicate glass) is used.
그러나, 고집적 메모리 소자에 있어서 충전용량을 증가시키기 위하여 상기 전하저장노드에 증착되는 질화막의 두께를 감소시키게 되면, 층간절연막에 위치하는 질화막의 두게 역시 감소하여 N/O 공정의 산화 분위기에서 발생되는 산소가 하부의 층간 절연막을 투과하여 그 하부에 비트라인 또는 기타 다른 폴리실리콘막을 산화시키게 된다.However, when the thickness of the nitride film deposited on the charge storage node is reduced in order to increase the charge capacity in the high-density memory device, the thickness of the nitride film positioned in the interlayer insulating film is also reduced, and oxygen generated in the oxidizing atmosphere of the N / O process is reduced. Penetrates the lower interlayer insulating film and oxidizes a bit line or other polysilicon film thereunder.
도 2는 층간절연막으로 BPSG + MTO, 도 3은 층간절연막으로 BPSG + PE-TEOS를 사용한 구조에서 금속콘택이 형성되는 주변회로 지역이 산화되어 실리콘 하부가 부풀어오르고, 마치 버즈비크(Bird's Beak)와 같이 산화현상이 발생한 것을 보여준다. 이 현상은 MTO 및 PE-TEOS의 두께를 100∼3000Å까지 변화한 경우에도 모두 발생하며, 이들 층간절연막 자체는 두께에 관계없이 산소의 충분한 베리어 역할을 하지 못한다.2 is a BPSG + MTO as an interlayer insulating film, Figure 3 is a BPSG + PE-TEOS structure of the peripheral circuit area where the metal contact is formed in the structure is oxidized swelling the bottom of the silicon, as if Burd's Beak (Bird's Beak) It shows that oxidation occurred. This phenomenon occurs even when the thickness of the MTO and PE-TEOS is changed from 100 to 3000Å, and these interlayer insulating films themselves do not function as a sufficient barrier of oxygen regardless of the thickness.
결국, 질화막의 두께가 감소함에 따라 N/O 산화공정에서의 질화막이 산소의 베리어역할을 충분히 수행하지 못하게 되어 실리콘 하부 웰(well)지역이 산화되는 현상이 발생한다. 특히, 그 하부 지역에 금속콘택이 형성되어 있을 경우 접촉저항의 증가로 인하여 소자가 제대로 동작하지 않는 문제점이 유발된다.As a result, as the thickness of the nitride film decreases, the nitride film in the N / O oxidation process does not sufficiently perform the role of oxygen, and thus a phenomenon in which the silicon well region is oxidized. In particular, when a metal contact is formed in the lower region thereof, a problem arises that the device does not operate properly due to an increase in contact resistance.
따라서, 상기 문제점을 해결하기 위하여 안출된 본 발명은 캐패시터의 유전막으로 사용되는 N/O의 산화공정시 산소 침투로 인하여 그 하부에 형성된 다른 층의 산화를 방지 함으로써 소자의 신뢰도를 향상시키는 산화 방지 방법을 제공하는 데 그 목적이 있다.Accordingly, the present invention devised to solve the above problems is an oxidation prevention method for improving the reliability of the device by preventing the oxidation of the other layer formed thereunder due to oxygen infiltration during the oxidation process of N / O used as the dielectric film of the capacitor The purpose is to provide.
도 1은 폴리실리콘막과 폴리실리콘막 사이를 절연하는 층간절연막이 형성되는 메모리 소자의 일례를 도시한 도면,1 is a view showing an example of a memory device in which an interlayer insulating film is formed between the polysilicon film and the polysilicon film;
도 2는 종래의 층간절연막(BPSG + MTO)을 사용한 구조에서 금속콘택이 형성되는 주변회로지역의 산화를 도시한 도면,2 is a view showing oxidation of a peripheral circuit region where a metal contact is formed in a structure using a conventional interlayer insulating film (BPSG + MTO),
도 3은 종래의 층간절연막(BPSG + PE-TEOS)을 사용한 구조에서 금속콘택이 형성되는 주변회로지역의 산화를 도시한 도면,3 is a view showing oxidation of a peripheral circuit region in which a metal contact is formed in a structure using a conventional interlayer insulating film (BPSG + PE-TEOS),
도 4는 본 발명에 따른 질소가 풍부한 SiON막을 층간절연막으로 사용한 주변회로지역의 실리콘 하부 모양을 나타낸 도면.Figure 4 is a view showing the bottom of the silicon in the peripheral circuit region using a nitrogen-rich SiON film according to the present invention as an interlayer insulating film.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1: 반도체 기판 2: 게이트 전극1: semiconductor substrate 2: gate electrode
3,5: 증간절연막 4: 비트라인3,5: interlayer insulating film 4: bit line
6: 전하저장노드6: charge storage node
본 발명에서는 산소의 베리어 역할을 할 수 있는 층간절연막으로 질소를 풍부하게 함유하는 SiON막을 형성하거나, 이온주입을 통하여 PE-TEOS, TEOS, MTO등의 산화막내부로 질소를 침투시켜 산소가 투과하지 못하도록 함으로써 하부의 실리콘 산화 현상을 방지한다.In the present invention, to form a SiON film rich in nitrogen as an interlayer insulating film that can act as a barrier of oxygen, or to penetrate nitrogen into the oxide film such as PE-TEOS, TEOS, MTO through ion implantation so that oxygen does not permeate. This prevents the silicon oxidation phenomenon of the lower part.
또한, 본 발명은 반도체 메모리 소자의 층간절연막 제조 방법에 있어서, 층간을 절연하는 층간절연막을 형성하는 제 1 단계; 및 상기 층간절연막에 질소를 주입하여 질소가 풍부한 절연막으로 형성하는 제 2 단계를 포함한다.In addition, the present invention provides a method for manufacturing an interlayer insulating film of a semiconductor memory device, comprising: a first step of forming an interlayer insulating film for insulating an interlayer; And a second step of forming nitrogen-rich insulating film by injecting nitrogen into the interlayer insulating film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
먼저, 본 발명의 일 실시예에서는 이하의 공정 조건을 통해 층간절연막 SiON막을 100Å∼3000Å 증착한다.First, in an embodiment of the present invention, an interlayer insulating film SiON film is deposited from 100 kV to 3000 kV through the following process conditions.
1) 소스가스: SiH450∼100sccm, N2O 100∼300sccm, NH30∼300sccm;1) source gas: SiH 4 50-100 sccm, N 2 O 100-300 sccm, NH 3 0-300 sccm;
2) He 또는 N2캐리어 가스: 1500∼3000sccm;2) He or N 2 carrier gas: 1500-3000 sccm;
3) 챔버내 압력: 200 mTorr∼10 Torr;3) pressure in chamber: 200 mTorr-10 Torr;
4) 챔버내 샤워 헤드와 웨이퍼 척 거리: 5∼20mm;4) In-chamber shower head and wafer chuck distance: 5-20 mm;
5) 챔버온도: 상온 또는 500℃이하;5) Chamber temperature: below room temperature or 500 ° C;
6) 소스가스의 플라즈마 형성 RF: 50∼500W6) Plasma Formation of Source Gas RF: 50 ~ 500W
또한, 본 발명의 다른 일 실시예에서는 이하의 공정 조건을 통해 층간절연막에 질소를 이온주입 함으로써 산화 방지막을 형성한다. 특히, MTO, TEOS, PE-TEOS, HDP 또는 BPSG등의 층간절연막에 1∼10KeV의 에너지로 1×1014∼1×1016이온/cm-3의 질소를 주입한다.In another embodiment of the present invention, an oxide film is formed by ion implanting nitrogen into the interlayer insulating film through the following process conditions. In particular, nitrogen of 1 × 10 14 to 1 × 10 16 ions / cm −3 is injected into an interlayer insulating film such as MTO, TEOS, PE-TEOS, HDP, or BPSG at an energy of 1 to 10 KeV.
도 4는 질소가 풍부한 SiON막을 사용한 BPSG + SiON으로 구성된 층간절연막 구조에서 N/O 산화공정을 진행하였을 경우의 주변회로지역의 실리콘 하부 모양을 나타낸 것이다. 도면에서 보듯이 도 2와 도 3과는 달리 실리콘 하부로 부풀어오르는 현상도 발생하지 않았으며, 버즈비크모양도 생겨나지 않았음을 알 수 있다. .FIG. 4 shows the bottom surface of silicon in the peripheral circuit area when the N / O oxidation process is performed in the interlayer insulating film structure composed of BPSG + SiON using a nitrogen-rich SiON film. As shown in the figure, unlike in Figures 2 and 3 did not occur swelling to the bottom of the silicon, it can be seen that the appearance of the Buzz beak. .
또한, 유전체 바로 하부에 위치한 층간절연막을 MTO, TEOS, PE-TEOS 및 BPSG중 어느하나 또는 이들중 적어도 두 층이 적층된 막으로 형성한 후 질소를 주입시켜 비정질 상태의 층간절연막을 형성한 후 750℃ 이상의 열공정, 또는 850℃∼1050℃ 20초 정도의 RTP공정을 거치게 하면, N/O 산화공정에서 질화막을 투과한 산소의 확산을 방지할 수 있다. 이때 질소 주입량은 1×1014이상으로 하고 이온주입 에너지는 1∼5KeV로 한다.In addition, after forming an interlayer insulating layer directly under the dielectric as one of MTO, TEOS, PE-TEOS, and BPSG or at least two of them, nitrogen is injected to form an amorphous interlayer insulating layer. When the heat treatment is performed at a temperature higher than or equal to C or a RTP process at about 850 ° C to 1050 ° C for about 20 seconds, diffusion of oxygen that has passed through the nitride film in the N / O oxidation step can be prevented. At this time, the nitrogen injection amount is 1 × 10 14 or more and the ion implantation energy is 1-5KeV.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 층간절연막에 질소가 풍부한 산화막을 형성함으로써 ONO 유전막과 같은 캐패시터 유전체 산화 공정에서 하부의 실리콘산화를 방지함으로써, ONO의 질화막 두께를 감소시킬 수 없는 한계를 극복할 수 있다. 따라서 유전물질로 사용하는 질화막의 두께를 감소시킴으로써 충분한 충전용량을 확보할 수 있다.The present invention can overcome the limitation that the thickness of the nitride film of ONO can not be reduced by forming a nitrogen-rich oxide film in the interlayer insulating film, thereby preventing the silicon oxidation of the lower portion in the capacitor dielectric oxidation process such as the ONO dielectric film. Therefore, it is possible to secure sufficient charging capacity by reducing the thickness of the nitride film used as the dielectric material.
Claims (7)
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