KR20000025297A - Synchronous time-sharing variable encoder - Google Patents

Abstract

PURPOSE: An encoder is provided to simplify a structure to reduce complicated operations by minimizing interface signals and by separating time to read or write data from or to a video buffer. CONSTITUTION: A block variable encoder(10) zigzag-scans inputted data, determines a level of a coefficient value, and stores a code value with respect to a macro block. A slicer(30) slices the inputted macro block data, inputs a synchronizing signal, and outputs a vertical synchronizing signal. A code packing part(40) packs slice header data inputted from the slicer(30) and the block data. A picture header production part(50) produces and adds picture header information to the data packed from the code packing part(40) according to the vertical synchronizing signal.

Description

Synchronous time division variable coding device

The present invention relates to the compression of video information, and more particularly, to a synchronous time division variable encoding apparatus using an entropy encoding method according to a bias of a code generation probability.

In general, a method of compressing image information includes a method of using spatial correlation in a screen using a discrete cosine transform (DCT), a method of using correlation between screens, and an entropy encoding method according to a bias of a code occurrence probability. There is a way.

However, conventionally, there is no device implementing the entropy encoding method according to the probability of occurrence of a code.

Accordingly, the present invention has been proposed to solve the above-mentioned general problems, and an object of the present invention is to provide a synchronous time division variable encoding apparatus using an entropy encoding method according to a bias of a code generation probability.

Synchronous time division variable encoding apparatus according to the present invention in order to achieve the above object,

A block variable encoding unit for zigzag-scanning the input data, determining a level that is a coefficient value, and storing a code value for the macroblock; A slicer for receiving and slicing macroblock data of the block variable encoder and outputting a vertical synchronization signal by receiving a synchronization signal; A code packing unit for packing slice header data and block data inputted from the slicer; A picture header generator for generating and adding picture header information to the data packed by the code packing unit according to the vertical synchronization signal of the slicer; A VBV RAM storing VBV data of the picture header generator; Technical features of the present invention include a VBV RAM control and output unit which controls the VBV RAM to read data of the VBV RAM and outputs fixed bit rate data.

1 is a block diagram of a synchronous time division variable encoding apparatus according to the present invention;

FIG. 2 is a block diagram of a block variable encoder of FIG. 1;

3 is a timing diagram of a synchronization and vertical signal input in FIG. 2;

4 is an overall timing diagram for one image shown in FIG. 2;

5 is an overall timing diagram for one macroblock in FIG.

6 is a detailed block diagram of the VBV RAM control and output unit in FIG.

<Explanation of symbols for the main parts of the drawings>

10: block variable encoding unit 30: slicer

40: code packing unit 50: picture header generation unit

60: VBV RAM 70: VBV RAM Control and Output

Hereinafter, with reference to the accompanying drawings an embodiment according to the technical idea of the present invention synchronous time division variable coding apparatus as described above in detail.

First, the variable coding targets are DCT coefficients and additional information of an image. Therefore, in the present invention, in order to effectively encode these coefficients and additional information, a synchronization signal is set to operate according to the synchronization signal, thereby minimizing the complexity of the operation by minimizing the interface signals between the respective implementation blocks. In addition, the structure is simplified by dividing the data writing time and the reading time into a video buffer which stores the encoded data and outputs the encoded data at a fixed bit rate.

1 is a block diagram of a synchronous time division variable coding apparatus according to the present invention.

As shown therein, the block variable encoding unit 10 zigzag-scans the input data, determines a level which is a coefficient value, and stores a code value for the macroblock; A slicer (30) for receiving and slicing macroblock data of the block variable encoding unit (10) and receiving a synchronous signal and outputting a vertical synchronous signal; A code packing unit (40) for packing slice header data and block data input from the slicer (30); A picture header generator (50) for generating and adding picture header information to the data packed by the code packer (40) according to the vertical synchronization signal of the slicer (30); A VBV RAM (60) for storing VBV data of the picture header generator (50); The VBV RAM 60 is configured to read the data of the VBV RAM 60 and to output fixed bit rate data, and includes a VBV RAM control and output unit 70.

FIG. 2 is a block diagram of the block variable encoder 10 of FIG. 1.

As shown therein, a plurality of SCANs 11 each zigzag-scan the inputted block data and count the number of zeros between nonzero coefficients to determine a level that is a run and a nonzero coefficient value; A plurality of variable length coders (15) for determining code values and code sizes by allocating code values for each valid run and level in data input from the plurality of SCANs (11); A plurality of packing units 19 for packing codes received from the plurality of variable length code units 15 into predetermined bits; A plurality of FIFOs (23) for storing the data packed by the plurality of packing units (19) for reading by the slicer (30); A macroblock header generator 27 for receiving a macroblock additional information and generating a header; A packing unit 28 for packing data output to the macroblock header generation unit 27; It consists of a FIFO (29) for storing the additional information of the macroblock packed in the packing unit 28 to be stored in the slicer 30 to read.

3 is a timing diagram of synchronization and vertical signals input to the block variable encoder 10, FIG. 4 is an overall timing diagram for one image, and FIG. 5 is an overall timing diagram for one macroblock.

6 is a detailed block diagram of the VBV RAM control and output unit 70 in FIG.

As shown in the figure, a write address control unit 71 which receives a write response signal of VBV and controls to write VBV data to the VBV RAM 60; A read address control unit 72 which receives the vertical synchronization signal from the slicer 30 and controls to read data from the VBV RAM 60 during a read time in synchronization with 1 MB time; A VBV buffer 73 for storing control commands of the write address control unit 71 and the read address control unit 72; A buffer (74) for storing VBV data of the VBV RAM (60) in accordance with a control command stored in the VBV buffer (73); A serial / parallel converter 75 which receives serial clocks and converts them in parallel to generate an output clock; A ReadVBV control unit (76) which determines the number of data to be read by reading the number of data remaining in the buffer (74) according to the parallel clock of the serial / parallel conversion unit (75) and controls to read as many as this number; A 32/8 converter 77 converts 32 bits of data of the VBV RAM 60 read by the ReadVBV controller 76 into 8 bits to output data having a fixed bit rate.

The operation of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, one image may be hierarchically composed of Picture / Slice / Macro Block / Block. A block is composed of data of 8x8 pixels, and four blocks, that is, 16x16 pixels of data, are referred to as a macro block (MB). In fact, at 1MB, 4 blocks are luminance data, and there are 2 (4: 2: 0) or 4 (4; 2: 2) or 8 (4: 4: 4) data blocks for chrominance. do.

Therefore, in case of 4: 2: 0, the number of blocks per MB is 6.

Slice is also defined as a collection of several MBs. For example, when the size of an image is 1920 × 1088, one slice is composed of 120 MB, and one picture is composed of 68 slices. Multiple images are collected to form a GOP (Group Of Picture).

Therefore, in the present invention, the start signal of MC / Slice / Picture / GOP is defined as a synchronization signal. The timing diagram of these synchronization signals is shown by the SYNC signal of FIG. SYNC [0] is MB Start, SYNC [1] is Slice Start, SYNC [2] is Picture Start, and SYNC [3] is GOP Start. The input signal assumes that the SYNC signal and the image coefficient data are synchronized with each other.

In addition, 128 clocks are allocated to process one MB of data. Therefore, the MB Start signal always occurs every 128 clocks. One block requires 64 clocks, so two blocks of data can be processed for 128 clocks.

Therefore, three paths are required in parallel to encode six block data of one MB during 128 clocks. Thus, in the input of Fig. 1, three block data are simultaneously input. Figure 2 changes the input data from Raster Scan to Zigzag scan and counts the number of zeros between nonzero coefficients of this data to determine the level of run and nonzero coefficient values.

Thus, the variable length coder 15 of FIG. 2 assigns a code value to each valid run and level to determine code and code size. The 32-bit packing unit 19 packs the received code into 32 bits and stores the received code in the FIFO 23.

In FIG. 1, the FIFO with reference numeral 24 stores block variable encoded data for DCM [0], the FIFO with reference numeral 25 stores block variable encoded data for DCM [1], and the FIFO with reference numeral 26. Stores block variable coded data for DCM [2]. Based on the MB Start, the code value for one MB is stored in the FIFOs 24 through 26 every 128 clocks.

The data representing one MB must process the additional information of the MB in addition to the block data of the three paths described above. This additional information is carried in the MBPARM [12] input to the macroblock header generation unit (MB Head) 27. This data represents information corresponding to that MB every 128 clocks. Thus, the macroblock header generation unit 27, the 32-bit packing unit 28, and the FIFO 29 make an MB header using additional information for each MB and store the MB header in the FIFO 29. Here, the macroblock header generation unit 27 creates an MB header bitstream using the information of the MBParm.

The slicer 30 receives the SYNC [4] signal, which is a synchronization signal, to generate a VSYNC [4], which is a vertical synchronization signal. VSYNC is a synchronization signal that is readjusted in order to process Picture Header, Slice Header, MB Header, and Block data. The timing diagram of VSYNC is shown in FIG. In FIG. 3, VSYNC [0] is an MB Start signal, VSYNC [1] is a Slice Start signal, VSYNC [2] is a Picture Start signal, and VSYNC [3] is a GOP Start signal. In FIG. 3, VSYNC [1] is delayed by 1MB time because 1MB of time is allocated to the GOP / Picture Header, and VSYNC [1] and next VSYNC [1] are allocated because 1MB of time is allocated to the Slice Header for each slice. The time interval between SYNC [1] and the next SYNC [1] adds 1 MB of time.

The overall timing assignment structure for one area is shown in FIG. Thus, during the MB data time, the slicer 30 sequentially reads block data from the FIFOs 24-26 and 29. The time allocated for each block for 1MB data time is shown in FIG. In FIG. 5, three clocks are allocated to read the MB header from the FIFOs 24-26 (29) and write them to the VBV (Video Buffering Verifier) RAM 60, and writes each block data to the FIFOs 24-26. 20 clocks per block, that is, 120 clocks in the case of 6 blocks, is allocated to read from the (29).

The reason why the time divided by writing and reading data from the 128 clock allocated to 1MB to the VBV RAM 60 is divided into the VBV RAM 60 because the SRAM (Static Random Access Memory) is used. Since the bus is shared, you have no choice but to split it. If you want to be able to write and read at the same time, you need to use FIFO or DPSRAM (Dual Port SRAM). Since FIFO or DPSRAM is not large, it is a relatively complicated structure.

The slicer 30 generates a slice header in addition to the operation of generating the VSYNC. Then, the 32-bit code packer 40 packs the slice header data and the block data into 32 bits, and the picture header generator 50 generates the picture header. This causes the picture header to occur in 32 bits, so there is no need to pack it. In addition, the VBV RAM control and output unit 70 reads data from the VBV RAM 60.

On the other hand, in the VBV RAM control and output unit 70, the write address control unit 71 receives VBVWrReq, which is a write response signal of VBV, to write VBV data to the VBV RAM 60, and the read address control unit 72 It receives VSYNC and synchronizes 1 MB of time to read data from the VBV RAM 60 during the double read time. At this time, the number of readings among the maximum 5 clocks determines the number of readings by the readVBV control unit 76 based on the number remaining in the buffer 74 of 32 × 5 and reads this value by the number of readings.

In addition, the serial / parallel converter 75 receives a serial clock and converts in parallel to generate an output clock. The 32/8 conversion unit 77 converts the 32-bit data read from the VBV RAM 60 into 8-bit and outputs the converted 8-bit data.

Therefore, the maximum possible bit rate when allocating 5 clocks as data output is possible up to 5 × 32 × 120 × 68 × 30 = 39168000 for 1920 × 1088 video.

Therefore, as shown in FIG. 4, the structure is simplified by sequentially generating the MB image in synchronization with MB Start in order of Picture Header-Slice Header-MB Header-Block data. In addition, by dividing the time for writing and reading data into the VBV RAM 60, the SRAM can be sufficiently implemented.

As described above, the present invention can configure a synchronous time division variable encoding apparatus using an entropy encoding method according to a bias of a code generation probability.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the apparatus for synchronizing time division variable coding according to the present invention operates to match the synchronization signal by setting a synchronization signal in order to effectively encode coefficients and additional information of a macroblock, thereby minimizing an interface signal between each block. The complexity of the operation can be reduced, and the structure can be simplified by dividing the data writing time and the reading time into a video buffer that stores the encoded data and outputs the encoded data at a fixed bit rate.

Claims (5)

A block variable encoding unit for zigzag-scanning the input data, determining a level that is a coefficient value, and storing a code value for the macroblock; A slicer for receiving and slicing macroblock data of the block variable encoder and outputting a vertical synchronization signal by receiving a synchronization signal; A code packing unit for packing slice header data and block data inputted from the slicer; A picture header generator for generating and adding picture header information to the data packed by the code packing unit according to the vertical synchronization signal of the slicer; A VBV RAM storing VBV data of the picture header generator; And a VBV RAM control and output unit for controlling the VBV RAM to read data of the VBV RAM and output fixed bit rate data. The method of claim 1, wherein the block variable encoder, A plurality of SCANs for zigzag scanning input block data and counting the number of zeros between nonzero coefficients to determine a level that is a run and a nonzero coefficient value; A plurality of variable length coders for allocating code values for each valid run and level from data input from the plurality of SCANs to determine code values and code sizes; A plurality of packing parts for respectively packing codes received from the plurality of variable length code parts with predetermined bits; A plurality of FIFOs for storing the data packed by the plurality of packing units to be read by the slicer; A macroblock header generation unit configured to receive additional information of the macroblock and generate a header; A packing unit for packing data output to the macroblock header generation unit; And a FIFO for storing the additional information of the macroblock packed by the packing unit so as to be read by the slicer. The method of claim 1, wherein the block variable encoder, In order to encode six block data which is one macroblock during 128 clocks, three paths are set in parallel to simultaneously store block-variable encoded data, and additional information of the macroblock is simultaneously stored together with the block-variable encoded data. A synchronous time division variable encoding apparatus, characterized in that. The method of claim 1, wherein the slicer, The vertical synchronous signal created by receiving the sync signal is readjusted to process Picture Header, Slice Header, MB Header, and Block data in order, and the vertical synchronous signal for processing the Slice Header is delayed by 1 macroblock for the slice. The time interval between the vertical synchronous signal for processing the header and the vertical synchronous signal for processing the next Slice Header is one macroblock time compared to the synchronous signal for processing the Slice Header and the synchronous signal for processing the next Slice Header. A synchronous time division variable encoding apparatus characterized by the above-mentioned. The method of claim 1, wherein the VBV RAM control and output unit, A write address control unit which receives a write response signal of VBV and controls VBV data to be written to the VBV RAM; A read address control unit which receives a vertical synchronization signal from the slicer and controls to read data from the VBV RAM during a read time in synchronization with 1 MB; A VBV buffer for storing control commands of the write address control unit and the read address control unit; A buffer for storing VBV data of the VBV RAM according to a control command stored in the VBV buffer; A serial / parallel converter configured to receive a serial clock and convert it in parallel to generate an output clock; A ReadVBV control unit configured to determine the number of data to be read by reading the number of data remaining in the buffer according to the parallel clocks of the serial / parallel conversion unit, and to control the number of data to be read by the number; And a 32/8 conversion unit for converting 32-bit data of the VBV RAM read by the ReadVBV control unit into 8-bit and outputting a fixed bit rate data.