KR20000022714A - Error correction system, error correction method, and data memory with error correction function - Google Patents

Abstract

PURPOSE: A data memorizing system is provided to manage the error correction in a high speed by reducing the time required at transmitting the data and to effectively improve usage of the first buffer memory device by memorizing the syndrome in the area which is not used. CONSTITUTION: A system comprises a DVD(11), a motor(12), a reading head(13), a reading circuit(16), a digital server processor(18), a formator(20), a DRAM buffer(22), SRAM buffer(24), a decoder(26), a syndrome former(28, 38), an error correcting circuit(30), an MPU(32), and a data bus(36). The syndrome former is placed between the former and the DRAM buffer(22). The syndrome former receives ECC block sequentially from the former(20) and sends the received ECC block to the DRAM buffer(22) and forms the syndrome corresponding to the ECC block. The DRAM buffer sends only the syndrome to the SRAM buffer(24). The SRAM buffer sends the syndrome received from the DRAM buffer to the decoder(26). The error correction circuit inside the decoder manages the error in direction on the basis of received syndrome from the SRAM buffer.

Description

ERROR CORRECTION SYSTEM, ERROR CORRECTION METHOD, AND DATA MEMORY WITH ERROR CORRECTION FUNCTION}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction system and a data storage system having an error correction function. More specifically, the present invention relates to data in an error correction system using an error correction code in the form of a multiplication code as shown in a digital versatile disk (DVD). The present invention relates to a technique for shortening the time required for an error correction process by increasing transmission efficiency.

A DVD represented by an optical disc generally uses an error correction technique using an error correction code in the form of a multiplication code, and a reed-solomon code is used as the error correction code. Fig. 1 shows a basic data format using an error correcting code in a multiplication code format. The data bytes are arranged in k1 rows x k2 columns. As is known, a row error correction code called a PI code (Parity-Inner Code) or an inner code is given in the row (horizontal) direction, and a PO code (Parity-Outer Code) or in the column (vertical) direction. A column error correction code called an outer code is assigned. The array 1 of data bytes with PI code and PO code is called an ECC block. As is known, PI and PO codes are generated by sign generation polynomials based on row data and column data.

The format of the ECC block is determined by the DVD standard, where k1 is 192 rows, k2 is 172 bytes, PI of each row is 10 bytes, and PO is 16 rows. Therefore, the length Y in the row direction of the ECC block is 182 bytes, and the length Z in the column direction of the ECC block is 208 rows. That is, each of the 208 rows of the ECC block contains 182 bytes, and each of the 182 columns of the ECC block contains 208 bytes. The ECC block contains sixteen sectors S1-S16, each sector comprising twelve byte rows L1-L12. Each of the byte rows L1-L12 contains 172 data bytes and 10 PI bytes. The PO contains 16 PO byte lines PO1-PO16.

2 schematically shows an ECC block recording format recorded on a data track of a DVD. The 16 PO byte rows PO1-PO16 of FIG. 1 are divided into 16 sectors each. For example, sector S1 includes a combination of twelve byte rows L1-L12 and one PO byte row PO1 associated therewith, and sector S16 includes twelve byte rows L1-L12 and one PO byte row associated therewith. Combination with P16 (not shown).

The ECC block of FIG. 1 is converted to the recording format of FIG. 2 and recorded on the DVD. Generally, the ECC block of FIG. 1 is converted to the recording format of FIG. 2, a frame synchronizing signal is added, and 8/16 modulation (EFM plus modulation) is recorded on DVD. At the time of reading, the signal read out from the DVD is 8/16 demodulated, the frame synchronizing signal is removed, and assembled in the ECC block format of FIG.

In general, the error correction process first performs error correction in the row direction, and performs loss (eraser) correction in the column direction when more than a predetermined number of error bytes are detected in the row direction. In the case of a DVD, the Hamming distance of the Reed Solomon code in the row direction is 11 and the Hamming distance of the Reed Solomon code in the column direction is 17. The maximum error correction number in the row direction is 5 bytes, and the maximum error correction number in the column direction is 8 bytes. However, the maximum error correction number in the row direction is usually limited to less than five, for example, three bytes, and when an error exceeding three bytes is detected, the loss correction is performed in the column direction.

Next, an error correction procedure in the conventional DVD system will be described with reference to FIG. The ECC block data is stored in the DVD 11, such as an optical disc, in the recording format described with reference to FIG. The disk 11 is rotated by the spindle motor 12. The read head 13 moving on the guide rod 14 reads the write data and the servo information from the DVD 11 and sends them to the read circuit 16. The read circuit 16 sends the read write data and the servo information to the formatter 20. The rotation of the spindle motor 12 and the movement of the read head 13 on the guide rod 14 are controlled by the digital servo processor 18 in response to servo information.

In FIG. 3, the broken line and the number in parentheses shown by the broken line show the procedure of data transfer and processing.

(1) The formatter 20 demodulates the read signal by 8/16, removes the frame synchronization signal, and generates an ECC block in the format of FIG. The formatter 20 stores the byte rows (hereinafter ECC block rows) L1, L2, L3... Of the ECC block of FIG. PO15 and PO16 are sequentially transferred to the DRAM 22 operating as the first buffer memory device. The DRAM 22 is used as a working memory for holding an ECC block, storing a corrected ECC block when there is an error, and transferring the corrected ECC block to a host PC (personal computer).

(2) When one or more ECC block rows are transferred to the DRAM 22, the first ECC block rows are transferred to the SRAM 24 operating as the second buffer storage device. The SRAM 24 is a relatively small high speed buffer and is for efficiently performing error correction processing. The ECC block row sent to SRAM 24 contains 172 data bytes and 10 PI bytes.

(3) The ECC block rows sent to the SRAM 24 are then sent to the error correction code decoder 26. Decoder 26 includes a syndrome generator 28 and an error correction circuit 30. The syndrome generator 28 generates a syndrome of 10 bytes based on the data of the ECC block row from the SRAM 24. The error correction circuit 30 obtains an error position and an error value of the ECC block row based on the generated syndrome, and corrects an error byte when the number of error bytes is three or less.

(4) The decoder 26 then sends an error corrected byte to the MPU 32.

(5) The MPU 32 sends the corrected byte sent from the decoder 26 to the DRAM 22, and rewrites the error byte of the corresponding ECC block row in the DRAM 22 as the corrected byte.

The above order is performed sequentially for all ECC block rows. If more than three error bytes are detected in the decoder 26, the missing pointer is set. When the missing pointer is set, after completion of the error correction processing in the row direction, byte strings (hereinafter referred to as ECC block columns) of ECC blocks in the DRAM 22 are sequentially transferred to the SRAM 24. A syndrome of 16 bytes is generated by the syndrome generator 28 in the column direction, and error correction processing is performed in the column direction similarly to row error correction. In order to perform the error correction processing in the column direction, the entire ECC block must be stored in the DRAM 22 before that.

(6) When all the error correction processing ends, there is an ECC block in the DRAM 22 that does not contain an error. Data of the ECC block in the DRAM 22 is sent to the host PC (personal computer) via the line 23.

Syndrome for row direction error correction is generated based on a 182 byte ECC block row containing 172 data bytes and 10 PI bytes. Since the conventional system described above has a syndrome generator 28 downstream of the SRAM 24, it is necessary to transfer the entire 182 bytes of ECC block rows from the DRAM 22 to the SRAM 24 and subsequently to the decoder 28. There is. Therefore, there has been a problem that data transmission takes a long time and error correction processing cannot be performed efficiently.

It is desirable that the error correction process can be executed on-the-fly, ie in real time without waiting for data to be sent to the host. Also in the above-described conventional system, on-the-fly can be realized by increasing the processing efficiency by using parallel pipeline processing, for example, but it is preferable that the processing time can be shortened more essentially. If the data transfer time between the DRAM 22 and the decoder 26 can be shortened, the occupancy time of the internal bus 36 due to the data transfer can be shortened, and an internal bus 36 such as the MPU 32 can be used. By increasing the amount of time you spend, you can increase the efficiency of the entire data storage system.

In addition, since the ECC block format is fixed and the length (182 bytes) of the ECC block row is not a power of two, in the conventional system, an unused area remains in the DRAM buffer 22, and thus the There was a problem that the utilization efficiency was low.

Accordingly, it is an object of the present invention to provide an error correction system and an error correction method that can shorten the time required for error correction processing by increasing data transmission efficiency.

It is still another object of the present invention to provide an error correction system that can shorten the time required for error correction processing and can further increase the use efficiency of the buffer storage device.

Another object of the present invention is to provide a data storage system which has an error correction function using an error correction code in the form of a multiplication code and can shorten the time required for error correction processing.

According to one aspect of the present invention, an error correction system of the present invention includes a formatter for generating an ECC block including at least data arranged in a matrix and a code for correcting row errors for each row, and in each ECC block row from the formatter. A syndrome generator for generating a syndrome based on the first memory; a first buffer storage device for receiving and storing ECC block rows and associated syndromes from the syndrome generator; and receiving a syndrome from the first buffer memory device; And an error correction code decoder for performing error correction processing on ECC block rows in the apparatus.

The first buffer memory has a first and a second bank, each row of the bank has a byte length of 2 ⁿ x (2m + 1), where n and m are positive integers, and (2m + It is divided into 1) byte blocks. Byte length Y of the ECC block row, 2n × 2m <Y <2 n × (2m + 1) , and wherein the first and second banks in units of blocks of each of the ECC block row of bytes in the second ^n-length The byte blocks are alternately stored in an interleaved fashion. The syndrome for each ECC block row is stored in an empty area of byte length [ ²ⁿ × (2m + 1) -k] of the bank byte block in which the (2m + 1) th block of the ECC block row is stored. .

According to yet another aspect of the present invention, a data storage system of the present invention formats a storage medium storing sector data including data and an error correction code in multiplication code format, and sector data read from the storage medium, A formatter for generating an ECC block including data arranged in a matrix, an inner code for row error correction for each row, and an outer code for column error correction for each column, and sequentially receiving ECC block rows from the formatter, and receiving each ECC block A syndrome generator for generating a syndrome based on the row, a first buffer storage device for receiving an ECC block row and an associated syndrome from the syndrome generator, a second buffer memory device for receiving the syndrome from the first memory device; Receive the syndrome from the second buffer memory, and error an ECC block row stored in the first buffer. And a decoder that performs correction processing.

1 is a diagram showing the data format of an ECC block used in a DVD.

2 is a diagram showing a recording format of sector data recorded on a DVD.

3 is a diagram showing a schematic configuration of a conventional DVD storage system.

4 is a diagram showing a schematic configuration of a DVD storage system according to an embodiment of the present invention;

5 illustrates data mapping to a DRAM buffer.

<Explanation of symbols for main parts of drawing>

1: ECC block

11: DVD

12: motor

13: readhead

16: readout circuit

18: digital servo processor

20: formatter

22: DRAM buffer (first buffer storage)

24: SRAM buffer (second buffer storage)

26: decoder

28: syndrome generator

30: error correction circuit

32: MPU

36 data bus

38: syndrome generator

Next, the present invention will be described with reference to FIG. Of the components of FIG. 4, the components corresponding to those of FIG. 3 are shown with the same reference numerals. A feature of the present invention is that the same syndrome generator 38 as the syndrome generator 28 included in the decoder 26 of the conventional system of FIG. 3 is arranged between the formatter 20 and the DRAM buffer 22. It is. The syndrome generator 38 sequentially receives ECC block rows from the formatter 20, transfers the received ECC block rows to the DRAM buffer 22, and generates syndromes for the ECC block rows. Each ECC block row and associated syndromes are all stored in the DRAM 22. The DRAM 22 transfers only syndromes to the SRAM 24. The SRAM 24 transfers the syndrome received from the DRAM 22 to the decoder 26. The error correction circuit 30 in the decoder 26 performs the error correction processing in the row direction based on the syndrome received from the SRAM 24. The syndrome generator 28 in the decoder 26 is used to generate syndromes in the column direction, and is not used to generate syndromes in the row direction.

The broken line in FIG. 4 and the number in parentheses shown by the broken line show the procedure of data transfer and processing.

(1) The formatter 20 generates an ECC block in the format of FIG. 1 as in the prior art. The formatter 20 executes ECC block rows L1, L2, L3... PO15 and PO16 are sequentially transmitted to the syndrome generator 38.

(2) Each time the syndrome generator 38 receives an ECC block row from the formatter 20, it generates a 10-byte syndrome for the ECC block row. The syndrome generator 38 generates a syndrome for the ECC block row while transferring the received ECC block row to the DRAM buffer 22 serving as the first buffer storage device. The generated syndrome is stored in the DRAM 22 along with the associated ECC block row.

(3) The DRAM 22 sequentially transfers only syndromes to the SRAM 24 operating as the second buffer memory device.

(4) The SRAM 24 transmits the syndrome received from the DRAM 22 to the error correction code decoder 26. The error correction circuit 30 of the decoder 26 obtains an error position and an error value of an associated ECC block row based on the received syndrome, and corrects an error byte when the number of error bytes is 3 or less.

(5) The decoder 26 then sends an error corrected byte to the MPU 32.

(6) The MPU 32 sends the corrected byte sent from the decoder 26 to the DRAM 22, and rewrites the error byte of the corresponding ECC block row in the DRAM 22 as the corrected byte.

The loss correction processing in the case where more than three error bytes are detected in the decoder 26 is the same as in the conventional case of FIG. That is, when the missing pointer is set, after completion of the error correction processing in the row direction, the byte strings of the ECC blocks in the DRAM 22 are sequentially transferred to the SRAM 24. In the column direction, a 16-byte syndrome is generated by the syndrome generator 28, and error correction processing in the column direction is performed similarly to error correction processing in the row direction.

(7) When all the error correction processing is completed, there is an ECC block in the DRAM 22 that does not contain an error. Data of the ECC block in the DRAM 22 is sent to the host PC (personal computer) via the line 23.

As is apparent from the above, in the present invention, the syndrome in the row direction is generated at a position between the formatter 20 and the DRAM buffer 22. The syndrome is stored in the DRAM 22 along with each ECC block row. Only the 10-byte syndrome is transmitted from the DRAM 22 to the SRAM 24 and the decoder 26, so that the entire 182-byte ECC block row is transferred from the DRAM 22 to the SDRAM 24 and the decoder 26. Compared with the conventional transmission by the above, it is possible to significantly shorten the data transfer time. In addition, since the loss correction processing in the column direction is performed in the same order as in the prior art, the time required for the loss correction is basically the same as in the prior art.

In the present invention, both the ECC block and the syndrome are stored in the DRAM buffer 22. According to the present invention, the utilization efficiency of the DRAM buffer 22 can be improved. This is an additional feature of the present invention. Next, how to store the ECC block and syndrome in the DRAM buffer 22 in the present invention will be described.

ECC blocks have a fixed data format defined by the standard, and each ECC block row has a length of 182 bytes. On the other hand, in DRAM, the length in the row direction is a power of two. Therefore, when one ECC block row is stored in each row of the DRAM, there is a problem that a free area remains and the memory utilization efficiency is lowered. The address of the DRAM is continuous in the row direction but discontinuous in the column direction. Therefore, there is a problem that the access speed cannot be increased in the column direction.

Korean Patent Application Publication No. 10-15740 by the present applicant proposes a technique for interleaving ECC blocks in two memory banks in order to improve the efficiency of use of the DRA buffer and to allow continuous access in both directions of the matrix. Doing. As two banks, two SDRAM (synchronous DRAM) chips are used. 5 shows the memory data mapping disclosed in this patent application. The upper part of FIG. 5 shows the logical mapping of the ECC block of FIG. 1, and the lower part shows the physical mapping to two memory banks (bank 0 and bank 1). L1, L2, L3... Are the ECC block rows L0, L1, L3... Of sector S1 in FIGS. Corresponds to. For simplicity, only ECC block rows L1-L4 are shown.

The byte rows of banks 0 and 1 are divided into odd byte blocks, respectively. Each byte block has the same length in the row direction. The length (number of bytes) in the row direction of the banks 0 and 1 is represented by ²ⁿ × (2m + 1). Where n and m are positive integers. 2 ⁿ is the number of bytes in a one-byte block, which in this example is 64 (n = 6). 2m + 1 is the number of byte blocks, which in this example is 3 (m = 1). The length in the row direction of the banks 0 and 1 is 192 bytes. When the number of bytes (1182 bytes in this example) of 1 ECC block row is Y, the following relationship is established.

2 ⁿ × 2m <Y <2 ⁿ × (2m + 1)

Each row L1, L2, L3... Of the ECC block. Also divided into three byte blocks of 64 bytes each. The first byte block A0 of the ECC block row L1 is stored in the byte block A0 of bank 0, the second byte block B0 of the ECC block row L1 is stored in the byte block B0 of bank 1, and the third byte block A1 of L1 is It is stored in the byte block A1 of bank 0. The first byte block B1 of the ECC block row L2 is stored in the byte block B1 of bank1, the second byte block A2 of L2 is stored in the byte block A2 of bank 0, and the third byte block B2 of L2 is stored in the bank 1 It is stored in the byte block B2. Likewise below, each ECC block row is stored in the interleaved format in the byte blocks of banks 0 and 1.

When fetching ECC block row L1, byte blocks A0, B0, A1 are alternately accessed between banks 0 and 1, and when fetching ECC block row L2, byte blocks B1, A2, B2 are bank1. And alternately between zero. When fetching the left ECC block string, the byte blocks A0, B1, A3, B4... Are alternately accessed between banks 0 and 1, and when fetching the central ECC block string, byte blocks B0, A2, B3, A5... Are alternately accessed between banks 1 and 0. Also, in the error correction processing in the column direction, the ECC block is processed in units of byte strings, so the leftmost byte string of the ECC block is the byte block strings A0, B1, A3, B4. It is fetched by selecting the leftmost byte of.

In the memory data mapping of Fig. 5, each bank has a continuous address in the row direction. In addition, adjacent rows are stored in different banks, and each bank can be accessed in a bank interleaved manner so that internal circuit delays required for precharge and the like are not visible from the outside. Add 192) to continually fetch thermal data. Therefore, according to this method, fast access can be realized in both directions of the matrix.

In addition, the length of each bank in the row direction is 192 bytes, whereas the ECC block row is 182 bytes in length. Therefore, the byte block strings A1, B2, A4, B5, ... on the right side of the ECC block. Only the bank block that stores the data stores 54 bytes of data. The storage area use efficiency at this time is 182/192 = 0.948, and high use efficiency is obtained.

Therefore, according to the bank interleave method of FIG. 5, fast access and high storage area use efficiency can be obtained. However, each bank row contains an empty area of ²ⁿ × (2m + 1) -Y = 192-182 = 10 bytes.

According to the present invention, the bank interleaving method of FIG. 5 is used for the DRAM buffer 22 of FIG. 4 and the syndrome is stored in an unused area of 10 bytes per bank row. Since the syndrome generator 38 generates a 10-byte syndrome for each ECC block row, the interleaved ECC block rows are stored in the bank, and the associated 10-byte syndrome is stored in a 10-byte unused area. The use efficiency of the buffer 22 can be increased to 100%.

While specific embodiments have been described above, it will be apparent to those skilled in the art that various changes may be made within the scope of the present invention. For example, in the embodiment, the error correction processing in the column direction is performed after the error correction processing in the row direction, but the present invention can be applied even when the error correction in the column direction is performed first. In this case, however, the error correction process cannot be started until the entire ECC block is stored in the DRAM buffer 22. When the error correction processing in the row direction is first performed, this method is advantageous because the error correction processing can be started when one or more ECC block rows are stored in the DRAM buffer. In addition, although the data structure of a specific structure was used in embodiment, it is also possible to use another data format.

In the present invention, a syndrome generator is disposed between the formatter and the first buffer memory, and only the syndrome is transmitted to the second buffer memory and the decoder for error correction. Therefore, the time required for data transfer can be greatly shortened, and the error correction process can be speeded up.

In addition, by using the bank interleaved storage method for the first buffer storage device and storing the syndrome in the unused row area of each bank, the use efficiency of the first buffer storage device can be improved.

It is also economical because no additional storage device is required for storing the syndrome and no special memory control is required. Although it is necessary to add a syndrome generator between the formatter and the first buffer memory device, the addition of the syndrome generator has little effect on the overall system cost since the syndrome generator is inexpensive because of the relatively simple gate.

Claims (16)

A formatter for generating an ECC block including at least data arranged in a matrix and a row error correction code for each row; A syndrome generator for generating a syndrome based on each ECC block row from the formatter; A first buffer storage device for receiving and storing ECC block rows and associated syndromes from the syndrome generator; An error correction code decoder that receives the syndrome from the first buffer memory device and performs an error correction process on an ECC block row in the first buffer memory device Error correction system comprising a. The method of claim 1, The first buffer storage device has first and second banks, Each row of the bank has a byte length of 2 ⁿ x (2m + 1), where n and m are positive integers, and is further divided into (2m + 1) byte blocks, The byte length Y of the ECC block row is ²ⁿ × 2m <Y < ²ⁿ × (2m + 1), and each ECC block row is the block of the byte length of ²ⁿ in the first and second banks. Error correction system, characterized in that the byte block is alternately stored in the interleaved form. The method of claim 2, The syndrome for each ECC block row is stored in an empty area of byte length [ ²ⁿ × (2m + 1) -Y] of the bank byte block in which the (2m + 1) th block of the ECC block row is stored. Error correction system, characterized in that. The method of claim 3, Wherein Y is 182 bytes, n is 6, m is 1, and the syndrome is 10 bytes long. The method according to any one of claims 1 to 4, A second buffer memory device for receiving the syndrome from the first buffer memory device, And the decoder receives a syndrome for each ECC block row from the second buffer memory, and performs an error correction process on the ECC block rows stored in the first buffer memory. The method of claim 5, The ECC block includes a column error correction code for each column, And the decoder performs error correction processing on the ECC block strings in the first buffer storage device as necessary after error correction processing on ECC block rows. Generating a syndrome based on each ECC block row of the ECC block including at least data arranged in a matrix and a row error correction code for each row; Storing the ECC block row and associated syndromes in a buffer storage device; Transferring the syndrome of the buffer storage device to an error correction code decoder to perform error correction processing on an ECC block row in the buffer storage device; Error correction method comprising a. The method of claim 7, wherein The buffer storage device has a first bank and a second bank, Each row of the bank has a byte length of 2 ⁿ x (2m + 1), where n and m are positive integers, and is further divided into (2m + 1) byte blocks, The byte length Y of the ECC block row is ²ⁿ × 2m <Y < ²ⁿ × (2m + 1), and each ECC block row is the block of the byte length of ²ⁿ in the first and second banks. An error correction method characterized in that the byte blocks are alternately stored in an interleaved form. The method of claim 8, The syndrome for each ECC block row is stored in an empty area of byte length [ ²ⁿ × (2m + 1) -Y] of the bank byte block in which the (2m + 1) th block of the ECC block row is stored. Error correction method, characterized in that. The method according to any one of claims 7 to 9, The ECC block includes a column error correction code for each column, And the decoder performs error correction processing on the ECC block string in the buffer storage means as necessary after the error correction processing on the ECC block row. A storage medium which stores sector data including data and an error correction code in multiplication code format; A formatter for formatting sector data read from the storage medium and generating an ECC block including data arranged in a matrix, a row error correction code for each row, and a column error correction code for each column; A syndrome generator for sequentially receiving ECC block rows from the formatter and generating syndromes based on each ECC block row; A first buffer memory for receiving an ECC block row and associated syndromes from the syndrome generator; A second buffer memory device for receiving the syndrome from the first memory device; A decoder that receives the syndrome from the second buffer memory device and performs an error correction process on the ECC block rows stored in the first buffer memory device. Data storage system having an error correction function comprising a. The method of claim 11, And the syndrome generator transmits the ECC block row to the first buffer storage device, generates a syndrome for the ECC block row, and stores the syndrome in the first buffer memory device. The method of claim 12, The first buffer storage device has first and second banks, Each row of the bank has a byte length of 2 ⁿ x (2m + 1), where n and m are positive integers, and is further divided into (2m + 1) byte blocks, The byte length Y of the ECC block row is ²ⁿ × 2m <Y < ²ⁿ × (2m + 1), and each ECC block row is the block of the byte length of ²ⁿ in the first and second banks. A data storage system characterized by being stored in an interleaved fashion alternately in a byte block. The method of claim 13, The syndrome for each ECC block row is stored in an empty area of byte length [ ²ⁿ × (2m + 1) -Y] of the bank byte block in which the (2m + 1) th block of the ECC block row is stored. Data storage system characterized in that. The method of claim 14, And wherein Y is 182 bytes, n is 6, m is 1, and the syndrome is 10 bytes long. The method according to any one of claims 11 to 15, The first buffer storage device sequentially receives ECC block rows from the formatter, stores data for one ECC block, And the second buffer storage device performs error correction processing on the ECC block string in the first buffer storage device as necessary after the error correction processing on the ECC block row.