KR20000021507A - Method for forming isolation area of semiconductor device - Google Patents
Method for forming isolation area of semiconductor device Download PDFInfo
- Publication number
- KR20000021507A KR20000021507A KR1019980040631A KR19980040631A KR20000021507A KR 20000021507 A KR20000021507 A KR 20000021507A KR 1019980040631 A KR1019980040631 A KR 1019980040631A KR 19980040631 A KR19980040631 A KR 19980040631A KR 20000021507 A KR20000021507 A KR 20000021507A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor substrate
- trench
- hard mask
- forming
- layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000002955 isolation Methods 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000004140 cleaning Methods 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims 1
- 238000007517 polishing process Methods 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 공정 마진(Margin)을 향상시키는데 적당한 반도체 소자의 격리영역 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method for forming an isolation region of a semiconductor device suitable for improving process margins.
일반적으로 반도체 소자가 점차로 고집적화 됨에 따라 그에 따른 여러 가지 방법 중 소자 격리영역과 소자형성영역 즉, 활성영역의 크기를 축소하는 방법들이 제안되고 있다.In general, as semiconductor devices are increasingly integrated, methods for reducing the size of device isolation regions and device formation regions, that is, active regions, have been proposed.
상기와 같은 소자격리영역의 형성기술로는 로코스(LOCOS : LOCal Oxidation of Silicon) 공정을 사용하였다. 이러한 로코스 공정을 이용한 격리영역 형성공정은 그 공정이 간단하고 재현성이 우수하다는 장점이 있어 많이 사용되고 있다.As the formation technology of the device isolation region as described above, a LOCOS (LOCal Oxidation of Silicon) process was used. The isolation region forming process using the LOCOS process has been widely used because of its advantages that the process is simple and excellent in reproducibility.
그러나 소자가 점차로 고집적화함에 따라 로코스 공정으로 격리영역을 형성하는 경우 로코스로 형성된 격리산화막의 특징인, 활성영역으로 확장되는 격리산화막 에지부의 버즈빅(Bird's Beak) 발생 때문에 활성영역의 면적이 축소되어 64MB급 이상의 디램(DRAM : Dynamic Random Access Memory) 소자에서 사용하기에는 적합하지 못한 것으로 알려져 있다.However, as the device is gradually integrated, the area of the active region is reduced due to the occurrence of Bird's Beak at the edge of the isolation oxide that extends into the active region, which is characteristic of the isolation oxide formed by the LOCOS process. It is not suitable for use in DRAMs of more than 64MB.
그래서 종래 로코스를 이용한 격리영역의 형성방법에는 버즈빅의 생성을 방지하거나 또는 버즈빅을 제거하여 격리영역을 축소하고 활성영역을 늘리는 등의 어브밴스드 로코스(Advanced LOCOS) 공정이 제안되어 64MB 또는 256MB급 디램의 제조공정에서 사용되었다.Therefore, in the conventional method of forming an isolation region using LOCOS, an advanced LOCOS process is proposed such as preventing the generation of buzz big or removing the buzz big to reduce the isolation area and increase the active area. Or in the manufacturing process of 256MB DRAM.
그러나 이러한 어드밴스드 로코스를 사용한 격리영역의 형성공정도 셀 영역의 면적이 0.2μm2이하를 요구하는 기가(GIGA)급 이상의 디램에서는 격리영역이 차지하는 면적이 크다는 문제점과 로코스 공정으로 형성되는 필드 산화막이 실리콘 기판과의 계면에서 형성되면서 실리콘 기판의 농도가 필드 산화막과 결합으로 인해 낮아지게 되어 결과적으로 누설전류가 발생하는 등의 문제점이 발생하여 격리영역의 특성이 나빠지므로 기가 디램급 이상의 격리영역 형성방법으로 격리영역의 두께 조절이 용이하고 격리 효과를 높일 수 있는 트랜치(Trench)를 이용한 격리영역 형성방법이 제안되었다.However, in the process of forming the isolation region using the advanced advanced process, the area of the isolation region is large in the GIGA class or more DRAM which requires the cell area of 0.2 μm 2 or less and the field oxide film formed by the LOCOS process. As the silicon substrate is formed at the interface with the silicon substrate, the concentration of the silicon substrate is lowered due to the coupling with the field oxide film, and as a result, a problem such as leakage current occurs, resulting in poor isolation characteristics. As a method, a method of forming an isolation region using a trench that can easily control the thickness of the isolation region and enhance the isolation effect has been proposed.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 격리영역 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming an isolation region of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래의 기술의 반도체 소자의 격리영역 형성방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming an isolation region of a semiconductor device of the related art.
도 1a에 도시한 바와 같이, 반도체 기판(11)상에 하드 마스크(Hard Mask)용 질화막(12)을 증착하고, 포토리소그래픽 공정을 실시하여 반도체 기판(11)의 표면이 소정부분 노출되도록 질화막(12)을 패터닝하여 필드영역을 정의한다.As shown in FIG. 1A, a nitride film 12 for a hard mask is deposited on the semiconductor substrate 11 and a photolithographic process is performed to expose a portion of the nitride film so that the surface of the semiconductor substrate 11 is partially exposed. Pattern (12) to define the field area.
이어, 상기 패터닝된 질화막(12)을 마스크로 이용하여 상기 노출된 반도체 기판(11)의 필드영역을 선택적으로 제거하여 소정깊이를 갖는 트랜치(13)를 형성한다.Next, the trench 13 having a predetermined depth is formed by selectively removing the field region of the exposed semiconductor substrate 11 using the patterned nitride film 12 as a mask.
도 1b에 도시한 바와 같이, 상기 트랜치(13)를 포함한 반도체 기판(11)의 전면에 산화막(14)을 증착한다.As shown in FIG. 1B, an oxide film 14 is deposited on the entire surface of the semiconductor substrate 11 including the trench 13.
도 1c에 도시한 바와 같이, 상기 산화막(14)이 트랜치(13)의 내부에만 남도록 전면에 CMP(Chemical Mechanical Polishing)공정을 실시하여 STI(Shallow Trench Isolation) 구조를 갖는 소자 격리막(14a)을 형성한다.As shown in FIG. 1C, a CMP (Chemical Mechanical Polishing) process is performed on the entire surface such that the oxide layer 14 remains only inside the trench 13 to form a device isolation layer 14a having a shallow trench isolation (STI) structure. do.
여기서 미설명한 "A"는 상기 산화막(14)에 CMP 공정을 실시하여 소자 격리막(14a)을 형성할 때 상기 질화막(12)이 식각된 부분을 나타낸다.Here, "A", which is not described herein, refers to a portion where the nitride film 12 is etched when the device isolation layer 14a is formed by performing the CMP process on the oxide layer 14.
도 1d에 도시한 바와 같이, 상기 하드마스크용 질화막(12)을 제거하고, 상기 반도체 기판(11)에 세정공정을 실시한다.As shown in FIG. 1D, the hard mask nitride film 12 is removed and a cleaning process is performed on the semiconductor substrate 11.
여기서 상기 세정공정시 소자 격리막(14a)의 에지(Edge)부분이 손실된다.Here, an edge portion of the device isolation layer 14a is lost during the cleaning process.
즉, "B"는 세정공정에 의해 소자 격리막(14a)의 에지부분이 손실되어 파임부분을 나타낸다.Namely, " B " indicates that the edge portion of the device isolation film 14a is lost by the cleaning process to represent the recessed portion.
그러나 상기와 같은 종래 기술의 반도체 소자의 격리영역 형성방법에 있어서 다음과 같은 문제점이 있었다.However, in the method of forming the isolation region of the semiconductor device of the related art as described above, there are the following problems.
즉, 도 1d에서와 같이, 세정공정시 소자 격리막의 에지부분이 손실됨으로 파임 현상이 발생하여 배선층 증착시 파임부분까지 증착됨으로써 배선의 불량이 발생하고, 이로 인하여 고집적 디바이스에 필요한 작은 선폭 공정의 마진을 확보하기 어렵다.That is, as shown in Figure 1d, the edge portion of the device isolation film is lost during the cleaning process, the chipping phenomenon occurs, the wiring defect is deposited by the deposition of the wiring layer during deposition, resulting in a small line width process required for high integration devices Difficult to secure.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 세정공정시 소자 격리막의 에지부분의 손실에 의한 파임 현상을 방지하여 공정 마진을 확보할 수 있도록 한 반도체 소자의 격리영역 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and provides a method of forming an isolation region of a semiconductor device to ensure a process margin by preventing the dig phenomenon caused by the loss of the edge portion of the device isolation layer during the cleaning process. There is a purpose.
도 1a 내지 도 1d는 종래 기술의 반도체 소자의 격리영역 형성방법을 나타낸 공정단면도1A to 1D are cross-sectional views illustrating a method of forming an isolation region of a semiconductor device of the related art.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 격리영역 형성방법을 나타낸 공정단면도2A through 2E are cross-sectional views illustrating a method of forming an isolation region of a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : 질화막21 semiconductor substrate 22 nitride film
23 : 트랜치 24 : 절연막23 trench 24 insulating film
24a : 소자 격리막24a: device isolation layer
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 격리영역 형성방법은 반도체 기판의 표면이 소정부분 노출되도록 하드 마스크층을 형성하는 단계와, 상기 하드 마스크층을 마스크로 이용하여 노출된 반도체 기판을 선택적으로 제거하여 트랜치를 형성하는 단계와, 상기 하드 마스크층을 선택적으로 제거하여 상기 트랜치 양측의 반도체 기판의 표면을 소정부분을 노출시키는 단계와, 상기 트랜치를 포함한 반도체 기판의 전면에 절연막을 형성하는 단계와, 상기 절연막이 트랜치 내부 및 노출된 반도체 기판의 표면에만 남도록 선택적으로 제거하여 소자 격리막을 형성하는 단계와, 상기 하드 마스크층을 제거하고 상기 반도체 기판에 세정공정을 실시하는 단계를 포함하여 형성함을 특징으로 한다.In order to achieve the above object, a method of forming an isolation region of a semiconductor device according to the present invention includes forming a hard mask layer to expose a predetermined portion of a surface of a semiconductor substrate, and using the hard mask layer as a mask to expose the semiconductor. Selectively removing the substrate to form a trench; selectively removing the hard mask layer to expose a portion of the surface of the semiconductor substrate on both sides of the trench; and insulating film on the entire surface of the semiconductor substrate including the trench. Forming a device isolation film by selectively removing the insulating film so that the insulating film remains inside the trench and only on the exposed surface of the semiconductor substrate; and removing the hard mask layer and performing a cleaning process on the semiconductor substrate. It is characterized by forming.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 격리영역 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, an isolation region forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 격리영역 형성방법을 나타낸 공정단면도이다.2A to 2E are cross-sectional views illustrating a method of forming an isolation region of a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(21)상에 하드 마스크(Hard Mask)용 질화막(22)을 증착하고, 포토리소그래픽 공정을 실시하여 반도체 기판(21)의 표면이 소정부분 노출되도록 질화막(22)을 패터닝하여 필드영역을 정의한다.As shown in FIG. 2A, a nitride film 22 for a hard mask is deposited on the semiconductor substrate 21 and a photolithographic process is performed to expose the nitride film so that a predetermined portion of the surface of the semiconductor substrate 21 is exposed. Patterning (22) defines the field area.
이어, 상기 패터닝된 질화막(22)을 마스크로 이용하여 상기 노출된 반도체 기판(21)의 필드영역을 선택적으로 제거하여 소정깊이를 갖는 트랜치(23)를 형성한다.Subsequently, the trench 23 having a predetermined depth is formed by selectively removing the field region of the exposed semiconductor substrate 21 using the patterned nitride layer 22 as a mask.
도 2b에 도시한 바와 같이, 상기 하드 마스크용 질화막(22)을 습식식각으로 표면으로부터 소정두께를 선택적으로 제거한다. 이때 상기 질화막(22)은 표면의 상부와 측면이 선택적으로 제거됨으로써 상기 트랜치(23) 양측의 반도체 기판(21)의 표면이 소정부분 노출된다.As shown in Fig. 2B, the hard mask nitride film 22 is selectively removed from the surface by wet etching. In this case, the upper and side surfaces of the nitride film 22 are selectively removed to expose a portion of the surface of the semiconductor substrate 21 on both sides of the trench 23.
이때 상기 질화막(22)을 선택적으로 제거하기 위하여 포토리소그래픽 공정을 사용할 수도 있다.In this case, a photolithographic process may be used to selectively remove the nitride film 22.
여기서 미설명한 "C"는 상기 질화막(22)이 습식식각에 의해 제거된 부분이다."C", which is not described herein, is a portion where the nitride film 22 is removed by wet etching.
도 2c에 도시한 바와 같이, 상기 트랜치(23)를 포함한 반도체 기판(21)의 전면에 산화막(24)을 형성한다.As shown in FIG. 2C, an oxide film 24 is formed on the entire surface of the semiconductor substrate 21 including the trench 23.
도 2d에 도시한 바와 같이, 상기 산화막(24)이 상기 트랜치(23)의 내부 및 노출된 반도체 기판(21)의 표면에만 남도록 전면에 CMP 공정이나 에치백공정을 실시하여 상기 산화막(24)을 선택적으로 제거하여 STI구조를 갖는 소자 격리막(24a)을 형성한다.As shown in FIG. 2D, a CMP process or an etch back process is performed on the entire surface of the oxide film 24 so that the oxide film 24 remains only inside the trench 23 and on the exposed surface of the semiconductor substrate 21. It is selectively removed to form the device isolation film 24a having the STI structure.
여기서 미설명한 "D"는 상기 산화막(24)에 CMP 공정이나 에치백 공정시 상기 질화막(22)이 함께 식각되는 부분이다.Herein, "D", which is not described, is a portion in which the nitride film 22 is etched together during the CMP process or the etch back process.
도 2e에 도시한 바와 같이, 상기 하드마스크용 질화막(22)을 제거하고, 상기 반도체 기판(21)에 세정공정을 실시함으로써 소자 격리막(24a)의 형성공정을 완료한다.As shown in Fig. 2E, the hard mask nitride film 22 is removed, and the semiconductor substrate 21 is subjected to a cleaning process to complete the process of forming the device isolation film 24a.
여기서 상기 소자 격리막(24a)은 상기 트랜치(23) 양측의 반도체 기판(21)상에도 형성되어 있기 때문에 세정공정시 산화막(24)에 의해 형성된 소자 격리막(24a)의 에지부분이 식각되어지더라도 소자 격리막(24a)의 에지부분의 손실에 의한 파임 현상은 방지할 수 있다.Since the device isolation layer 24a is formed on the semiconductor substrate 21 on both sides of the trench 23, the device isolation layer 24a may be etched even when the edge portion of the device isolation layer 24a formed by the oxide layer 24 is etched during the cleaning process. Digging due to the loss of the edge portion of the separator 24a can be prevented.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 격리영역 형성방법에 있어서 소자 격리막의 에지부분의 손실에 의한 파임 현상을 방지함으로써 배선 공정시 배선을 결함을 방지할 수 있고, 고집적 디바이스에 필요한 작은 선폭을 갖는 공정에서 공정마진을 확보할 수 있는 효과가 있다.As described above, in the method for forming the isolation region of the semiconductor device according to the present invention, by preventing the phenomena caused by the loss of the edge portion of the device isolation film, the wiring defect can be prevented during the wiring process, and the small line width required for the highly integrated device In the process having the effect of ensuring a process margin.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980040631A KR20000021507A (en) | 1998-09-29 | 1998-09-29 | Method for forming isolation area of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980040631A KR20000021507A (en) | 1998-09-29 | 1998-09-29 | Method for forming isolation area of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000021507A true KR20000021507A (en) | 2000-04-25 |
Family
ID=19552425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980040631A KR20000021507A (en) | 1998-09-29 | 1998-09-29 | Method for forming isolation area of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000021507A (en) |
-
1998
- 1998-09-29 KR KR1019980040631A patent/KR20000021507A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR19990061066A (en) | Method of forming device isolation film of semiconductor device | |
| KR100244300B1 (en) | Method of forming isolation region in a semiconductor device | |
| KR100403316B1 (en) | Forming method for field oxide of semiconductor device | |
| KR100305026B1 (en) | Manufacturing method of semiconductor device | |
| KR100205339B1 (en) | Method for forming isolation region of semiconductor device | |
| KR20000021507A (en) | Method for forming isolation area of semiconductor device | |
| KR100792709B1 (en) | Manufacturing method for semiconductor device | |
| KR100252908B1 (en) | Method for forming field region of semiconductor device | |
| KR100277870B1 (en) | Method of forming an isolation region of a semiconductor device | |
| KR100244303B1 (en) | Method for forming isolation region of semiconductor device | |
| KR100351904B1 (en) | method for forming isolation film of semiconductor device | |
| KR100235971B1 (en) | Method of manufacturing semiconductor device | |
| KR100379516B1 (en) | method for manufacturing in a semiconductor device | |
| KR100239454B1 (en) | Method of forming an element isolation region in a semiconductor device | |
| KR20040002121A (en) | Method for Forming Field Area in Semiconductor Device | |
| KR20010063864A (en) | Fabricating method for semiconductor device | |
| KR20030000436A (en) | Method for manufacturing isolation of semiconductor device | |
| KR100221633B1 (en) | Isolation method for a semiconductor device | |
| KR20030000437A (en) | Method for manufacturing isolation of semiconductor device | |
| KR19990057376A (en) | Device Separating Method of Semiconductor Device | |
| KR20010064963A (en) | method for forming isolation region of semiconductor device | |
| KR19990052944A (en) | Manufacturing method of semiconductor device | |
| KR20040002119A (en) | Method for Forming Field Area in Semiconductor Device | |
| KR20010001447A (en) | A forming method for field oxide of semiconductor device | |
| KR20000044879A (en) | Method for forming isolation film of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| WITN | Withdrawal due to no request for examination |