KR20000019969A - Cell string structure of nand type flash memory - Google Patents

Abstract

PURPOSE: A cell string structure of NAND type flash memory is provided to effectively realize the high integration of the device by ensuring effective channel area and greatly reduce power consumption due to the decrease of leakage current. CONSTITUTION: A cell string structure of NAND type flash memory comprises memory cell strings(S), and wiring lines(112) for connecting channels. The strings respectively have one impurity injecting area and are separated in order to expose a semiconductor substrate(100) between cells. The lines surround the cell defining the memory cell string and connect the surfaces of the substrate exposed between the cells. Channels are formed in the memory cell string by applying corresponding bias voltage.

Description

Cell string structure of NAD flash memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, in a NAND type structure in which a plurality of cells are connected to a bit line in series, a sufficient effective channel length of a cell transistor can be ensured and a junction leakage can be reduced. Relates to a cell string structure.

In general, nonvolatile memory has the advantage that the stored data is not lost even when the power is interrupted. It is widely used for data storage of PC Bios, set-top box, printer and network server. It is also used in many mobile phones.

Among the above nonvolatile memories, EEPROM type flash memory having a function of collectively erasing data of all cells has two or more cell transistors in parallel on one bit line. A connected NOR flash memory is divided into a NAND flash memory in which two or more cell transistors are connected in series on one bit line.

1 is a vertical cross-sectional view showing a stacked MOS transistor having a conventional LDD impurity junction region. Referring to this figure, a unit cell of a NAND flash memory having a stacked cell transistor is disposed on an upper portion of a semiconductor substrate 10. Referring to FIG. Stacked gate electrode 14 comprising a floating gate 14a for recording data, a control gate 14c for controlling the data state according to the voltage of the gate 14a, and an inter-gate insulating film 14b, and a stacked type A spacer 18 formed on both sides of the sidewall of the gate electrode 14, a tunnel oxide film 12 formed between the floating gate 14a and the substrate 10 to a thickness of about 100 μs, and a surface near the edge of the gate electrode 14. It is composed of a source / drain region 20 formed under the substrate 10.

The cell transistor configured as described above is an LDD in which impurities of the source / drain region 20 are lightly implanted in the lower portion of the substrate 10 near the edge of the gate electrode 14 to prevent hot carrier effects and short channel effects of the microchannel device. (Lightly Doped Drain) region 16, the channel of the actual device is the length (lc) of the gate electrode 14 minus the length (lo) of the LDD region 16 near the edge of the gate electrode 14 ( le).

Therefore, when the cell transistor is more highly integrated, the effective channel length (le) is also smaller, resulting in a punchthrough phenomenon during operation of the device, resulting in a decrease in the electrical characteristics of the device.

2 is a vertical cross-sectional view showing a cell string structure of a NAND flash memory having a stacked cell transistor according to the prior art, in which the NAND flash memory has a string structure in which 8 or 16 cell transistors are connected to a bit line in series. For convenience, only four cell transistors M1, M2, M3, and M4 are shown. The cell transistors M1, M2, M3, and M4 have the same reference numerals as the transistors shown in FIG. 1, but only source and drain regions 20a and 20b are distinguished from each other.

This figure shows a stacked cell transistor that does not have the LDD structure described above. At this time, since the cells of the flash memory commonly use impurity implantation regions used as the source and drain regions 20a and 20b except for both ends, impurities in the source / drain regions diffuse sideways during the device process. The impurity region overlaps the lower portion of the gate electrode so that the effective channel of the device is smaller than the set channel length.

Therefore, the NAND type flash memory cell has a worse electrical characteristic than a semiconductor device having only a single transistor due to a smaller effective channel, and in particular, there is a problem in that power consumption increases due to an increase in junction leakage current.

The object of the present invention is to eliminate the source / drain regions of the cells except for both ends of the flash memory cell transistor in which a plurality of cell transistors are connected in series in order to solve the above problems of the prior art, and instead of connecting the channels. The present invention provides a cell string structure of a NAND-type flash memory that can secure the effective channel length and prevent degradation of electrical characteristics due to a fine cell structure.

1 is a vertical sectional view showing a stacked MOS transistor having a conventional LDD impurity junction region;

2 is a vertical sectional view showing a cell string structure of a NAND flash memory having a stacked cell transistor according to the prior art;

3 is a vertical sectional view showing a cell string structure of a NAND type flash memory having a stacked cell transistor according to the present invention;

* Description of the symbols for the main parts of the drawings *

100 semiconductor substrate 102 tunnel oxide film

104a: floating gate 104b: inter-gate insulating film

104c: control gate 104: gate electrode

106: spacer 108a: source region

108b: drain region 110: insulating film

112: wiring for channel connection

In order to achieve the above object, the present invention provides a cell string structure of a NAND-type flash memory in which a plurality of cells having a gate electrode in which floating gates / inter-gate insulating films / control gates are sequentially stacked are connected. Memory cell strings each having one impurity implantation region facing each other in a substrate near the lower edge of the cell gate electrode corresponding to each other, and having a structure spaced apart by a predetermined distance so that the substrate is exposed between the cells, and cells forming the memory cell string. And a channel connection line for interconnecting the surface of the substrate exposed between the cells so that a channel is formed in the memory cell string by applying a corresponding bias voltage during data writing and reading operations to the channel connection line. It features.

In the present invention, an insulating film for thin interlayer insulation is further provided on the entire upper surface of the cells constituting the memory cell string.

According to the present invention, since the channel connection wiring is interconnected with the substrate surface corresponding to the connection portion of the plurality of cell transistors constituting the memory cell string, it serves as a link ring that effectively connects the channels of each memory cell when driving the memory. do.

Therefore, even if the cell structure of the NAND type flash memory is integrated, the source / drain regions are selectively formed only in the cell transistors corresponding to both ends of the string, without forming all the impurity implantation regions of the cell transistors forming the string. It is possible to secure the effective channel length of while preventing the degradation of electrical characteristics due to the fine cell structure.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a vertical cross-sectional view showing a cell string structure of a NAND type flash memory having a stacked cell transistor according to the present invention, which is typically a structure in which a plurality of cells of 8 or 16 or more are connected in series. For simplicity of explanation, four cells are described as basic structures.

The flash memory includes a substrate 100 near the lower edge of the gate electrode 104 of the first and fourth cells M1 and M4 corresponding to both ends of the first to fourth cells M1, M2, M3, and M4. Source and drain regions 108a and 108b which are impurity implantation regions, respectively, facing each other, and have a structure spaced apart by a predetermined distance so that the surface of the substrate 100 is exposed between the cells M1, M2, M3, and M4. Channel connection wiring 112 interconnecting the memory cell string S and the substrate surface 111 exposed between the cells M1, M2, M3, and M4 surrounding the front surface of the cells constituting the memory cell string S. ) And an insulating layer 110 for thin interlayer insulation on the entire upper surface of the cells constituting the memory cell string S and the lower portion of the channel connection wiring 112.

The transistor structure of the memory cell includes a stacked gate electrode 104 including a floating gate 104a, a control gate 104c, and an inter-gate insulating film 104b on the semiconductor substrate 100, and a stacked gate electrode. A spacer 106 formed on both sides of the sidewall of the 104 and a tunnel oxide film 102 having a tunnel of a predetermined region between the floating gate 104a and the substrate 100.

In the flash memory according to the present invention having a structure as described above, assuming that the selected cell is M3, and when data is programmed into the cell M3, 0 V is applied to the source region 108a near the M1 cell, 5V is applied to the drain region 108b in the vicinity. At the same time, 5V is applied to the control gate 104c of the first, second, and fourth cells M1, M2, and M4 that are unselected cells, and 12V is applied to the third cell M3, which is the selected cell, and the channel connection wiring ( Apply 4V to 112). At this time, the bias voltage of the substrate 100 is 0V. Then, a channel path is formed in the vicinity of the substrate of the cells M1, M2, M3, and M4, and the substrate surface between the cells M1, M2, M3, and M4 is caused by the bias voltage of the channel connection wiring 112. A channel is also formed in the region 111, and hot electrons in the channel region of the selected cell M3 are injected into the floating gate to raise the threshold voltage to about 4V.

In the read operation of the flash memory, 0 V is applied to the source region 108a and 2 V is applied to the drain region 108b to turn off all of the unselected cells M1, M2, and M4. At the same time, 5V is applied to the control gate 104c of the first, second, and fourth cells M1, M2, and M4 that are unselected cells, and 3.5V is applied to the third cell M3, which is the selected cell, and the channel connection wiring Apply 4V to 112. At this time, the bias voltage of the substrate 100 is 0V. Then, data stored in the floating gate of each cell is read according to the on / off state of the cells M1, M2, M3, and M4.

Finally, during the erase operation of the flash memory, the source region 108a, the drain region 108b, and the channel connection wiring 112 are suspended, and -9V is applied to the control gates of all the cells M1, M2, M3, and M4. do. At the same time, a floating gate of all cells M1, M2, M3, and M4 is applied by FN tunneling by applying a bias voltage of 5 V to a well (not shown) of a substrate to which the selected third cell M belongs. Electrons are emitted from the lower side of the substrate to lower the threshold voltage of each cell to about 1V.

Therefore, the present invention includes a channel connection wiring for applying a voltage to the substrate between the cells constituting the cell string of the NAND type flash memory, so that the channel of each memory cell is also included in the substrate of the channel connection wiring during data writing and reading operations. Connected to perform the same operation as a normal memory.

As described above, in the case of the NAND type flash memory, it is possible to effectively achieve high integration of the device by securing the effective channel region according to the design rule, and to reduce the leakage current of the impurity injection region generated in the cell. Therefore, the power consumption of the entire system can be greatly reduced.

Claims (2)

In the cell string structure of a NAND type flash memory in which a plurality of cells having a gate electrode in which floating gates / inter-gate insulating films / control gates are sequentially stacked are connected in series, A memory cell string having one impurity implantation region so as to face each other in a substrate near an edge of an edge of a cell gate electrode corresponding to both ends of the plurality of cells, and having a structure spaced apart from each other to expose a substrate between the cells; And A channel connection line surrounding the front surface of the cells constituting the memory cell string and interconnecting the surface of the substrate exposed between the cells, and applying a corresponding bias voltage to the channel connection line during data write and read operations, A cell string structure of a NAND-type flash memory characterized in that a channel is formed in the. The cell string structure of claim 1, further comprising an insulating layer thinly interlayer insulating the upper surface of the cells constituting the memory cell string.