KR20000019111A - Noise attenuating circuit for sense amplifier - Google Patents

Abstract

PURPOSE: A noise attenuating circuit for a sense amplifier is provided, which attenuates a noise generated when reading data of a sense amplifier to stably operate a device. CONSTITUTION: A noise attenuating circuit for a sense amplifier comprises: a first and second sense amplifiers (1, 2) for outputting each different signals according a common memory cell and first and second reference cells; a selecting delay means (3) for selectively delaying output signals of first and second sense amplifiers (1, 2), including first and second selecting delay means (3a, 3b); a data transmission means (4) for delaying one signal between the output signal of the first sense amplifier (1) and the output signal of the second sense amplifier (2) according to an initial output signal of first and second sense amplifiers (1, 2); and a noise attenuating means (5) for outputting a signal which a noise is attenuated according to the output signal of the first selecting delay means (3a), the output signal of the second selecting delay means (3b), and the output signal of the data transmission means (4). Thereby, it is possible to decrease a chip size.

Description

Noise Attenuation Circuit of Sense Amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise attenuation circuit of a sense amplifier, and more particularly, to a noise attenuation circuit of a sense amplifier capable of stably operating a device by attenuating noise that may occur when data is read from a sense amplifier. .

FIG. 1 is a block diagram of a general sense amplifier, in which a sense amplifier reads data by sensing a voltage difference caused by a current flowing through a memory cell and a current flowing through a reference cell. Output to output buffer. When the potential of the sensing node of the memory cell is smaller than the potential of the sensing node of the reference cell in the sense amplifier performing such an operation, it is output high and the potential of the sensing node of the memory cell is greater than the potential of the sensing node of the reference cell. Output low.

However, in such a sense amplifier circuit, when reading cell data, wrong data is directly output to the outside according to each case. For example, as shown in FIGS. 2A and 2B, a memory cell is changed from an erase cell to a program cell in a state where the potential of the sensing node SENREFD of the reference cell is fixed. When switching to the program cell, the potential of the sensing node SENDTD of the memory cell is shaken by the instantaneous current change of the memory cell, which causes the output signal SAOUT of the sense amplifier to change. In the graph, the changed output signal, ie, wrong data, expressed as glitch, is output to the output buffer.

The induced voltage induced by Ldi / dt from the output buffer into which the wrong data is input is fed back to induce another noise, thereby slowing down the operation speed of the device and causing unstable operation.

To prevent this, the output buffer was artificially disabled using the address transition detection circuit when the address is inverted. However, it is difficult to set the disable time of the output buffer and the noise output after the disable time is not improved, so the conventional circuit is meaningless in an unstable device state. In addition, even when the cells are stably read, the output transition is artificially disabled using an address transition detection circuit, causing unnecessary delay and power consumption.

Accordingly, an object of the present invention is to provide a noise attenuation circuit of a sense amplifier which can solve the above problems by reducing the noise that may be generated when data is read out of the sense amplifier so that the device can be stably operated.

The present invention for achieving the above object has a different load ratio, each of the first and second sense amplifiers for outputting different signals according to the common memory cell and the first and second reference cells, and the initial output of the sense amplifier Selective delay means for selectively delaying and outputting the output signals of the first and second sense amplifiers in accordance with a signal, and output signals of the first sense amplifier and the second sense amplifiers in accordance with an initial output signal of the sense amplifier. A data transmission means for delaying and outputting any one of the output signals by a predetermined time, a signal whose noise is attenuated according to the output signal of the first selection delay means, the output signal of the second selection delay means, and the output signal of the data transmission means. And noise attenuation means for outputting.

1 is a block diagram of a typical sense amplifier.

2 (a) and 2 (b) are graphs showing a change in an output signal according to cell data reading of a general sense amplifier.

3 is a block diagram of a noise attenuation circuit of a sense amplifier in accordance with the present invention.

4 is a block diagram of a sense amplifier of the noise attenuation circuit of the sense amplifier according to the present invention.

5 (a) and 5 (b) are detailed circuit diagrams of the first and second select delay means of the noise attenuation circuit of the sense amplifier according to the present invention;

6 is a detailed circuit diagram of data transmission means of the noise attenuation circuit of the sense amplifier according to the present invention.

7 is a detailed circuit diagram of noise attenuation means of the noise attenuation circuit of the sense amplifier according to the present invention.

8 is a block diagram of control means for noise attenuation means;

9 is a timing diagram showing the output of each means of the noise attenuation circuit of the sense amplifier according to the present invention.

10 and 11 are graphs showing simulation results when transitioning from a high state to a low state and a transition from a low state to a low state in order to compare a circuit according to the present invention with a conventional circuit.

<Description of the symbols for the main parts of the drawings>

1: first sense amplifier 2: second sense amplifier

3: selection delay means 3a: first selection delay means

3b: second selection delay means 4: data transmission means

5: noise attenuation means

The present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a noise attenuation circuit of a sense amplifier according to the present invention, and is configured as follows.

The first and second sense amplifiers 1 and 2 have different load ratios, respectively, and determine outputs according to common memory cells and separate first and second reference cells. That is, different output signals SA1b and SA0b are output at time intervals according to the first and second reference cells.

The selection delay means 3 consists of first and second selection delay means 3a and 3b. The first selection delay means 3a delays the output signal SA1b of the first sense amplifier 1 and outputs SAOUT1 according to the initial output signal SAOUT_int of the sense amplifier. The second select delay means 3b delays the output signal SA0b of the second sense amplifier 2 and outputs it SAOUT1 in accordance with the initial output signal SAOUT_int of the sense amplifier.

The data transmission means 4 selects one of an output signal SA1b of the first sense amplifier and an output signal SA0b of the second sense amplifier according to the initial output signal SAOUT_int of the sense amplifier, and delays the output by a set time. Generate signal SAOUT2.

The noise attenuation means 5 is connected to the output signal SAOUT1 of the first selection delay means 3a, the output signal SAOUT0 of the second selection delay means 3b, and the output signal SAOUT2 of the data transmission means 4. Therefore, an output signal SAOUT having attenuated noise is generated and output to the output buffer.

4 is a block diagram illustrating in detail the first and second sense amplifiers of the noise attenuation circuit of the sense amplifier according to the present invention.

In the present invention, two sense amplifiers 11 and 12 having different load ratios are used in which the output of each sense amplifier output through different read margins varies with time intervals. That is, the number of load transistors and leek transistors connected to the first and second reference cells are different from each other. The read margin is different depending on the number of load transistors and liquor transistors.

For example, there are two load transistors and two liquor transistors connected to the main cell, four load transistors and two liquor transistors connected to the first reference cell, and a load transistor and a liquor transistor connected to the second reference cell. Six each, the ratio between the main cell and the first and second reference cells is 2: 4 and 2: 6. Therefore, when the current flowing in the main cell is 80 mA or more, the first reference cell recognizes 40 mA or more as an erase cell, and the second reference cell recognizes about 26.67 mA or more as an erase cell. As a result, the first reference cell and the second reference cell have different read margins, whereby the output signals of the respective sense amplifiers are output at time intervals.

5 (a) and 5 (b) are detailed circuit diagrams of the selection delay means of the noise attenuation circuit of the sense amplifier according to the present invention, and FIG. 5 (a) is a circuit diagram of the first selection delay means, and FIG. 5 (b). ) Is a circuit diagram of the second selection delay means.

A driving method of the first selection delay means will be described with reference to Fig. 5A.

The first selection delay means determines a path through which the power supply voltage V _CC is supplied according to the initial output signal SAOUT_int of the sense amplifier. In other words, the 1 PMOS transistor (P11) to the power supply voltage (V _CC) that is input via the 2 PMOS transistor (P12) and a resistor (R11) than the power supply voltage (V _CC) that is inputted through a so as to have a delay of a predetermined time Should be. Therefore, the resistance component of the first PMOS transistor P11 should be made small and the resistance component of the second PMOS transistor P12 should be made large. That is, the width of the first PMOS transistor P11 is made large and the length is made short. By this principle, the first select delay means delays and outputs the output signal SA1b of the first sense amplifier in accordance with the initial output signal SAOUT_int of the sense amplifier.

The circuit driving when the initial output signal SAOUT_int of the sense amplifier in the high state and the output signal SA1b of the first sense amplifier in the high state are input will be described as follows.

The second PMOS transistor P12 is turned off by the initial output signal SAOUT_int of the sense amplifier in the high state, and is inverted to a low state through the first inverter I21, so that the first PMOS transistor P11 is turned on. The power supply voltage V _CC is supplied through the turned on first PMOS transistor P11. On the other hand, the third PMOS transistor P13 of the inverter means is turned off by the first sense amplifier output signal SA1b in the high state, and the first NMOS transistor N11 is turned on to form a path to the ground, thereby providing a node K11. ) Potential becomes low. The potential of the node K11 maintaining the low state is output through the second and third inverters I22 and I23 (SAOUT1).

The circuit driving when the initial output signal SAOUT_int of the sense amplifier in the high state and the output signal SA1b of the first sense amplifier in the low state are input will be described as follows.

The second PMOS transistor P12 is turned off by the initial output signal SAOUT_int of the sense amplifier in the high state, and is inverted to a low state through the first inverter I21, so that the first PMOS transistor P11 is turned on. The power supply voltage V _CC is supplied through the turned on first PMOS transistor P11. On the other hand, since the third PMOS transistor P13 of the inverter means is turned on by the first sense amplifier output signal SA1b in the low state, the first NMOS transistor N11 is turned off to supply the power supply voltage V _CC . The potential of the node K11 becomes high. The potential of the node K11 maintaining the high state is output through the second and third inverters I22 and I23 (SAOUT1).

The circuit driving when the initial output signal SAOUT_int of the sense amplifier in the low state and the output signal SA1b of the first sense amplifier in the high state are input will be described as follows.

Since the second PMOS transistor P12 is turned on by the initial output signal SAOUT_int of the sense amplifier in the low state, and is inverted to a high state through the first inverter I21, the first PMOS transistor P11 is turned off. The power supply voltage V _CC is supplied through the turned-on second PMOS transistor P12 and the resistor R11. By the way, claim 1 PMOS transistor (P11) to the power supply voltage (V _CC) of claim 2 PMOS transistors supply voltage (V _CC) that is input through (P12) and a resistor (R11) compared with the input through to have a delay of a predetermined time Should be. Therefore, the resistance component of the first PMOS transistor P11 should be made small and the resistance component of the second PMOS transistor P12 should be made large. That is, the width of the first PMOS transistor P11 is made large and the length is made short. On the other hand, the third PMOS transistor P13 of the inverter means is turned off by the first sense amplifier output signal SA1b in the high state, and the first NMOS transistor N11 is turned on to form a path to the ground, thereby providing a node K11. ) Potential becomes low. The potential of the node K11 maintaining the low state is output through the second and third inverters I22 and I23 (SAOUT1).

The circuit driving when the initial output signal SAOUT_int of the sense amplifier in the low state and the output signal SA1b of the first sense amplifier in the low state are input will be described as follows.

Since the second PMOS transistor P22 is turned on by the initial output signal SAOUT_int of the sense amplifier in the low state, and is inverted to a high state through the first inverter I21, the first PMOS transistor P11 is turned off. The power supply voltage V _CC is supplied at a predetermined time delay through the turned-on second PMOS transistor P12 and the resistor R11. On the other hand, the third PMOS transistor P13 of the inverter means is turned on by the first sense amplifier output signal SA1b in the low state, and the first NMOS transistor N11 is turned off so that the second PMOS transistor P12 and the resistor are turned off. The delayed power supply voltage V _CC is supplied through R11 so that the potential of the node K11 becomes high. The potential of the node K11 maintaining the high state is output through the second and third inverters I22 and I23 (SAOUT1).

As described above, when the initial output signal SAOUT_int of the sense amplifier is applied to the low state and the output signal SA1b of the first sense amplifier is applied to the low state, the first selection delay means has a high state delayed for a predetermined time. Output the signal (SAOUT1). In addition, the first selection delay means outputs a low state signal when the initial output signal SAOUT_int of the sense amplifier is applied in a low state and the output signal SA1b of the first sense amplifier is applied in a high state (SAOUT1). ). On the other hand, when the initial output signal SAOUT_int of the sense amplifier is applied in a high state, the first selection delay means outputs a power supply voltage without a delay time like a general inverter.

A driving method of the second selection delay means will be described with reference to Fig. 5B.

The second selection delay means determines a path through which the potential of the node K21 passes to ground according to the initial output signal SAOUT_int of the sense amplifier. That is, compared to the potential of the node K21 passing through the second NMOS transistor N22 to the ground, the potential of the node R21 and the node K21 passing through the third NMOS transistor N23 to the ground for a predetermined time. It should be delayed. Therefore, the resistance component of the second NMOS transistor N22 should be made small and the resistance component of the third PMOS transistor N23 should be made large. In other words, the width or length of the second NMOS transistor N22 is increased. By this principle, the second selection delay means delays and outputs the output signal SA0b of the second sense amplifier in accordance with the initial output signal SAOUT_int of the sense amplifier.

The circuit driving when the initial output signal SAOUT_int of the sense amplifier in the high state and the output signal SA0b of the second sense amplifier in the high state are input will be described as follows.

The first PMOS transistor P21 of the inverter means is turned off by the output signal SA0b of the second sense amplifier in the high state, and the first NMOS transistor N21 is turned on. Meanwhile, the third NMOS transistor N23 is turned on by the initial output signal SAOUT_int of the sense amplifier in the high state, and the second NMOS transistor N22 is turned on by the signal inverted to the low state through the first inverter I31. Is turned off. Accordingly, since a path is formed through the first NMOS transistor N21, the resistor R21, and the third NMOS transistor N23 to the ground, the potential of the node K21 becomes low. However, the pass time through the resistor R21 and the third NMOS transistor N23 should be longer than the pass time through the second NMOS transistor N22. Therefore, the resistance component of the second NMOS transistor N22 should be smaller than the resistance component of the third NMOS transistor N23. To this end, the width of the second NMOS transistor N22 is increased or the length is shortened. The potential of the node K21 in the low state is output through the second and third inverters I32 and I33 (SAOUT0).

The circuit driving when the initial output signal SAOUT_int of the sense amplifier in the high state and the output signal SA0b of the second sense amplifier in the low state are input will be described as follows.

The first PMOS transistor P21 of the inverter means is turned on by the output signal SA0b of the second sense amplifier in the low state, and the first NMOS transistor N21 is turned off so that the power supply voltage V _{CC is} connected to the node K21. Is supplied. Meanwhile, the third NMOS transistor N23 is turned on by the initial output signal SAOUT_int of the sense amplifier in the high state, and the second NMOS transistor N22 is turned on by the signal inverted to the low state through the first inverter I31. Is turned off. However, since the first NMOS transistor N21 is turned off, no path is formed to the ground, so that the node K21 maintains the potential of the high state. Therefore, the potential of the node K21 in the high state is output through the second and third inverters I32 and I33 (SAOUT0).

The circuit driving when the initial output signal SAOUT_int of the sense amplifier in the low state and the output signal SA0b of the second sense amplifier in the high state are input will be described as follows.

The first PMOS transistor P21 of the inverter means is turned off by the output signal SA0b of the second sense amplifier in the high state, and the first NMOS transistor N21 is turned on. Meanwhile, the third NMOS transistor N23 is turned off by the initial output signal SAOUT_int of the sense amplifier in the low state, and the second NMOS transistor N22 is inverted to the high state through the first inverter I31. ) Is turned on. Therefore, since a path is formed through the first NMOS transistor N21 and the second NMOS transistor N22 to the ground, the potential of the node K21 becomes low. The potential of the node K21 in the low state is output through the second and third inverters I32 and I33 (SAOUT0).

The circuit driving when the initial output signal SAOUT_int of the sense amplifier in the low state and the output signal SA0b of the second sense amplifier in the low state are input will be described as follows.

The first PMOS transistor P21 of the inverter means is turned on by the output signal SA0b of the second sense amplifier in the low state, and the first NMOS transistor N21 is turned off to the power supply voltage V _CC to the node K21. ) Is supplied. Meanwhile, the third NMOS transistor N23 is turned off by the initial output signal SAOUT_int of the sense amplifier in the low state, and the second NMOS transistor N22 is inverted to the high state through the first inverter I31. ) Is turned on. However, since the first NMOS transistor N21 maintains the turn-off state, the node K21 maintains the high potential because the first NMOS transistor N21 does not form a path to the ground. The potential of the node K21 in the high state is output through the second and third inverters I32 and I33 (SAOUT0).

As described above, the second selection delay means has a low state delayed for a predetermined time when the initial output signal SAOUT_int of the sense amplifier is applied to the high state and the output signal SA0b of the second sense amplifier is applied to the high state. Output the signal (SAOUT0). In addition, the second select delay means outputs a high state signal when the initial output signal SAOUT_int of the sense amplifier is applied in a high state and the output signal SA0b of the second sense amplifier is applied in a low state (SAOUT0). ). On the other hand, when the initial output signal SAOUT_int of the sense amplifier is applied in the low state, the second selection delay means inverts the output signal of the second sense amplifier without delay time and outputs the same as a general inverter.

In the selection delay means of the noise attenuation circuit of the sense amplifier according to the present invention operating as described above, when the initial output signal SAOUT_int of the sense amplifier is applied in a low state, the first selection delay means is operated so that The output signal SA1b is inverted for a predetermined time and outputted. In addition, when the initial output signal SAOUT_int of the sense amplifier is applied to the high state, the second selection delay means operates to output the delayed inverted output signal SA0b of the second sense amplifier by a predetermined time.

6 is a detailed circuit diagram of data transmission means of the noise attenuation circuit of the sense amplifier according to the present invention.

According to the initial output signal SAOUT_int of the sense amplifier, the output signal SA1b of the first sense amplifier is inverted through the first inverter I41 and input to the first transfer gate M1 and the output signal of the second sense amplifier. SA0b is inverted through the second inverter I42 and input to the second transfer gate M2.

A driving method when the initial output signal SAOUT_int of the sense amplifier is input to the high state will be described below.

The NMOS transistor of the first transfer gate M1 is turned on and the PMOS transistor of the second transfer gate M2 is turned off by the initial output signal SAOUT_int of the sense amplifier input in the high state. The initial output signal SAOUT_int of the sense amplifier input to the high state is inverted to the low state through the third inverter I43 so that the PMOS transistor of the first transfer gate M1 is turned on and the second transfer gate M2 is turned on. The NMOS transistor is turned off. Therefore, only the first transfer gate M1 is turned on to transmit the output signal SA1b of the first sense amplifier. If the output signal SA1b of the first sense amplifier is input to the high state, the output signal SA1b is inverted to the low state through the first inverter I41 (SA1). The signal SA1 inverted to the low state is transmitted through the first transmission gate M1 and output after being delayed for a predetermined time through the first delay means (SAOUT2). On the other hand, when the output signal SA1b of the first sense amplifier is input in the low state, the high state signal is output after a predetermined time delay (SAOUT2).

A driving method when the initial output signal SAOUT_int of the sense amplifier is input to the low state will be described below.

The NMOS transistor of the first transfer gate M1 is turned off and the PMOS transistor of the second transfer gate M2 is turned on by the initial output signal SAOUT_int of the sense amplifier input in the low state. The initial output signal SAOUT_int of the sense amplifier input to the low state is inverted to the high state through the third inverter I43 so that the PMOS transistor of the first transfer gate M1 is turned off and the second transfer gate M2 is turned off. The NMOS transistor is turned on. Thus, only the second transfer gate M2 is turned on to transmit the output signal SA0b of the second sense amplifier. If the output signal SA0b of the second sense amplifier is input to the high state, the output signal SA0b is inverted to the low state through the second inverter I42 (SA0). The signal SA0 inverted to the low state is transmitted through the second transfer gate M2 and output after being delayed for a predetermined time through the first delay means (SAOUT2). On the other hand, when the output signal SA0b of the second sense amplifier is input in the low state, the high state signal is output after a predetermined time delay (SAOUT2).

As described above, when the initial output signal SAOUT_int of the sense amplifier is input to the high state, the data transmission means inverts and outputs the output signal SA1b of the first sense amplifier, and outputs the initial output signal SAOUT_int of the sense amplifier. Is input in a low state, the output signal SA0b of the second sense amplifier is inverted and delayed.

7 is a detailed circuit diagram of the noise attenuation means of the noise attenuation circuit of the sense amplifier according to the present invention, and FIG. 8 is a block diagram of the control means of the noise attenuation means.

The noise attenuation means is operated by inputting the output signal SAOUT1 of the first selection delay means, the output signal SAOUT0 of the second selection delay means and the output signal SAOUT2 of the data transmission means.

The output signal SAOUT1 of the first selection delay means and the output signal SAOUT0 of the second selection delay means are inputted with different signals by a time delayed by the selection delay means, thereby forming an exclusive OR gate (hereinafter, referred to as an XOR gate). Since the enable signal SAOUTEN of the high state is output through (), the first inverting means 21 is disabled. That is, the first PMOS transistor P31 of the first inverting means 21 is turned off by the enable signal SAOUTEN in the high state and is inverted to the low state through the first inverter I51. The second NMOS transistor N32 is turned off and the first inverting means 21 is disabled. Therefore, the data latched in the latch means 23 is inverted and output through the second inverter I52 (SAOUT).

After the delayed time in the select delay means, the output signal SAOUT1 of the first select delay means and the output signal SAOUT0 of the second select delay means have the same state. Output the signal SAOUTEN. The first PMOS transistor P31 of the first inverting means 21 is turned on by the enable signal SAOUTEN in the low state and the second NMOS transistor N32 by the signal inverted through the first inverter I51. ) Is turned on. The second PMOS transistor P32 and the first NMOS transistor N31 of the first inverting means 21 operate according to the output signal SAOUT2 of the data transfer means. That is, when the output signal SAOUT2 of the data transfer means is in a high state, the second PMOS transistor P32 is turned off and the first NMOS transistor N31 is turned on to form a path to the ground. Therefore, the output signal SAOUTb of the first inverting means 21 goes low. On the other hand, when the output signal SAOUT2 of the data transfer means is low, the second PMOS transistor P32 is turned on, and the first NMOS transistor N31 is turned off to supply the power supply voltage V _CC . Therefore, the output signal SAOUTb of the first inverting means 21 goes high.

The second inverting means 22 is a sense amplifier delay enable signal SA_DEL_EN input through the output signal SAOUTb of the first inverting means and the control means of the noise attenuation means shown in FIG. Driven by SA_DEL_ENb). That is, the third PMOS transistor P33 is driven according to the sense amplifier delay enable signal SA_DEL_EN, and the fourth PMOS transistor P34 and the third NMOS transistor N33 are output signals SAOUTb of the first inverting means. The fourth NMOS transistor N34 is driven according to the sense amplifier delay enable bar signal SA_DEL_ENb.

The sense amplifier delay enable signal SA_DEL_EN and the sense amplifier delay enable bar signal SA_DEL_ENb are output through the control means of the noise attenuation means shown in FIG.

The sense amplifier delay enable signal SA_DEL_EN is a signal obtained by delaying the output signal SAOUTEN of the XOR gate of the noise attenuation means through a second delay means for a predetermined time, and the sense amplifier delay enable bar signal SA_DEL_ENb is an inverter. This signal is inverted and output through (I).

Accordingly, when the output signal SAOUTb of the first inverting means 21 is low and the sense amplifier delay enable signal SA_DEL_EN is low, the second inverting means 22 is enabled and the latch means ( The low state signal is outputted through the 23) and the second inverter I52. On the other hand, when the output signal SAOUTb of the first inverting means 21 is high and the sense amplifier delay enable signal SA_DEL_EN is high, the second inverting means 22 is disabled and the latch means ( The high state signal is output through the 23) and the second inverter I52.

The reason why the control circuit as shown in FIG. 8 is used is as follows. If the width of the cleat is larger than the set value, the false data by the cleat is output to the output buffer. This is fed back again to operate in the opposite manner as described above, which in the worst case enables the first inverting means of the noise attenuation means and inverts the output signal SAOUT2 of the data transmission means. In other words, a problem that may arise when the glitch of the first and second sense amplifiers is greater than a given delay time in the first and second select delay means, i.e., after the first inverting means of the noise attenuation means are enabled As the output signal SAOUT2 of the data transmission means which is one input signal of the first inverting means is changed, new glitches are generated in the final output signal SAOUT. However, at the time when the output signal SAOUT2 of the data transmission means changes, the output signal SAOUT2 of the data transmission means changes after the delay time of the data transmission means in the worst case after the first inverting means is enabled. Therefore, the above problem can be solved by using the control means.

9 is a timing diagram in each means of the noise attenuation circuit of the sense amplifier according to the present invention, which shows a timing diagram when transitioning from a high state to a low state. As shown, by setting a new reference sensing node SEN_REFD_NEW having a larger sensing margin than the reference sensing node SENREFD, it can be seen that the glitch is improved by the conventional means.

10 and 11 are graphs showing simulation results when transitioning from a high state to a low state and a transition from a low state to a low state in order to compare a circuit according to the present invention with a conventional circuit. It can be seen that the glitches are significantly improved compared to the above.

As described above, according to the present invention, the device can be stably operated by outputting data with significantly attenuated noise, and glitches can be effectively removed without using an address transition detection circuit and an auxiliary circuit as compared to a conventional circuit. The size can be reduced.

Claims (11)

First and second sense amplifiers having different load ratios and outputting different signals according to common memory cells and first and second reference cells, Selection delay means for selectively delaying and outputting the output signals of the first and second sense amplifiers according to the initial output signal of the sense amplifier; Data transmission means for delaying and outputting any one of an output signal of the first sense amplifier and an output signal of the second sense amplifier according to an initial output signal of the sense amplifier by a set time; And noise attenuation means for outputting a signal in which the noise is attenuated in accordance with the output signal of the first selection delay means, the output signal of the second selection delay means, and the output signal of the data transmission means. Attenuation circuit. 2. The apparatus of claim 1, wherein the selection delay means comprises: first selection delay means for delaying the selection of the output signal of the first sense amplifier; And second selection delay means for selectively delaying the output signal of the second sense amplifier. 3. The apparatus of claim 2, wherein the first select delay means comprises: first inverting means for inverting an initial output signal of the sense amplifier; First switching means for supplying a power supply voltage according to an initial output signal of the sense amplifier inverted through the inverter; Second switching means for delaying and supplying a power supply voltage in accordance with an initial output signal of the sense amplifier; And second inverting means for inverting the output signal of the first sense amplifier. 4. The noise of a sense amplifier according to claim 3, wherein the first and second switching means comprise first and second PMOS transistors, wherein the second PMOS transistor has a larger resistance value than the first PMOS transistor. Attenuation circuit. 3. The apparatus of claim 2, wherein the second select delay means comprises: first inverting means for inverting an output signal of the second sense amplifier; Second inverting means for inverting the initial output signal of the sense amplifier; First switching means for dropping an output signal to ground potential in accordance with an initial output signal of the sense amplifier inverted through the second inverting means; And second switching means for delaying the output signal by a predetermined time and dropping it to the ground potential according to the initial output signal of the sense amplifier. The noise of the sense amplifier according to claim 5, wherein the first and second switching means comprise first and second NMOS transistors, and the resistance value of the second NMOS transistor is larger than that of the first NMOS transistor. Attenuation circuit. 2. The apparatus of claim 1, wherein the data transmitting means comprises: a first transmission gate for transmitting an inverted signal of the output signal of the first sense amplifier in accordance with an initial output signal of the sense amplifier and an inverted signal thereof; A second transfer gate for transmitting an inverted signal of the output signal of the second sense amplifier to an initial output signal of the sense amplifier and in accordance with its inverted signal; And delay means for delaying and outputting the signals output through the first and second transmission gates for a predetermined time. 2. The apparatus of claim 1, wherein the noise attenuation means comprises: logic means for logically combining the output signals of the first and second selection delay means; First inverting means for adjusting an output signal in accordance with an output signal of the logic means and an output signal of the data transmission means; Delay means for delaying an output signal of the logic means for a predetermined time; Second inverting means for inverting the output signal of the delay means; Third inverting means for adjusting an output signal according to the output signal of the delay means, the output signal of the second inverting means and the output signal of the first inverting means; And a fourth inverting means for inverting the output signal of the third inverting means. 9. The noise attenuation circuit of claim 8 wherein the logic means is an XOR gate. 9. The apparatus of claim 8, wherein the first inverting means comprises: a first PMOS transistor supplying a power supply voltage in accordance with an output signal of the logic means; A second PMOS transistor for adjusting an output signal to a power supply voltage level in accordance with an output signal of the data transmission means; A first NMOS transistor for adjusting the output signal to a ground potential according to the output signal of the data transfer means; And a second NMOS transistor for adjusting the output signal to ground potential according to the inverted signal of the logic means. 9. The apparatus of claim 8, wherein the third inverting means comprises: a first PMOS transistor supplying a power supply voltage in accordance with an output signal of the delay means; A second PMOS transistor for adjusting the output signal to a power supply voltage level according to the output signal of the first inverting means; A first NMOS transistor for dropping an output signal to ground potential according to the output signal of the first inverting means; And a second NMOS transistor for lowering the output signal to the ground potential according to the output signal of the second inverting means.