KR20000014192A - Thin film transistor manufacturing method - Google Patents

Abstract

PURPOSE: An LDD area or an off-set area is formed by the heat treatment of a photosensitive pattern for the formation of a gate electrode and the use of the re-flowed photosensitive pattern as a mask and the doping of impurities with a high density on both sides of an activating layer. Consequentially, only one mask procedure is necessary and a miss alignment is prevented. Also the thin film transistor manufacturing process becomes simple and the manufacturing cost is reduced. CONSTITUTION: A buffer layer (12), an activating layer (13) and a gate dielectric layer(14) are formed on a substrate (11) successively. After an electric conducting layer (15) is formed in the whole area of the gate dielectric layer (14) and a photosensitive film is painted on the electric conducting layer (15), the photosensitive film is patterned. The patterned photosensitive film (PR) used as an etching mask etches the electric conducting layer (15) and a gate electrode (15a) is formed. After the patterned photosensitive film (PR) is heated and re-flowed, impurities of a high density is doped, with the re-flowed photosensitive film (RPR) used as the mask, in the activating layer (13), and a drain and source area (13a) is formed. After that, the re-flowed photosensitive film (RPR) is removed. Consequentially, a channel area (I) is formed in the activating layer (13) of the lower gate electrode (15a) and an off-set area (II) is formed between the drain (13b) and the source area(13b) and the channel area(I).

Description

Method of manufacturing thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor which reduces leakage current flowing through a channel of a thin film transistor when the thin film transistor is formed by forming an offset or LDD region in a channel region of the thin film transistor. .

Thin film transistors (TFTs) using polysilicon, which have greater carrier mobility than amorphous silicon, have excellent switching characteristics and can be more large-area compared to thin film transistors using amorphous silicon. The driving circuit for driving the pixels of the liquid crystal display device can be formed on the same substrate as the thin film transistor.

In the liquid crystal display using the polysilicon thin film transistor, the aperture ratio and the driving circuit can be formed on the same substrate, while the large leakage current flowing between the drain and the source of the thin film transistor when the thin film transistor is off, that is, the off current (Off) There is a problem that (Current) occurs.

By forming an undoped offset region or a lightly doped drain (LDD) region doped with a low concentration of impurities in the channel region of the thin film transistor, an off current, which is a leakage current when the thin film transistor is turned off, can be reduced.

Referring to the accompanying drawings, a conventional thin film transistor for forming an offset or LDD region for reducing leakage current in a thin film transistor is as follows.

2A and 2B illustrate a conventional thin film transistor using two photoresist patterns.

It is a cross-sectional structure diagram.

A method of manufacturing a conventional thin film transistor of FIGS. 2A and 2B is as follows.

As shown in FIG. 2A, after forming the buffer layer 2 and the polysilicon on the glass substrate 1, the polysilicon is patterned using a photolithography process to form the active layer 3. . A gate oxide film 4 is formed by entirely depositing a silicon oxide film as an insulating material on the active layer 3. After depositing a metal film on the entire surface of the gate oxide film 4 to form a first photosensitive film pattern PR1 on the metal film using a photolithography process, the metal film is etched using the first photosensitive film pattern PR1 as an etch mask. The metal gate electrode 5 is formed, and the active layer 3 is doped with a low concentration of impurities in the active layer 3 using the first photoresist pattern PR1 as a mask to form the active layer 3a and the channel region I. do. As shown in FIG. 2B, the first photoresist pattern PR1 is removed, a second photoresist pattern PR2 is formed on the gate oxide film 4 using a photolithography process, and the second photoresist pattern PR2 is formed. As a mask, high concentrations of impurities are doped on both sides of the active layer 3. As a result, the active layer 3 is lightly doped in the LDD region II and the heavily doped drain by the thickness of the second photoresist pattern PR2 formed on the sidewall of the metal gate electrode 5 by the low concentration and the high concentration of impurity doping. And a source region 3b and an undoped channel region I are formed.

In addition, instead of doping a low concentration of impurities into the active layer 3 using the first photoresist pattern PR1 as a mask, a subsequent process is performed, thereby undoping offset instead of the low concentration doped LDD region (II). Region (II) can be formed.

3 is a cross-sectional structure diagram of another conventional thin film transistor using anodization.

In another conventional thin film transistor of FIG. 3, as shown in FIG. 2A, a metal gate electrode 5 is formed using a first photoresist pattern, and a low concentration of impurities are formed in the active layer 3 using the first photoresist pattern as a mask. After the doping, the first photoresist pattern PR1 is removed, and the second photoresist pattern PR2 is not formed, the substrate on which the metal gate electrode 5 is formed and the stainless steel are placed in an ammonium tartrate solution. An anodization film 6 is formed on both sidewalls and the upper surface of the metal gate electrode 5 by anodization applying a bias between the stainless steel and the stainless steel, and the anodization film 6 is masked. The doped impurities are doped with high concentrations on both sides of the active layer 3 to form the LDD region II, which is lightly doped, the drain and source region 3c that are heavily doped, and the undoped channel region I.

Therefore, in the conventional thin film transistors of FIGS. 2A, 2B, and 3, an electric field applied between the drain and source regions 3b and 3c and the gate electrode 5 by the offset or LDD region II formed in the active layer 3 is formed. Therefore, the leakage current between the drain terminal and the source terminal is reduced when the thin film transistor is off, thereby improving off current characteristics of the thin film transistor.

In the conventional thin film transistor manufacturing method of forming an offset or LDD region using the first photoresist pattern and the second photoresist pattern, the process of manufacturing a thin film transistor is complicated because two mask processes must be performed to form an offset or LDD region. In addition, two exposure apparatuses should be used to pattern the first and second photoresist layers, but there is a problem in that misalignment may occur due to limitations of the exposure apparatus.

The conventional thin film transistor manufacturing method of forming an offset or LDD region using the anodic oxide film has a problem in that separate equipment for forming the anodic oxide film is required.

An object of the present invention is to heat the photoresist pattern for forming the gate electrode and to reflow, and then use the reflowed photoresist pattern as a mask to dope a high concentration of impurities on both sides of the active layer to form an LDD region or an offset region. Since a mask process is required, the occurrence of misalignment can be prevented, and the thin film transistor manufacturing process is simplified, thereby providing a thin film transistor manufacturing method that can reduce manufacturing costs.

The thin film transistor manufacturing method of the present invention for achieving the above object comprises the steps of sequentially forming a buffer layer, an active layer and a gate insulating layer on the substrate; Forming a conductive layer on the entire surface of the gate insulating layer, applying a photosensitive film on the conductive layer, and then patterning the conductive layer by etching the patterned photosensitive film with an etch mask to form a gate electrode; A photoresist heat treatment step of reflowing the patterned photoresist by heat treatment; Forming a drain and source region by doping a high concentration of impurities into the active layer using the photoresist film reflowed in the photoresist heat treatment step as a mask; And removing the reflowed photoresist after forming the drain and source regions, such that a channel region is formed in the active layer under the gate electrode, and an offset region is formed between the drain region and the channel region and between the source region and the channel region. It is characterized by.

The method of manufacturing a thin film transistor according to the present invention further comprises doping an active layer with a low concentration of impurities using a patterned photoresist as a mask after forming a gate electrode, thereby forming an LDD region between a drain region and a channel region, and between a source region and a channel region. Can be formed.

The photoresist heat treatment step is a heat treatment in a temperature range of 120 degrees to 250 degrees, the conductive layer is made of polycrystalline silicon or metal.

1A to 1G illustrate a method of manufacturing a thin film transistor according to the present invention.

Process flow chart,

2A and 2B are cross-sectional structural diagrams of a conventional thin film transistor using two photosensitive film patterns;

3 is a cross-sectional structural view of another conventional thin film transistor using anodization.

Hereinafter, a method of manufacturing a thin film transistor of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1G are flowcharts illustrating a method of manufacturing a thin film transistor according to the present invention.

In the method of manufacturing the thin film transistor of the present invention, the buffer layer 12, the active layer 13, and the gate insulating layer 14 are sequentially formed on the substrate 11, and the conductive layer 15 is formed on the entire surface of the gate insulating layer 14. ) To form a gate electrode 15a by etching the conductive layer 15 using the patterned photoresist film PR as an etch mask after patterning the photoresist film on the conductive layer 15. The photoresist heat treatment step of reflowing by heat treatment of PR) and the photoresist film (RPR) reflowed in the photoresist heat treatment step as a mask doped with a high concentration of impurities in the active layer 13 to form the drain and source region 13b. And removing the reflowed photoresist film RRP after the drain and source regions 13b are formed, and thus the channel region I is formed in the active layer 13 under the gate electrode 15a. Between source 13b and channel region I The station (13b) and the offset region between the channel region (Ⅰ) (Ⅱ) is formed.

In the method of manufacturing the thin film transistor of the present invention, after the gate electrode 15a is formed, a step of doping a low concentration of impurities in the active layer 13 using the patterned photoresist film PR as a mask is further provided for the drain region 13b. LDD region (II) can be formed between the channel region (I) and between the source region 13b and the channel region (I).

The photoresist heat treatment step is a heat treatment in a temperature range of 120 to 250 degrees, the conductive layer 15 may be made of a material of polycrystalline silicon or metal.

The active layer 13 is formed by depositing polycrystalline silicon on top of the buffer layer 12 and patterning it, or depositing amorphous silicon on the buffer layer 12 and then recrystallizing amorphous silicon to form polycrystalline silicon and patterning polycrystalline silicon. Can be formed.

A method of manufacturing the thin film transistor of the present invention will be described with reference to FIGS. 1A to 1G.

As shown in FIG. 1A, the buffer layer 12, the active layer 13, and the gate insulating layer 14 are sequentially formed on the glass substrate 11. The buffer layer 12 is formed to have a thickness of 500 kV to 2500 kV on the entire surface of the glass substrate 11 by using chemical vapor deposition or physical vapor deposition. The active layer 13 is directly patterned by depositing polysilicon or patterning polysilicon formed by recrystallizing amorphous silicon by laser annealing which deposits amorphous silicon to a thickness of 500 Å to 1000 Å at low temperature and irradiates a laser beam. Can be formed. Therefore, since the active layer 13 can be formed at low temperature by patterning polycrystalline silicon formed by recrystallization of amorphous silicon, the substrate 11 can use an inexpensive glass substrate, which is advantageous in terms of mass production and manufacturing cost. The gate insulating layer 14 is formed of an insulating material, such as a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiNx), by using a chemical vapor deposition method or a physical vapor deposition method, to a thickness of 500 kPa to 2000 kPa.

As shown in FIG. 1B, aluminum (Al), chromium (Cr), cobalt (Co), iridium (Ir), manganese (Mn), nickel (Ni), and palladium (Pd) are formed on the entire surface of the gate insulating layer 14. And a conductive layer 15 made of any one of lead (Pt) or a mixed metal of tungsten (W) metal and molybdenum (Mo) metal, or polycrystalline silicon, at a thickness of 2000 kPa to 5000 kPa, and using a photographic process. The photosensitive film pattern PR is formed on the conductive layer 15. Since the conductive layer 15 is used as a gate electrode in a later step, it is advantageous to form the conductive layer 15 with a metal material rather than polycrystalline silicon in order to reduce the delay time of the signal applied to the gate electrode.

As illustrated in FIG. 1C, the conductive layer 15 is etched with etching gases including carbon fluoride gases CF ₄ and CHF ₃ and inert gases He and Ar, using the photoresist pattern PR as an etching mask. The gate electrode 15a is formed.

As shown in FIG. 1D, a low concentration of about 10 ¹³ / cm 2 is ion-implanted into the active layer 13 to form an LDD region and a channel region using the photoresist pattern PR as a mask and doped with a low concentration of impurities. The active layer 13a is formed.

As shown in FIG. 1E, the substrate 11 on which the photoresist pattern PR is formed is heat-treated in a temperature atmosphere of 120 to 250 degrees to reflow the photoresist pattern PR to both sidewalls of the gate electrode 15a. The photoresist pattern RRP may be formed on both sidewalls and the upper portion of the gate electrode 15a.

Thereafter, as shown in FIG. 1F, a high concentration of impurities of about 10 ¹⁶ / cm 2 is ion-implanted by a self-aligned method using the reflowed photoresist pattern RRP as a mask to drain and source the active layer 13. The region 13b is formed.

Therefore, a low concentration of impurities are ion-implanted into the active layer 13 using the photoresist pattern PR as a mask, and the reflowed photoresist pattern RRP formed by reflowing the photoresist pattern PR is used as a mask. A high concentration of impurities are implanted into the active layer 13 to form a drain and source region 13b doped with a high concentration of impurities, and a channel region I is formed in the active layer 13 under the gate electrode 15a. The LDD region II doped with a low concentration of impurities is formed between the drain region 13b and the channel region I and between the source region 13b and the channel region I.

As shown in FIG. 1G, after the drain, the source region 13b, the channel region I and the LDD region II are formed in the active layer 13, the reflowed photoresist pattern RRP is removed, and the gate electrode ( 15a) and a passivation layer 16 over the gate insulating layer 14, and drain and source regions 13b for applying electrical signals with the drain and source regions 13b in the active layer 13; Contact holes are formed in the upper gate insulating layer 14 and the passivation layer 16, and a conductive layer is formed on the entire surface of the passivation layer 16 and then patterned to form drain and source electrodes 17.

As shown in FIG. 1C, the photoresist pattern PR may be formed as shown in FIG. 1C without using the photoresist pattern PR illustrated in FIG. 1D as a mask. The conductive layer 15 is etched using the etching mask to form the gate electrode 15a, and the reflowed photoresist pattern RRP is masked by reflowing the photoresist pattern PR as shown in FIGS. 1E and 1F. In this case, when a high concentration of impurities are implanted into the active layer 13, the offset region II between the drain region 13b and the channel region I and between the source region 13b and the channel region I in the active layer 13. Can be formed.

Therefore, according to the method of manufacturing the thin film transistor of the present invention, a high concentration of impurities are doped into the active layer 13 using a reflowed photoresist pattern RRP formed by reflowing the photoresist pattern PR for forming the gate electrode 15a. The leakage current of the thin film transistor can be reduced by forming the channel region (I) and the LDD region or offset region (II) doped with a low concentration of impurities.

According to the present invention, a mask process is performed by heat-treating a photoresist pattern for forming a gate electrode and then reflowing the photoresist pattern to form an LDD region or an offset region by doping a high concentration of impurities on both sides of the active layer using the reflowed photoresist pattern as a mask. Because of this requirement, the occurrence of misalignment can be prevented, and the thin film transistor manufacturing process can be simplified, thereby reducing the manufacturing cost.

Claims (7)

In the thin film transistor manufacturing method for reducing the leakage current of the thin film transistor, Sequentially forming a buffer layer, an active layer, and a gate insulating layer on the substrate; Forming a conductive layer on the entire surface of the gate insulating layer, applying a photosensitive film on the conductive layer, and patterning the conductive layer using an patterned photosensitive film as an etching mask to form a gate electrode; A photoresist heat treatment step of reflowing the patterned photoresist by heat treatment; Forming a drain and source region by doping a high concentration of impurities into the active layer using the photoresist film reflowed in the photoresist heat treatment step as a mask; And And removing the reflowed photoresist after forming the drain and source regions, wherein a channel region is formed in the active layer under the gate electrode, between the drain region and the channel region, and between the source region and the source region. A thin film transistor manufacturing method characterized in that the offset region is formed between the channel region. The method of claim 1, further comprising doping the active layer with a low concentration of impurities using the patterned photoresist as a mask after the gate electrode is formed, between the drain region and the channel region and between the source region and the source region. A thin film transistor manufacturing method, characterized in that the LDD region is formed between the channel region. The method of claim 1, wherein the conductive layer is made of polycrystalline silicon. The method of claim 1, wherein the heat treatment of the photoresist film is performed in a temperature range of 120 to 250 degrees. The method of claim 1, wherein the conductive layer is formed of a metal material. The method of claim 1, wherein the active layer is made of polycrystalline silicon. The method of claim 1, wherein the active layer is Depositing amorphous silicon on the buffer layer and recrystallizing the amorphous silicon to form polycrystalline silicon; And A method of manufacturing a thin film transistor, comprising the step of patterning the polycrystalline silicon.