KR20000013247A - Wet etching method of polysilicon - Google Patents
Wet etching method of polysilicon Download PDFInfo
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- KR20000013247A KR20000013247A KR1019980032007A KR19980032007A KR20000013247A KR 20000013247 A KR20000013247 A KR 20000013247A KR 1019980032007 A KR1019980032007 A KR 1019980032007A KR 19980032007 A KR19980032007 A KR 19980032007A KR 20000013247 A KR20000013247 A KR 20000013247A
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- etching
- wet etching
- polysilicon film
- polysilicon
- wet
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 47
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 47
- 238000001039 wet etching Methods 0.000 title claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 44
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000008367 deionised water Substances 0.000 claims abstract description 3
- 229910021641 deionized water Inorganic materials 0.000 claims abstract description 3
- 238000007654 immersion Methods 0.000 claims description 7
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 6
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 229910017855 NH 4 F Inorganic materials 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 5
- 229920000642 polymer Polymers 0.000 abstract description 5
- 239000007788 liquid Substances 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Weting (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 습식식각을 이용한 폴리실리콘막의 식각방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an etching method of a polysilicon film using wet etching.
현재 게이트 폭이 2㎛에 해당하는 로직(LOGIC)과 같은 일반적인 반도체 소자에 있어서, 폴리실리콘으로 구성된 게이트 전극의 식각은 등방성 건식식각(isotropic dry etching)을 이용하여 진행하고 있다. 그러나, 건식식각의 경우 폴리실리콘막 단면(Profile)의 재현성 불량, 콘택홀의 불량을 야기하고 임계치수를 높게 하는 폴리머(Polymer)의 발생 및 금속배선(metal)의 단선(short)을 일으키는 파티클의 발생등이 주요한 문제점이다. 이에 따라 상술한 문제점을 없애고 좀더 수직에 가까운 재현성있는 단면(profile)을 갖는 폴리실리콘으로 된 게이트 전극에 대한 식각방법이 요구된다.Currently, in a general semiconductor device such as a logic (LOGIC) having a gate width of 2 μm, etching of a gate electrode made of polysilicon is performed using isotropic dry etching. However, in the case of dry etching, there is a defect in reproducibility of the polysilicon profile, generation of polymers that cause contact hole defects and a high critical dimension, and generation of particles that cause short circuits of metals. This is a major problem. Accordingly, there is a need for an etching method for a gate electrode made of polysilicon which eliminates the above-described problems and has a more vertical reproducible profile.
도 1 내지 도 3은 종래 기술에 의한 폴리실리콘막의 식각방법을 설명하기 위해 도시한 단면도들이다.1 to 3 are cross-sectional views illustrating a method of etching a polysilicon film according to the prior art.
도 1을 참고하면, 반도체 기판(50)에 소자분리 공정을 진행한 후, 게이트 산화막(52)을 형성하고, 게이트 전극용 폴리실리콘막(54)을 적층한다. 이어서, 게이트 전극용 폴리실리콘막(54)을 식각하기 위한 포토레지스트 막을 도포(coating)하고 현상공정을 진행하여 폴리실리콘막(54)의 일부를 노출시키는 포토레지스트 패턴(56)을 형성한다.Referring to FIG. 1, after a device isolation process is performed on a semiconductor substrate 50, a gate oxide film 52 is formed, and a polysilicon film 54 for a gate electrode is stacked. Subsequently, a photoresist film for etching the polysilicon film 54 for the gate electrode is coated and a development process is performed to form a photoresist pattern 56 exposing a portion of the polysilicon film 54.
도 2를 참조하면, 상기 포토레지스트 패턴(56)이 형성된 결과물에 염소(Cl2) 또는 육불화황(SH6) 가스를 이용한 등방성의 건식식각을 진행하여 하부 폴리실리콘막(54)의 일부를 식각하여 폴리실리콘 패턴(58)을 형성한다. 이때 게이트 산화막(52)의 일부된 함께 식각된다.Referring to FIG. 2, an isotropic dry etching process using chlorine (Cl 2 ) or sulfur hexafluoride (SH 6 ) gas is performed on the resultant on which the photoresist pattern 56 is formed to partially remove the lower polysilicon layer 54. Etching is performed to form the polysilicon pattern 58. At this time, portions of the gate oxide layer 52 are etched together.
도 3을 참조하면, 상기 등방성 건식식각이 완료된 반도체 기판에서 포토레지스트 패턴(56)을 제거하여 게이트 전극 패턴에 대한 식각을 완료한다.Referring to FIG. 3, the etching of the gate electrode pattern is completed by removing the photoresist pattern 56 from the isotropic dry etching completed semiconductor substrate.
그러나, 종래기술은 폴리실리콘으로 구성된 게이트 패턴의 측면 프로파일(profile)이 30∼80도 사이의 경사를 보이고, 또한 식각과정에서 다량의 폴리머(polymer)를 생성하고 파티클을 발생시켜 반도체 소자의 신뢰성을 떨어뜨리며 이로 인해 공정의 재현성이 떨어지는 문제점이 있다.However, in the prior art, the side profile of the gate pattern made of polysilicon shows an inclination of 30 to 80 degrees, and also generates a large amount of polymer and generates particles during the etching process, thereby improving reliability of the semiconductor device. There is a problem in that the fall of the process and the reproducibility of the process.
본 발명이 이루고자 하는 기술적 과제는 폴리실리콘막의 측면 프로파일을 개선하고 공정의 재현성을 향상시키고 폴리머 및 파티클의 발생을 억제할 수 있는 폴리실리콘막의 습식식각 방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a wet etching method of a polysilicon film capable of improving side profile of a polysilicon film, improving reproducibility of a process, and suppressing generation of polymers and particles.
도 1 내지 도 3은 종래 기술에 의한 폴리실리콘막의 식각방법을 설명하기 위해 도시한 단면도들이다.1 to 3 are cross-sectional views illustrating a method of etching a polysilicon film according to the prior art.
도 4 내지 도 6은 본 발명에 의한 폴리실리콘막의 습식식각 방법을 설명하기 위해 도시한 단면도들이다.4 to 6 are cross-sectional views for explaining a wet etching method of a polysilicon film according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100: 반도체 기판, 102: 게이트 산화막,100: semiconductor substrate, 102: gate oxide film,
104: 폴리실리콘막, 106: 포토레지스트 패턴,104: polysilicon film, 106: photoresist pattern,
108: 폴리실리콘 패턴.108: polysilicon pattern.
상기 기술적 과제를 달성하기 위하여 본 발명은, 반도체 기판에 게이트 산화막과, 게이트 전극용 폴리실리콘막을 적층하는 공정과, 상기 폴리실리콘막 상부에 포토레지스트 패턴을 형성하는 공정과, 상기 포토레지스트 패턴을 식각마스크로 하부의 폴리실리콘막을 식각하는 공정으로 구성된 폴리실리콘막의 식각공정에 있어서, 상기 식각은 습식식각으로 식각액을 불산(HF)과 질산(HNO3)과 순수한 물(Deionized water)의 혼합비가 1:50:25인 식각액을 사용하는 것을 특징으로 하는 폴리실리콘막의 습식식각 방법을 제공한다.In order to achieve the above technical problem, the present invention is a process for laminating a gate oxide film and a polysilicon film for a gate electrode on a semiconductor substrate, forming a photoresist pattern on the polysilicon film, and etching the photoresist pattern In the etching process of the polysilicon film consisting of the process of etching the lower polysilicon film with a mask, the etching is wet etching the mixing ratio of hydrofluoric acid (HF), nitric acid (HNO 3 ) and pure water (Deionized water) is 1: Provided is a wet etching method of a polysilicon film using an etching solution of 50:25.
본 발명의 바람직한 실시예에 의하면, 상기 습식식각은 식각액의 온도를 24±2℃의 환경에서 진행하고, 식각조(bath)에서 식각액을 순환(circulation)시키고, 식각될 반도체 기판이 담긴 캐리어(carrier)를 흔들어 주면서 습식식각을 진행하는 것이 적합하다.According to a preferred embodiment of the present invention, the wet etching is carried out in an environment of the temperature of the etching solution in the environment of 24 ± 2 ℃, circulating the etching solution in the bath (bath), the carrier (carrier) containing the semiconductor substrate to be etched It is appropriate to perform wet etching by shaking).
상기 습식식각은 폴리실리콘막을 140∼150%의 범위로 오버에칭(over etching)하는 것이 적합하다.In the wet etching, it is suitable to overetch the polysilicon film in the range of 140 to 150%.
바람직하게는, 상기 습식식각을 진행한 후에 불산과 불화암모늄이 10:1의 비율로 혼합된 용액을 액조(bath)에 투입하고 31±1℃의 환경에서 담굼처리(DIP)를 더 진행하는 것이 적합하고, 이때에도 액조(bath)에서 용액을 순환(circulation)시키면서 담굼처리를 3±2초간 진행하는 것이 적합하다.Preferably, after the wet etching, a solution in which hydrofluoric acid and ammonium fluoride are mixed at a ratio of 10: 1 is added to a bath, and further dipping is performed in an environment of 31 ± 1 ° C. In this case, it is also suitable to proceed the immersion treatment for 3 ± 2 seconds while circulating the solution in a bath.
본 발명에 따르면, 반도체 소자에 적합한 측면 프로파일을 갖는 폴리실리콘막에 대한 식각을 구현할 수 있다.According to the present invention, it is possible to implement etching for a polysilicon film having a side profile suitable for a semiconductor device.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
당 명세서에서 말하는 폴리실리콘막은 가장 넓은 의미로 사용하고 있으며 특정 패턴인 게이트 패턴만을 한정하는 것이 아니다.The polysilicon film used in this specification is used in the widest sense and does not limit only the gate pattern which is a specific pattern.
도 4 내지 도 6은 본 발명에 의한 폴리실리콘막의 습식식각 방법을 설명하기 위해 도시한 단면도들이다.4 to 6 are cross-sectional views for explaining a wet etching method of a polysilicon film according to the present invention.
도 4를 참조하면, 반도체 기판(100)에 활성영역을 정의하고, 산화공정(oxidation)을 이용하여 게이트 산화막(102)을 1000Å 미만으로 형성한다. 이어서, 상기 게이트 산화막(102) 위에 게이트 전극으로 사용될 폴리실리콘막(104)을 약 6000Å의 두께로 적층(deposition)한다. 상기 폴리실리콘막(104) 위에 사진 공정을 위한 포토레지스트 막을 도포하고 현상(development) 공정을 진행하여 상기 폴리실리콘막(54)의 일부를 노출시키는 포토레지스트 패턴(106)을 형성한다.Referring to FIG. 4, an active region is defined in the semiconductor substrate 100, and the gate oxide layer 102 is formed to be less than 1000 kV by using an oxidation process. Subsequently, a polysilicon film 104 to be used as a gate electrode is deposited on the gate oxide film 102 to a thickness of about 6000 Å. A photoresist film for a photolithography process is applied on the polysilicon film 104 and a development process is performed to form a photoresist pattern 106 exposing a portion of the polysilicon film 54.
도 5를 참조하면, 상기 포토레지스트 패턴(106)에 대한 하드베이크(hard bake) 공정을 진행하여 포토레지스트 패턴(106)을 경화시키고, 디스컴(DESCUM) 공정을 진행하여 현상공정에서 제거되지 않은 미량의 포토레지스트를 제거한다. 이어서, 상기 포토레지스트 패턴을 식각마스크로 하부의 폴리실리콘막(104)을 습식식각하여 폴리실리콘 패턴(108)을 형성한다. 본 발명에 의한 습식식각은 불산과, 질산과 순수한 물이 혼합된 식각액(etchant)을 사용하여 진행한다. 이때 식각액의 혼합비는 불산: 질산: 순수한 물이 1: 50: 25의 비율로 혼합된 용액을 식각조(bath)에 넣어서 사용하고, 식각액의 온도를 24±2℃의 범위로 설정하고, 식각액은 순환(circulation)시키고, 식각될 반도체 기판이 담긴 캐리어(carrier)를 흔들어 주면서 습식식각을 진행하는 것이 적합하다. 본 발명에 의한 습식식각은 식각종말점에서 식각을 중단하지 않고 약 140∼150%의 범위로 오버에칭을 진행하는 것이 적합하며, 이를 고려할 때 식각시간은 폴리실리콘막(104)의 두께에 따라 차이가 있으나, 6000Å인 경우 약 115±5초의 범위에서 식각을 진행하는 것이 적합하다. 이어서, 상기 습식식각이 완료된 반도체 기판을 질산과 불화암모늄이 10:1의 비율로 혼합된 액조에 3±2초간 담굼처리(DIP)하여 상기 습식식각에서 발생한 찌꺼기를 제거한다. 이때, 액조의 온도는 31±1℃의 범위로 조정하고, 역시 질산과 불화암모늄이 혼합된 용액을 순환시키면서 담굼처리를 진행하는 것이 적합하다.Referring to FIG. 5, a hard bake process is performed on the photoresist pattern 106 to cure the photoresist pattern 106 and a DESCUM process is not removed in the developing process. Remove trace photoresist. Subsequently, the polysilicon pattern 108 is formed by wet etching the polysilicon layer 104 below using the photoresist pattern as an etching mask. The wet etching according to the present invention is performed using an etchant in which hydrofluoric acid, nitric acid and pure water are mixed. At this time, the mixing ratio of the etching solution is a solution of hydrofluoric acid: nitric acid: pure water in a ratio of 1: 50: 25 in the bath (bath), the temperature of the etching solution is set to a range of 24 ± 2 ℃, the etching solution is It is suitable to perform the wet etching while circulating and shaking a carrier containing the semiconductor substrate to be etched. Wet etching according to the present invention is suitable to proceed over-etching in the range of about 140 to 150% without stopping the etching at the end of the etching, in consideration of this, the etching time is different depending on the thickness of the polysilicon film 104 However, in the case of 6000Å, it is appropriate to proceed with etching in the range of about 115 ± 5 seconds. Subsequently, the wet substrate is immersed for 3 ± 2 seconds in a liquid bath in which nitric acid and ammonium fluoride are mixed at a ratio of 10: 1 to remove debris generated by the wet etching. At this time, it is suitable to adjust the temperature of the liquid tank to the range of 31 +/- 1 degreeC, and to carry out a immersion process while circulating the solution which mixed nitric acid and ammonium fluoride again.
도 6을 참고하면, 상기 담굼처리(DIP)가 끝난 반도체 기판에 에칭(Ashing) 공정을 진행하여 포토레지스트 패턴(106)을 제거하고, 이어서 황산세정(H2SO4cleaning) 공정을 진행함으로써 본 발명의 일 실시예에 의한 폴리실리콘막 식각공정을 완료한다.Referring to FIG. 6, an etching process is performed on the semiconductor substrate after the immersion treatment (DIP) to remove the photoresist pattern 106, and then a sulfuric acid washing (H 2 SO 4 cleaning) process is performed. Complete the polysilicon film etching process according to an embodiment of the present invention.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.
따라서, 상술한 본 발명에 따르면 다음과 같은 효과를 도출할 수 있다.Therefore, according to the present invention described above, the following effects can be derived.
첫째, 폴리실리콘으로 된 게이트 전극 패턴에 대한 측면 프로파일을 종래의 30∼80%에서 80∼90%로 개선할 수 있다. 둘째, 폴리머 및 파티클의 발생을 억제하여 후속공정에서 반도체 소자의 신뢰성(reliability)을 향상시킬 수 있다. 셋째, 종래의 등방성 건식식각인 경우에 생산성이 시간당 18매 내외로 떨어졌으나, 본 발명에 의하면 이를 900매 내외로 올려서 획기적으로 생산성을 향상시킬 수 있다. 넷째, 종래의 등방성 건식식각 공정에서는 폴리실리콘막과 게이트 산화막의 식각선택비가 3:1 정도여서 게이트 산화막에 대한 손상(damage)이 발생할 수 있었으나, 본 발명에서는 40:1로 안정적이 됨으로써 게이트 산화막에 대한 손상 문제를 해결 할 수 있다.First, the side profile for the gate electrode pattern made of polysilicon can be improved from 30-80% to 80-90%. Second, it is possible to suppress the generation of polymers and particles to improve the reliability of the semiconductor device in a subsequent process. Third, in the case of the conventional isotropic dry etching, the productivity dropped to about 18 sheets per hour, but according to the present invention, the productivity can be improved by raising it to about 900 sheets. Fourth, in the conventional isotropic dry etching process, the etching selectivity of the polysilicon film and the gate oxide film is about 3: 1, so that damage to the gate oxide film may occur. However, in the present invention, the gate oxide film is stable at 40: 1. Can solve the problem of damage.
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980032007A KR20000013247A (en) | 1998-08-06 | 1998-08-06 | Wet etching method of polysilicon |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980032007A KR20000013247A (en) | 1998-08-06 | 1998-08-06 | Wet etching method of polysilicon |
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| KR20000013247A true KR20000013247A (en) | 2000-03-06 |
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| KR1019980032007A KR20000013247A (en) | 1998-08-06 | 1998-08-06 | Wet etching method of polysilicon |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030057180A (en) * | 2001-12-28 | 2003-07-04 | 동부전자 주식회사 | A Photo Resist Removal Method by Inserting an Auxiliary Layer |
| KR20130079151A (en) * | 2011-12-26 | 2013-07-10 | 후지필름 가부시키가이샤 | Method of etching silicon, silicon etchant used in the same, and kit thereof |
| KR20180067922A (en) | 2016-12-13 | 2018-06-21 | 동우 화인켐 주식회사 | Composition for manufacturing polysilicon etchant and polysilicon etchant comprising the same |
-
1998
- 1998-08-06 KR KR1019980032007A patent/KR20000013247A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030057180A (en) * | 2001-12-28 | 2003-07-04 | 동부전자 주식회사 | A Photo Resist Removal Method by Inserting an Auxiliary Layer |
| KR20130079151A (en) * | 2011-12-26 | 2013-07-10 | 후지필름 가부시키가이샤 | Method of etching silicon, silicon etchant used in the same, and kit thereof |
| KR20180067922A (en) | 2016-12-13 | 2018-06-21 | 동우 화인켐 주식회사 | Composition for manufacturing polysilicon etchant and polysilicon etchant comprising the same |
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