KR20000013207A - Heterojunction bipolar transistor manufacturing method - Google Patents

Abstract

PURPOSE: Regarding a heterojunction bipolar transistor (HBT) composed of a compound semiconductor, base resistance, junction capacitance between the base and the collector, parasitic resistance of the outer base, and an element smoothing problem which affects the element electric quality, especially the maximum resonance frequency are improved and with a higher speed and high frequency quality of HBT is improved. CONSTITUTION: In the normal HBT structure, the emitter electrode (8) is formed and the emitter cap layer (7) and the emitter layer (6) are removed by turns by the wet chemical mesa etching to expose the base layer (5) surface. The base layer (5) and the collector layer (4) are removed by the wet chemical mesa etching method to expose the sub-collector layer (3) surface. The collector electrode (9) is formed on the sub-collector layer (3) with the emitter electrode (8). The silicon nitride film (SiN) (10) is attached and the sub-collector layer (3) and the buffer layer including part of the panel (1) are removed with etching to have pure mesa form. With the SiN layer (10) protecting emitter electrode (8) and collector electrode (9) as a mask, the insulation epi-layer (11) is grown again up to the height of original sub-collector layer (3). The SiN layer (10) attached with a sensitive film as a mask layer is etched to expose the base layer (5) side and the collector layer (5) side, and the outside base layer (12) is grown and formed in the same conditions as the original base layer (5) growth. The base ohmic electrode (13) is attached and lifted off and the unnecessary re-grown base area is removed by etching with the base ohmic electrode (13) as the mask layer. The SiN film (10) used as mask for base re-growth is removed. From this point on the HBT is manufactured using the conventional method. The HBT high-speed quality and the process reliability is improved.

Description

Fabrication method of heterojunction dipole transistor

The present invention relates to a method for manufacturing a heterojunction bipolar transistor (hereinafter referred to as HBT) made of a compound semiconductor.

Conventional HBT is a high-speed and ultra-high frequency device, and is applied to various digital and analog communication circuits. Recently, in case of AlGaAs / GaAs HBT, the cutoff frequency (f _T ) and the maximum resonance frequency (f _max ) are each 100 Hz or more, and InP / In the case of InGaAs HBT, more than 200 microseconds have been published.

Although HBT has inherent high speed characteristics compared to other semiconductor devices, in order to maximize these advantages, first, the time required for electrons to pass through the base and the collector depletion layer must be shortened. Second, the emitter, base, and collector ohmic resistance. And process technology to reduce emitter-base capacity, base-collector capacity, and various parasitic factors.

In a simple quantified way f _max = (f _T / 8πR _B C _BC ) ^1/2 Can be expressed as R _B Bass resistance, C _BC Denotes the base-collector contact capacity.

As can be seen from the above equation, the lower the base resistance and the base-collector contact capacitance, the more important the high speed characteristics of the circuit. f _max Can be decisively improved.

As a specific process technology for this, self-alignment between the emitter and the base, ion implantation isolation of the outer base region, regrowth of the outer base, and overcutting of the outer base region are used. come.

Emitter-based self-alignment technology has recently been published in more than a hundred patents and papers to minimize parasitic resistance by minimizing the distance between emitter and base electrodes as reproducibly as possible.

The most common method, which was used in the early stages of HBT development in Rockwell, USA, is to define the inverse mesa shape by using the crystal orientation of the substrate when the emitter mesa is etched to the base surface. Inducing the coating to break causes the base electrode to the emitter to self-align.

Although this method is simple, it has a high possibility of generating leakage current between the emitter and the base depending on the reproducibility of the process.

As a more sophisticated method, there is a self-aligning method using an insulating sidewall mainly developed and used in NTT, NEC, etc. of Japan.

That is, after the emitter mesa etching, the dielectric insulating film is deposited on the entire surface of the wafer, and the etching is performed until the insulating film on the base substrate is removed by dry etching with strong vertical directivity, and the insulating sidewall film remains around the emitter electrode. When the base electrode is deposited at, it is isolated from the emitter by the thickness of the sidewall film and is self-aligned.

The above method is a very powerful method to reduce external parasitic resistance when the uniformity of etching is ensured and is widely used, but there is a risk of lattice damage to the base layer during dry etching to form sidewall film, and special surface treatment The needs of the course are raised.

The ion implantation isolation technology for the outer base region is based on the emitter electrode as a mask layer, which is typically used for the outer base layer doped with a high concentration of p-type impurities and the outer collector layer doped with n-type impurities. Significant achievements in research and development are intended to drastically reduce the effective bonding capacity between the base and the collector by accelerating the proton ions (H ⁺ ), helium (He ⁺ ) and boron ions (B ⁺ ) in the electrical channels. Is expected, but an activation heat treatment is required to recover the damage of the base surface to deposit the base ohmic electrode, which carries risks for commercial use as it may destroy the steep interface of the entire epistructure.

In the case of external base regrowth, there are planar regrowth and lateral regrowth, and its purpose is to increase the doping concentration by 10 ²⁰ ~ 10 ²¹ ㎝ ^-3 separately from intrinsic base and increase its thickness. It is to lower the bass resistance by thickening.

The planar regrowth method has an electrode contact structure with good planarization, and the regrown base layer is positioned between the base electrode and the existing base layer to serve as a contact layer on both sides.

Lateral regrowth is a structure in which the regrown base layer serves as the outer base and is in contact with the lateral cross section of the intrinsic base.

However, while these methods are effective for lowering the base resistance, they cannot be said to have a significant effect on lowering the capacity between the base and the collector.

The overetching technology of the outer base region is a method developed by the University of Michigan, USA, which defines the emitter and the base region, and then uses the high selective etching characteristics of the collector layer of the base layer during the base mesa etching up to the sub-letter layer. By inducing the side of over to be etched inward to reduce the effective base-collector contact capacity, the device characteristics are highly dependent on the reproducibility and uniformity of the process.

Prior patents (Korean Patent No. 91106) using such a flat base regrowth have a problem in that contact capacity is difficult to reduce because an inverted mesa type emitter is used as a mask.

In addition, US Patent No. 5698871 discloses that it is possible to improve the maximum resonant frequency by reducing the base-collector capacity (C _JC ) similarly as the base-collector capacity is reduced by the etching method of the external base. There was a difficult problem.

In addition, [US Pat. No. 5,672,522] has a problem that it is difficult to improve the maximum resonance frequency by reducing the base-collector capacitance (C _JC ).

As a preceding paper, [Juan-Wu Wang, Kwon, Ho V. 68, Iss. 6, 98.2.5] has a problem that it is impossible to simultaneously improve the parasitic resistance and base-collector junction capacitance component by fabricating a device using a complex ion implantation process.

In another preceding article, [T. Kumar, et al., Vol., No. V. 83, Iss. 4. 98.2.15] has a problem that it is difficult to improve the maximum resonance frequency by reducing the base-collector capacity (C _JC ).

In addition to the special device fabrication process technology mentioned above, a conventional fabrication method that was used mainly in HBT fabrication in the related art is illustrated in FIGS. 1A to 1C.

FIG. 1A illustrates that the AuGe-based or heat-resistant alloy-based metal is formed of the emitter electrode 13 on the HBT epitaxial substrate as shown in FIG. 2A, and FIG. 1B is a mesa-etched emitter cap layer 7 and the emitter layer 6. A base ohmic electrode 14 having a material different from that of an emitter electrode formed on the base layer 5 is shown. FIG. 1C illustrates a mesa etching of the base layer 5 and the collector layer 4 on the subcollector layer 3. After the collector ohmic electrode 15 is formed of a material different from the emitter electrode and the base electrode, the device isolation mesa is etched.

In order to solve the above problems, the present invention provides a base resistor, a junction capacitance between the base and the collector, a parasitic resistance in the external base, device planarization problems, etc., which have a significant influence on the electrical characteristics of the device, in particular, the maximum resonance frequency (f _max ). It is aimed at improving the high speed and high frequency characteristics of HBT by remarkably improving.

As multimedia communication service develops rapidly and the necessity for distributing high-quality information at high speed increases, advanced information communication system that can handle this is also rapidly developing. Therefore, high-speed and ultra-high frequency of core electronic devices mounted in the system It is inevitable.

HBT devices using compound semiconductors such as gallium arsenide and indium phosphorus have various functions because they have advantages such as high speed and high frequency characteristics, high current driving capability, high breakdown voltage, signal linearity, and uniform operating voltage. It is actively applied as.

HBT devices are fundamentally dependent on the resistance characteristics of the emitter, base, and collector ohmic contacts and the contact capacitance between the heterojunctions, and in particular, it is decisively determined by the base resistance and the capacity between the base and the collector. Because of the impact, it is very important to develop a new process method to realize the high performance characteristics of HBT and to make reliable device fabrication.

Therefore, in the present invention, the planarization is improved by epilayer regrowth of the device isolation region at the time of fabrication of the HBT made of the compound semiconductor, the outer base region is formed by the regrowth of the base, and the base electrode can be self-aligned to the emitter. The parasitic resistance was suppressed as much as possible, and although the base resistance can be reduced by the large base electrode area, the capacitance between the base and the collector can be reduced to improve the process efficiency and improve the performance of the HBT device.

1A to 1C are cross-sectional views of manufacturing processes of a heterojunction dipole device according to the prior art;

Figure 2a to 2n is a cross-sectional view of the manufacturing process of the present invention.

* Explanation of symbols for main parts of the drawings

1: Compound Semiconductor Substrate 2: Buffer Layer

3: subcollector layer 4: collector layer

5: base layer 6: emitter layer

7: emitter cap layer 8: emitter electrode

9 collector electrode 10 silicon nitride film mask layer

11: Regrowth Insulation Epilayer 12: Regrown Insulation Base Layer

13 base electrode 14 silicon nitride film protective layer

15: wiring metal 16: electrical insulation area

In order to achieve the above object, the present invention, after manufacturing the epi substrate of the conventional HBT structure, forming an emitter electrode on the pure mesa etched shape, and again forming a collector electrode on one side of the pure mesa etched shape A second process of regrowing an insulating epitaxial layer by recycling an oxynitride film used as a mask for mesa etching on the device isolation region formed by the mesa etching, and opening one side of the base layer of the epi substrate A third process of regrowing the layer, a fourth process of forming a base electrode on the upper surface of the outer base epitaxial layer and removing unnecessary external base regions using the electrode, and removing the oxynitride film (SiN) used for the epi regrowth After that, a silicon insulating film is applied to the entire surface of the wafer where the emitter electrode, the collector electrode, and the base electrode have been formed. It characterized in that it comprises a fifth step of forming a metal wiring.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2N are cross-sectional views of the manufacturing process of the present invention, and show the manufacturing process of the device devised by the present invention, more specifically, the heterojunction dipole transistor (HBT).

FIG. 2A shows an epitaxial structure of a conventional HBT formed on a compound semiconductor substrate 1 such as gallium arsenide (GaAs) or indium phosphorus (InP) that is electrically semi-insulating.

Here, the HBT epi substrate may be manufactured through various growth methods such as MBE (Molecular Beam Epitaxy) or MOCVD (Metal-Organic Chemical Vapor Deposition), and in the present invention, on the wafer substrate 1, the same method as the general HBT structure is performed. After the buffer layer 2 is grown, it grows while stacking toward the surface in the order of the subcollector layer 3, the collector layer 4, the base layer 5, the emitter layer 6, and the emitter cap layer 7. This completes the HBT epistructure used in the present invention.

Subsequently, the emitter electrode 8 is formed as shown in FIG. 2B, and the emitter cap layer 7 and the emitter layer 6 are sequentially formed by mesa etching by a wet chemical method. It is removed so that the surface of the base layer 5 is exposed.

In this case, as the emitter electrode material, a heat-resistant metal material that can withstand high temperature heat treatment upon regrowth of the base layer, for example, tungsten (W), tungsten silicon (WSi), and tungsten nitride (WN) should be used.

In FIG. 2C, the base layer 5 and the collector layer 4 are sequentially removed by the wet mesa etching method so that the surface of the subcollector layer 3 is exposed.

In this case, a chemical solution composed of phosphoric acid (H ₃ PO ₄ ) / hydrogen peroxide (H ₂ O ₂ ) / deionized water is used to have a positive mesa form in favor of the base regrowth after mesa etching. .

In FIG. 2D, the collector electrode 9, which is also made of a heat resistant electrode material, is formed on the subcollector layer 3 in the same manner as the emitter electrode 8.

Subsequently, as shown in FIG. 2E, a silicon nitride film (SiN) 10 is deposited on the front surface of the waiter, and the sub-collector layer includes a portion of the substrate 1 to have a net mesa shape when electrical devices are separated using the mask layer. 3) and a shape in which the buffer layer 2 was completely etched and removed are shown in FIG. 2F.

Fig. 2G shows a part of the characteristic process steps of the present invention, wherein the SiN layer 10, which is already used for the element isolation etching protecting the emitter electrode 8 and the collector electrode 9, is again used as a mask. When the insulating epitaxial layer 11 of the same material is regrown to the height of the original sub-collector layer 3, the planarization which can increase the reliability of the metallization process can be substantially improved as shown in FIG. 2G.

Another important point besides planarization is that the side of the subcollector layer is already covered by the insulating regrowth epi layer so that the bonding capacity with the collector layer due to the outer base layer is relatively lower than when the subcollector layer is exposed. Can be.

After etching the SiN film 10 previously deposited by the plasma discharge of the freon gas using the photoresist film as a mask layer so that the side surfaces of the base layer 5 and the collector layer 4 are exposed as shown in FIG. 2H, the original base layer is etched. (5) Regrowth under the same growth conditions, i.e., impurity doping concentration and thickness, results in the formation of the outer base layer 12 as shown in FIG.

Since the regrowth outer base structure uses lateral bending, the base base ohmic resistance is ultimately lowered by allowing a wide base electrode to be contacted even with a smaller contact capacitance than the conventional method.

Subsequently, when the base ohmic electrode 13 is deposited and lifted off, self-alignment is performed from the emitter region by the already formed SiN mask layer 10 as shown in FIG. 2J.

2K illustrates a state in which unnecessary regrowth base regions are etched away using the base ohmic electrode 13 as a mask layer.

FIG. 2L is a representative view of the present invention, after sequentially forming the emitter electrode 8, the collector electrode 9, the regrowth insulating layer 11 for planarization, the regrowth base 12, and the base electrode 13 The fabrication of individual HBT devices including the electrical separation between devices by removing the SiN film 10 used as a mask for regrowth is completed.

Subsequently, after the SiN protective film 14 is deposited on the entire surface of the wafer as shown in FIG. 2M according to a conventional method, the metal between the emitter electrode 8, the collector electrode 9, and the base electrode 13 and the wiring metal 15 are separated. If the contact window for the electrical connection is defined by dry etching, and the wiring metal 15 is formed by the lift-off method, the fabrication of the HBT, the ultrafast compound semiconductor device according to the present invention, is completed as shown in FIG. 2N.

The compound semiconductor HBT completed by these processes is active in various information and communication fields such as high speed broadband optical communication system, satellite communication system such as LMDS (Local Multipoint Distribution Service), as well as mobile communication fields such as mobile phones and digital and analog application circuits. It is applied.

In addition, it is possible to manufacture a communication component with high speed and high frequency characteristics of the communication component element.

When utilizing the technology according to the present invention can make a technical contribution to the realization of ultra-high speed characteristics by improving the bonding capacity between the emitter and the base, the base ohmic resistance, the external base parasitic resistance, etc. In addition, compared to the existing manufacturing method, the planarization is additionally achieved, and thus, an efficient and reliable manufacturing process is possible.

Claims (6)

In the method of manufacturing a heterojunction bipolar transistor (HBT), After fabricating an epitaxial substrate having a conventional HBT structure, an emitter electrode is formed, followed by pure mesa etching to the upper part of the base layer, followed by pure mesa etching to the upper part of the subcollector layer, thereby forming a collector electrode on one side of the pure mesa-etched shape. 1 course; Re-growing the insulating epitaxial layer by recycling an oxynitride film used as a mask for mesa etching on the device isolation region formed by the mesa etching; A third process of opening one side of the base layer of the epi board to regrow the outer base epi layer; Forming a base electrode on an upper surface of the outer base epitaxial layer and using the electrode to remove an unnecessary outer base region; Removing the silicon nitride film (SiN) used for the epi regrowth, and then applying a silicon insulating film to the entire surface of the wafer on which the emitter electrode, the collector electrode, and the base electrode have been formed; A method of manufacturing a heterojunction dipole transistor, characterized in that. The method of claim 1, wherein the first process is A first step of growing a buffer layer on the HBT wafer substrate and then growing while stacking the subcollector layer, the base layer, the emitter layer, and the emitter cap layer in order toward the surface to produce an HBT epistructure; After fabrication of the epi structure, an emitter electrode was formed on the substrate, and then, as a mask, phosphoric acid (H ₃ PO ₄ ) / hydrogen peroxide (H ₂ O ₂ ) / pure water (Deionized Water) to have a pure mesa shape for base growth. A second step of exposing the surface of the base layer by sequentially removing the emitter cap layer and the emitter layer by mesa etching using a chemical solution consisting of; And a third step of forming a collector electrode made of a heat resistant electrode material in the same way as the emitter electrode on the subcollector layer. The method of claim 1, wherein the second process After depositing a silicon nitride layer (SiN) layer on the entire surface of the wafer and the first device to completely remove the sub-collector layer and the buffer layer to include a portion of the substrate to have a net mesa shape when the separation between electrical devices using a mask as a mask Steps; And a second step of regrowing the insulating epitaxial layer of the same material as the substrate to the height of the original subcollector layer, using the silicon nitride film used for the element isolation etching protecting the emitter electrode and the collector electrode as a mask again. A method of manufacturing a heterojunction dipole transistor. The method of claim 1, wherein the third process is Etching the deposited silicon nitride film used for the device isolation etching using the photoresist film as a mask layer by plasma discharge of a freon gas to expose side surfaces of the base layer and the collector layer; And etching the base layer and the collector layer to form an outer base layer by regrowing in the same manner as the impurity doping concentration and thickness, which are the growth conditions of the original base layer. The method of claim 1, wherein the fourth process Depositing and lifting off the base ohmic electrode after the regrowth outer base layer is formed to self-align from the emitter region through a silicon nitride film already formed; And a second step of etching and removing unnecessary regrowth base regions by using the base ohmic electrode as a mask layer. The method of claim 1, wherein the fifth process Forming a base ohmic electrode after the base layer regrowth and lifting off to self-align the base electrode from the emitter region by the silicon nitride film; Etching the unnecessary regrowth outer base region using the base electrode as a mask layer, and then removing the SiN film used as a mask for device isolation mesa etching and epi regrowth; After removing the SiN film used as a mask, the SiN protective film was deposited on the entire surface of the wafer, and then the emitter electrode, the base electrode, and the contact window for electrical connection between the metal and the wiring metal were defined by dry etching, and the wiring metal was formed by the lift-off method. Method of manufacturing a heterojunction dipole transistor, characterized in that consisting of a third step.